SU1746401A2 - Method of and device for recording or transmitting digital data using double-frequency coding - Google Patents

Description

the marker combination is additionally formed and deployed m times, corresponding to the weight of the L-bit code of the information flag, before each information combination. To implement this method, an L-bit subtractive binary counter, a second decoder, an OR-NOT element, a third D-trigger, a third and fourth AND elements, and a third decoder are added to a known recording or transmission device, and L -discharge binary counter, fifth D-flip-flop and third and fourth inverters. 2 sp.f-ly, 3 Il.

The invention relates to a technique for recording or transmitting digital information with dual-frequency coding using marking information combinations to provide asynchronous reading of information from a recording medium or receiving information from a channel, and is an improvement on the known technical solution of ed. St. No. 1645993.

The purpose of the invention is to increase the information capacity of the carrier during recording or the transmission rate of information in the channel during transmission by eliminating the use of the alphabet of the source of information for recording on the carrier or transmitting through the communication channel the signal of the information feature,

FIG. 1 shows a functional block diagram of a signal signal generation unit of a device for recording or transmitting two-frequency coded N-bit information combinations; in fig. 2 - time diagram of the operation of the recording device; in fig. 3 is a temporary diagram of the operation of the recording device when implementing a known method.

The node of formation of the signal of the information sign of a recording or transmission device of two-frequency-coded M-bit information combinations consists of an L-bit subtractive binary counter 1, the information inputs Di - D2 of which are connected to the information buses of information signs, decoder 2, the inputs of which are connected to the corresponding outputs 1 of the counter 1, the element OR NOT 3, D-flip-flop 4, the input S of the installation in 1 which is connected to the inverse output of the D-trigger 5 and the input R of the installation in O L-bit calculus melting binary counter 1, information input D to the output of the decoder 2 and the first input of the element OR NOT 3, and input Gating to the output of the decoder 6, element 7, the first input of which is connected to the output of the element OR NOT 3 and input R set to O

D-flip-flop 4, and the output with the third input of the element OR 8 and the counting input -1 of the subtractive counter 1, the decoder 9, the inputs of which are connected to the corresponding

outputs 1 - K-bit counter 10, and the output - with the second input element And 7, element 11, the first input of which is connected to the output of the D-flip-flop 4, the second input - to the output of the potential-pulse cell i2, and the output - to the second input of the element OR-NOT 3 and to the input C of recording information into counter 1 via information inputs DI - D2 and is the output of Acknowledgment 2, counter 13, the C input of which is the input aa of the device, the output of the second bit is connected to C -input counter 10, and the output of the first discharge-with the input element NOT 14, the output of which is connected to the C-input trigger a 5, element OR 15, the first input of which

connected to the output of a potential pulse cell 12, the second input to the inverse “output of the trigger 5, and the output to the $ 2 input of the counter 13 and R to the input of the counter 10.

Method using a recording device

implemented as follows.

After turning on the power, in the absence of a Start signal, the inverse output of the trigger 5 sets a high potential (signal g), which is fed to the input R

installation in About counter 1, set it to its original state. As a result, a high potential (signal O) appears through the output of the decoder 2 through the element OR-NOT 3, to the first input of the element 7, blocking (signal H) the counting input -1 of the subtracting counter 1 and to the input R of the installation in About trigger 4.

In addition, the high potential signal, from the inverse output of the trigger 5, is fed to the input S of the D-flip-flop 4, sets it to the excited state (signal p of a single value).

When the Start signal appears at the inverse output of D-flip-flop 5, a low potential is established, which is fed to the input of the installation in O of the subtractive counter 1 and to the input of flip-flop 4, removing the blocking from them.

In addition, a low potential signal from the inverse output of the trigger 5 through the second element OR 8 at its second input 2 excites a potential-pulse cell 12, forming a pulse signal Confirmation 1, from the output of the potential-pulse cell 12. The signal through the And 11 element of its second input 2, when there is a high potential at its first input 1, enters the buffer register of the information combination for the time of its sweep (signal C), having buffered the information combination to be scanned and requests the following formational combinations and, accordingly, the information embedded in it, the combination of feature code.

In addition, from the output of the element 11, a pulse signal (signal C) is fed to the input C of the information recording in subtractive counter 1, allowing the code of the information flag to be written into bits D - DL of the counter 1. Buffering the information flag in the counter 1 causes the appearance of a low potential at the output of the decoder 2, and, consequently, at the first input 1 of the element OR-NOT 3, which in the interval of the absence of a pulse at the output of the element 11 and therefore at the second input 2 of the element OR-NOT 3, provides the appearance of high the output potential of the element OR NOT 3, prokidyval trigger 4 and unlocks the AND gate 7. This provides the start conditions form a single m-scan and the marker signal combinations corresponding to the weight of feature code. The overturning of the trigger 4 causes the appearance of a low potential at its output, which enters the first input 1 of the element 11 and blocks it.

During the formation and sweep of the marker combination signals, a high potential signal (signal M) appears at the switching interval at its inputs of the third marker discharge address (signal M), which through element 7 arrives at counting input -1 of the subtracting counter 1 changing its back front its state, while at the same front a potential-pulse cell 12 is excited through the element OR 8, at the output of which a pulse appears (signal e) which through the element OR 15 is fed to the input R of the installation in O Cr sp-stand binary counter 10 and to the input of the second installation 8d discharge in one two-bit counter 13 causes them to their original state,

providing each time the source address when forming and scanning the signal of the next marker combination. When the initial state of the subtractive counter 1 is reached, as a result of a negative modification of the buffered combination of the feature code information in it, a high signal appears at the output of the decoder 2

5 potential (signal O), which indicates the completion of the m-one-time formation and sweep of the signals of marker combinations corresponding to the weight code of the information feature. The high potential signal from the output of the decoder 2 is fed to the first input 1 of the element OR NOT 3, blocking the element AND 7 through it, through its first input 1. That provides the conditions for the formation and sweep of the signal of the last (nP + 1) -th marker combination with the subsequent formation and scan signal information combination.

On the scan interval of the last bit of the information combination on

0, a high potential signal (signal d) appears at the output of the decoder 6, which is fed to the D-trigger 4 gate Gating, gating with its leading edge a single value of the signal (signal O) that comes from the output of the decoder 2 to the information input D -trigger 4, which leads to the appearance of a high potential signal at the output of the D-flip-flop 4, which is fed to the first input 1 of the element 11 and

0 removes a lock from it. The high potential signal from the output of the decoder 6 also enters through the OR element 8 to the input of the potential pulse cell 12, which is excited on its falling edge, to form a pulse of the signal Confirmation 1, coming through the element 11, to the input C of the information record of the counter 1, which indicates the completion of the cycle of formation and sweep of the entire complex of signals,

0 and if there is a single value of the Start signal and the beginning of the next processing cycle of the indicative and informational combinations.

Claims (2)

Invention Formula 5 1. A method of sequential recording or transmission with dual-frequency coding according to the author. St. Ms 1645993, characterized in that, in order to increase the information capacity of the carrier during recording or speed 0 transmission of information in the channel during transmission due to the exclusion of the use of the alphabet of the source of information for recording on the carrier or transmission through the communication channel of the signal of the attribute of information, the marker 5, the combination is additionally formed and deployed several times in accordance with with the weight of the multi-bit code of the information feature before each information combination. 2. A sequential recording or transmission device with two-frequency coding, characterized in that, in order to increase the information capacity of the carrier during recording or the transmission rate of information on the channel during transmission by eliminating the use of an alphabet of the source of information for recording on the carrier or transmission through a communication channel information sign, it additionally contains a subtracting counter, the information inputs of which, by the number of bits of the combinations, are connected to the information buses of the information sign, the second the encoder, the inputs of which are connected to the corresponding outputs of the detracting counter, the element OR NOT, the third D-flip-flop, the installation input in 1 of which is connected to the inverse output of the second a, LAG1LLDD / i  hHnj njHj nj4ji x 9 to    2 / w i 3 te .....- And GP GP-L. / w1 Р 3 Ирм Зрт | 2 rp g 3 / ich, B +. . l l l. l l i l i l gp l i  2p Zri V 2ri Zrt | / d, | 2rm „& Y MQ gfTl о g gJTI g gfTl ° Р Пv о I i h 1 .Г i  P I1 P P P f i i ii, i | I, I I I | ° to Lj7  TO "Lx FIG. 2 D-flip-flop and installation input into O subtracting counter, information input to the output of the second decoder and the first input of the OR-NOT element, and gate input to the output of the first decoder, the third AND element, the first input of which is connected to the output of the OR-NO element and with the installation input into the third D-flip-flop, and the output with the third input of the first element OR and the counting input of the counting counter, the third decoder, the inputs of which are connected to the corresponding outputs of the K-bit binary counter, and the output - with the second input of the third element And, and the fourth element And, the first input of which is connected to the output of the third D-flip-flop, the second input is to the output of a potential-pulse cell, and the output is to the second input of the OR-NOT element and to the information recording input to the subtracting counter by the information inputs and is the device output.  w Ј3 - @ i fg - four very much fM cviv a "is Ll J.L, R Nb j 5 QG -w "  i fg - four Ji fM cviv a "is C O. J