SU1742842A1 - Device for information compressing and processing - Google Patents

Abstract

The invention relates to the field of computing and measuring equipment and can be used in various automated systems for collecting and processing information, as well as diagnostic control. The purpose of the invention is to increase the information content and reliability of the device. The device contains analog-to-digital converter 1, differentiating element 2, first 3 second M blocks of comparison, 5 pulse generator, divider 6, driver 7 codes, counter 8, first block 9 of buffer memory, processing blocks containing the first 10, second 11, third 12, fourth 13 elements AND, trigger AND, first 15, second 16 elements of the comparison, element OR 17. The device also contains the element OR 18, the element AND NOT 19, the element AND 20, the second block 21 buffer memories. 6 Il.

Description

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with

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The invention relates to computing and measuring technology and can be used in various automated systems for collecting and processing information, as well as diagnostic control.

A device for processing and compressing information is known, which contains a register of the current sample, the information inputs of which are information inputs of the device, the output bits are connected to the information inputs of the RAM and the information inputs of the number register, the outputs of the lower bits are connected to the first information inputs of the adder , the second information inputs of which are connected to the first output of the RAM unit, the information outputs of the adder are connected to the information inputs of the node comparison with the tolerance, the output of which is connected to the first input of the first element OR, the output of which is connected to the summing input of the reversing counter, the clock input of the operating memory unit and the current input of the number register, the output of which is the first output of the device, the second output and the second information input of the register the numbers are connected respectively to the information input and output of the buffer memory block, the clock input of which is combined with the subtracting input of the reversible counter and is the first clock input of the device The control terminals of the reversible counter are connected to the first inputs of the first AND elements, the second inputs of which are the second clock inputs of the device. The outputs of the reversible counter are connected to the clock inputs of the comparison node with the tolerance.

The disadvantage of this device is its low efficiency with high dynamics of the process being measured, since an anomalous measurement can be considered a significant sampling, and with a small change in the input signal, an accumulation of error occurs due to a compromise between speed and a step of comparing the input value.

The closest to the technical nature of the present invention is a device containing an analog-to-digital converter, the input of which

five

0

is the input of the device, the pulse generator, the output of the pulse generator is connected to the input of the first

frequency divider, the output of which is connected to the control input of the analog-digital converter and to the counter input, trigger, whose output is connected to the control

the inputs of the first and second keys, the output of the analog-digital converter is connected to the input of the first block of buffer memory, the shift register, the output of which is connected to the first input of the calculator, the second input of which is combined with the input of the shift register, the output of the calculator is connected to the input of the quadrator, the output of the quadrator connected to the input of the averager, the output of which is connected to the first input of the comparator unit, to the second input of which the output of the permanent memory unit is connected, the first and second outputs of the comparator unit are connected respectively from the first and second keys, the output of the first key is connected to the summing input of the adder, the output of the second key is connected to the subtractive input

0 adder, the output of which is connected to the control input of the switch, whose information inputs are connected to the corresponding outputs of the second frequency divider, output

 the switch is connected to the control input of the shift register; the output of the second block of buffer memory is the output of the device, the third key.

tt

0 The disadvantage of the known device is its low information content, due to the inflexibility of the device, the ability to skip the anomaly in significant

5 sampling and accumulation of error with a small change in the input signal due to the step of determining a significant sample. I

. The proposed device is intended to increase the information content of the measurement information and increase its reliability due to preprocessing. .

The purpose of the invention is to increase the information content and reliability of the device.

In a device for compressing and processing information, containing

go-digital1 converter, the first input of which is the input of the device, the outputs are connected to the same and first inputs of the first block of the buffer memory, the second block of the buffer memory, the output of which is the output of the device, a pulse generator, the output of which is connected to the input of the divider frequencies, a counter, a first comparison block and an AND element, code generator, a differentiating element, a second comparison block, an AND-NOT element, an OR element and information processing blocks, each of which is performed on the AND elements, the OR element, three | - hero and comparison elements, the output of the first element I is connected to the first input of the second element I, the output of which is connected to the direct input of the third element I and to the first input of the trigger, the inverse output of which is connected to the inverse input of the third element I, direct output the trigger and the output of the third element And are connected to the first inputs of the first and second elements of the comparison, respectively, the outputs of which are connected respectively to the first and second inputs of the OR element, the output of which is connected to the first input of the fourth element AND, The outputs of the fourth elements AND information processing units are connected to the corresponding first inputs of the second buffer memory unit, the second inputs of the second elements AND information processing units are connected to the corresponding outputs of the analog-digital converter, the output of the counter is connected to the second input of the first buffer memory unit, the outputs of which are connected with the third inputs of the elements OR the corresponding information processing units, the input of the differentiating element is connected to the input of the device, the output is connected to the inputs of the gene pulse generator, the first and second comparison blocks, the first output of the first comparison block is connected to the first input of the OR element and the first direct inputs of the first AND elements of all information processing units, the second output of the first comparison block is connected to the first input of the AND element whose output is connected with the input of the counter, the second inputs of the triggers and the second inputs of the first elements And channels of information processing,

15

20

25

The first input of the NAND element and the second input of the analog-digital converter are combined and connected to the output of the pulse generator, the output of the frequency divider is connected to the second inputs of the fourth elements AND channels of information processing, the second input of the second buffer memory block

10 and the input of the code generator, the outputs of which are connected to the second inputs of the comparison elements of the corresponding information processing channels, the output of the second comparison unit is connected to the inverse inputs of the first AND elements of the information processing units and to the second input of the OR element, the output of which is connected to the second input of the AND-NOT element whose output is connected to the second input of the element I.

The proposed device, in comparison with the known, is characterized by the presence of a differentiating element, a comparison unit, a code generator, an AND-NOT element, an OR element, processing units, each of which contains four I9 elements OR element, two comparison elements, a trigger and their connections with the rest circuit elements. However, when they are introduced in this connection with the rest of the circuit elements in the device for compressing and processing information, these blocks exhibit new properties,

35 which leads to an increase in the information content and reliability by tracking the dynamics and eliminating the anomalous values of the input signal. Figure 1 shows the functional diagram of the device; Fig. 2 illustrates the implementation of an input signal with low dynamics; FIG. 3 is a diagram of the first comparison unit and timing diagrams of its operation MB1; FIG. A — signals

45 at the inputs of the corresponding elements of the device; figure 5 - the structure and features of the differentiating element; figure 6 - the structure of the coder codes,

50 Device - (Fig. 1) contains an analog-to-digital converter 1 (ADC), differentiating element 2, first 3, second k blocks of comparison, generator 5 of pulses, divider 6,

55 shaper 7 codes, counter 8, first block 9 of buffer memory, processing blocks containing the first 10, second 11, third 12, fourth 13 elements And, trigger 1, first 15,

the second 16 elements of the comparison, the element OR 17, the device also contains the element OR 18, the element AND-NOT 19, the element AND 20, the second block 21 of the buffer memory. Shaper 7 contains an estimator 71 and a block of permanent memory, the read input of which is connected to the counting input of the counter 7.1 and the output of the divider 6, the outputs of the counter 7.1 are the address inputs of the block 7.2.

ADC 1 with a control input can be implemented according to a known scheme, differentiating element 2 - according to a known scheme, with the addition, generator 5 can be performed on the basis of a Schmitt precision trigger, in which the input signal arrives at the output, block 3 is a two-threshold comparator, block C - the well-known block 7.2 can be performed on the MKS K 155 RU 2, comparison elements 15 and 16 are comparators, where for each bit a known scheme can be used, transmitting the output of the highest non-coincident p sp rows. To compare k- and 5-bit numbers, an IC is released, for example, SN, counter 8 is an asynchronous counter for all, with the higher-order pulse going to block 9 and at the same time to -. installation input in About counter 8.

The device input is connected to the first input of the ADC 1 and the input of the differentiating element 2, the output of which is connected to the inputs of blocks 3 and ktgenerator 5 whose output is connected to the second input of the ADC 1, and through divider 6 to the input of block 7 and the second input of block 21, output expensive is the output of the device. The group of outputs of the ADC 1 is connected to the first (informational) inputs of the unit E, the second input of which is connected to. the output of the counter 8, the counting input of which is connected to the output of the element AND 20 The output of the generator 5 is also connected through the element IS-NOT 19 to the second input of the element AND 20, the first input of which is connected to the second output of the block 3 the first output of which through the element OR T8 is connected to the second input of the element AND-NOT 19. The output of unit 1 is connected to the second input of the element OR 18, as well as to the inverse

y.

-

d

15

20

25

the input element And 10 of each processing unit

The second, first direct inputs, outputs, and elements of the And 10 element are connected respectively to the output of the generator 5, the first output of block 3, and through the And 11 element to the information first input of the trigger 1A, direct output

10 which through the comparison element 15, the elements OR 17 AND 13 is connected to the corresponding first input of the block 21. The corresponding output of the A / D converter 1 is connected to the second input of the element 11, the output of which is connected through the element 12, the element 16 to the second input of the element OR 17o Third input the element OR 17 of each processing unit is connected to the corresponding output of the block 9. The second input of the And 10 element is also connected to the second (clocking) input of the trigger 1, the inverse output of which is connected to the inverse input of the And 12 element. The output of the divider 6 is connected to the second inputs elements And 13 processing units, the second inputs of elements 15 and 16 of which, moreover, are connected about the corresponding outputs of the driver 7. Device

30 allows, in accordance with the dynamics of the input process, to change the sampling rate, as well as to exclude anomalous measurements and accumulated errors at low dynamics of the process.

The device works as follows.

To the input of the device for compressing and processing information, analog signals from the sensors are received in the form of a time varying voltage. For simplicity of describing the operation of the device, we assume that only one sensor is serviced, which

45 generates a continuous in time analog signal U (t). Then, when power is supplied to the device, its blocks are set to the initial state, in which the counter 8 pulses,

50 block 9, the elements 15 and 16 of the comparison are cleared, the generator 5 starts working immediately when the device is turned on. The analog signal U (t) arriving at the device input acts simultaneously on ADC1, the sampling frequency of which depends on the control voltage, and on the differentiating element 2. The last one

It follows the rate of voltage variation from the sensor, and performs the function U / clt. Obtained at the output of the differentiating element

2, the voltage is applied simultaneously to the generator 5, where, depending on the magnitude of the incoming voltage, the frequency of the generated clock signal changes, as well as blocks

3 and k comparisons, which are the comparators.

The block center compares the incoming value dU / dt- with the value of the specified reference voltage U /. The reference voltage U is chosen in advance on the basis of the available experimental data or by calculation, its physical meaning is the maximum rate of change of the input process. Consequently, the block C, issuing the output signal U, signals the presence of an anomalous measurement. The signal of the presence of an anomalous measurement from the output of the block k is sent simultaneously to the inverting input of the AND 10 element, as well as to the second input of the OR 18 element. incoming from block 2 voltages / / ej t with values of specified voltages Uf and C). The voltage U is also chosen in advance based on the available a priori data about the measured processes or by calculation.

The physical meaning of the entered constant U is the minimum rate of change of the input process, at which the device perceives the input process as varying with time. The set value U determines the compression ratio of the information. By varying the value of the constant Vff, it is possible to vary the compression ratio depending on the test program. Comparison unit 3, determine the value U2 du / cJt U, actually forming a corridor of significant samples, the speed of the process change that falls into this interval requires the formation of another significant count , Depending on the result

and U2c

by size

comparing the constants and derivatives at the current time from the outputs of block 3, a signal is output: respectively to the elements AND 10, OR 18 from the first output to the element AND 20 from the second. Temporary

I a

17428 1210

diagrams (fig.Z) explain the work

five

five

block 3, and for it l ex du / cJu

The generator 5, receiving from the output of element 2, the voltage dv / dt, alternates the frequency of the clock pulses, thus controlling the sampling frequency of the A / D converter 1, forming a temporary gate for the elements 10, IS-NE 19 by the operation of the trigger 14. and block 9 In addition , from the output of the generator 5, the pulses go to the divider b (frequency). The output of information to the communication channel from the output of block 21 takes place under the control of pulses from the output of divider 6, which has a constant division factor. With a small dynamics of the process is possible, the case when the sample during the K-cycles of the work is considered to be insignificant

In this case, the error AS is heated up, the maximum of which is

D5 KAs; , C h, where D5- is the error in the i-th cycle of operation, which tends, in the limit, to the value of the value U2 (Fig. 2). In order to avoid such a situation, a counter 8 is inserted into the proposed device, which counts the number of the following non-essential samples and, when the specified number is reached, outputs a signal to the block 9 of the buffer memory. By work

5 counters control the elements OR 18,

AND-NOT 19, and 2U. Element OR 18 at. the presence at its input of one of the CHI lines of blocks 3 and k forms a equal signal to the element AND NOT 19

0 and if it coincides with the impulse from generator 5, the AND-NE element 19 forms a temporary gate for the AND element 20 to skip the result of the comparison d U / d t Eggs of the second output

5 block 3 as a counting pulse to counter 8,

From the output group of the A / D converters 1, the measurement result in the digital code goes to block 9 and to the corresponding inputs

0 elements And 11 of each of the processing units under the influence of the clock pulse from the generator 5. Element And 10, depending on the combination of the signal at its input, performed the function Y XI-X2-X3, where Y,; X1t X2, X3 signals, respectively, at the output of the first, second, and third inputs of the element, generates a control pulse to the element 11, which, respectively, 11/428

It controls the operation of the element M and simultaneously enters the first (informational) input of the trigger 14.

A 1h trigger and an And 12 element control the arrival at the input of elements 1b and lb, respectively, of an odd and even significant sample, while the inverse output of a 1h trigger is connected to the inverse input of an And 12 element,

With elements 15 and 16, the bit of a significant sample is applied to the element OR 17 | at the input of which there may be bits from an irrelevant sample, coming from block 9 or essential from elements 15 and 16. One of these bits is fed to the input of element I 13 and is controlled by 10

12

This signal, which arrives at 6 frequencies, does not allow the corresponding elements to work. In connection with this, 15 and 1b are identical, op one of them for the case of

equals four (n 4)

I

The clock generator 7, pte 6, provides a counter je, suppose 1010, and in a buffer memory, the weight of which is less and less and less. At the inputs, attend the following Z:

20

 ..

a4agala aaa.

Va4a3a2 i v / 4a3a2aiVai, a5a2a, v a4a3aga a3a2ar

Z

 and and

one

but. where a - corresponds to the presence of I1 at the i-th input of the block 21; corresponds to the presence of O, i 1,1.

At the input of element 15 (16) of each processing unit, one of the following combinations X may occur:

X, where b, b - means the presence of 1

at the input, respectively, from element 14 (12) and the former 7 ° At the output of element 15 (16) 1 in the following case:

Y (1) - bjb.Yb-b.Vb, and O

Y (0) b2bf.

Then in our case

a; b2bjVbtb, Vbzb,,, respectively for each of the four bits.

The presence of two comparison elements (elements 15 and 16) in each processing unit is necessary to increase the speed of operation of the device. Divider 6 is a conventional counting trigger.

At the exit from the buffer memory block 21, a substantial sample is given on the incoming clock pulses with

25

Ј kf

g

thirty

where fr is the oscillator frequency b;

k is a coefficient proportional to the division ratio of the divider 6.

In this connection, it is sufficient to ensure that the clock start of the device is synchronized with the clock of the data processing system, for example, according to the moment the input signal arrives, in order to make it possible in principle to reconstruct the signal (Fig.).

The input process in the form of voltage is presented (Fig.) In the diagram. They have two characteristic areas of AB, BV and point D - anomalous ejection. Plot 40 AB is characterized by the fact that within its limits for the input voltage the inequality is satisfied

v0 ± &

dt

and

for section BV,

 O.C.

In the section of the AF at the output of the trimming element 50 (2), the voltage varies in proportion to the rate of change of the input voltage, and the frequency of the generator 5 changes in accordance with it (Fig. C).

divider 6 output. Due to the fact that the voltage at the first output of block 3, the division factor of divider 6 is constant stepwise (diagram D) is not, then the output of information to the channel at the second output of block 3 is a communication diagram with the output of block 21 occurs at intervals of time

ma D. At the last there is a response to the anomalous ejection (point D on

12

This signal coming from the frequency divider 6, passes the measurement bit to the corresponding input of the block 21. The operation of the processing elements 15, 16 is removed. Due to the fact that elements 15 and 1b are identical, we describe the operation of one of them for the case when the size of the code output from the ADC 1

equals four (n 4).

I

Under the influence of a clock signal passed by divider 6, the shaper 7 outputs a test constant, suppose 1010, and a code whose weight is less than or equal to this counter has to pass to the input of the block 21 of the buffer memory. At the inputs of block 21 there may be the following result Z:

five

Ј kf

g

0

where fr is the oscillator frequency b;

k is a coefficient proportional to the division ratio of the divider 6.

In this connection, it is sufficient to ensure that the clock start of the device is synchronized with the clock of the data processing system, for example, at the moment the input signal arrives in order to realize the fundamental possibility of reproducing the signal (Fig.).

The input process in the form of voltage is presented (Fig.) In the diagram. There are two characteristic areas of AB, BV and point D - anomalous ejection. Plot AB is characterized by the fact that within its limits for the input voltage the inequality is satisfied

v0 ± &

dt

and

for section BV,

 O.C.

In the section of the AF at the output of the trimming element 2 (Fig. B), the voltage varies in proportion to the rate of change of the input voltage, and the frequency of the generator 5 changes in accordance with it (Fig. C).

The voltage at the first output of the block varies in steps (diagram D at the second output of block 3 — diagrams

ma D. At the last there is a response to the anomalous ejection (point D on

and

diagram a), which is not yet considered as such.

The output of the block k is a zero signal (fig.e) with the exception of the response to an anomalous emission. At the output of ADC 1 (fig.zh) there is a discrete value that coincides with the implementation of the input process at the moment of issuance of a pulse by the generator 5. In the area of the VG, the implementation of the input process has a small dynamics (dU m / sK ug) and the sampling frequency is determined mainly by the digit size of the 8 meter. The G point characterizes the operation of the block k. At the output of block A, there is a separate pulse coinciding in time with an anomalous surge, which is reflected in the form of an anomalous measurement at the output of the A / D converter 1 (Fig. G).

The recording of significant reports in block 21 is carried out at times proportional to the frequency of generator 5 (diagram 4h). The result of a possible approximation is presented on the plot and. The marked sections of the State Duma, D1Ј, ЕЖ (fig.a) are similar, respectively, to SH, BV and AB.

Thus, the sampling rate of the signals to be transmitted varies in accordance with the rate of change of the input process while the device is simplified. The elimination of anomalous measurements and now essential samples with a small dynamics of the input process makes it possible to increase the reliability of the information obtained.

Claims (1)

Invention Formula A device for compressing and processing information, comprising an analog-to-digital converter, the first input of which is the device input, the outputs are connected to the first and the same inputs of the first block of the buffer memory, the second block of the buffer memory, the output of which is the output of the device, a pulse generator, the output of which is connected to the frequency input, the counter, the first comparison unit and the AND element, which differs in that, in order to increase the information content and reliability of the device, a shaper of codes that differentiate 28th element, second reference, AND-NOT element, OR element and blocks AND 0 five 0 five processing information, each of which is performed on AND elements, OR element, trigger and comparison elements, the output of the first AND element is connected to the first input of the second AND element, the output of which is connected to the direct input of the third And element and to the first trigger input, the inverse output of which connected to the inverse of the input of the third element And, the direct output of the trigger and the output of the third element And are connected to the first inputs of the first and second comparison elements, respectively, the outputs of which are connected respectively to the first and second inputs ORT, the output of which is connected to the first input of the fourth element AND, the outputs of the fourth elements AND of the information processing units are connected to the corresponding first inputs of the second block of the buffer memory, the second inputs of the second elements AND information processing units are connected to the corresponding outputs of the analog-digital converter , the output of the counter is connected to the second input of the first buffer memory block, the outputs of which are connected to the third inputs of the elements OR of the corresponding information processing units, the input is differentiated its element is connected to the device input, output is connected to inputs of the pulse generator; the first and second comparison blocks, the first output of the first comparison block is connected to the first input of the OR element and the first direct inputs of the first AND elements of all information processing blocks Q, the second output of the first comparison block is connected to the first input of the AND element whose output is connected to the counter input, the second inputs of the triggers and the second inputs of the first elements AND channels of information processing, the first input of the element NAND and the second input of the analog-digital converter are combined and connected to the output of the pulse generator, the output is divided frequency is connected to the second inputs of the AND Fourth information processing channels ,, the second input of the second buffer memory unit and an input of the codes, the outputs of which are connected to second inputs of the comparing elements of corresponding data processing channels, the second comparing unit output is connected to in0 five S 0 five 1b sixteen The top inputs of the first elements of which are connected to the second input AND of the Information processing block and to the NAND element, the output of which is connected to the second input of the OR element, the output is not connected to the second input of the element I. BW & HOE i / tfrf jtAyff (ue & il AiS.Atk-i & tK FIG. 2  Jm Own 3 sixteen  B fff / i U "Ui bwi Ut u & Ш2 I J U (Uf Ut Ui. "I TPTGTTZH and f   XW VH JKHjWtfJUVH 1  Uh g  If 149 yHdMHdmBiUVH Uhz7 TYM9 vHiHHawBduvH tpptp 5 tfaoiadJH j lu mvKvi7iidW g  one Have v FIG. five FIG. 6 Ubblx 9Л-ТА Block 1