SU1732499A1 - Digital receiver of delta-modulated signals - Google Patents

Abstract

SUMMARY OF THE INVENTION The receiver comprises a synchronization unit 1, first and second memory blocks 2 and 3, two circuits, each of which consists of an EXCLUSIVE OR 4 element, a reversible counter 5 and a module 6 calculating module, an adder 7, a threshold block 8 and a block 9 accumulation management. 1-2-4-5-6-7-8-9. 1-3-8. 5 il.

Description

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The invention relates to a digital signal processing technique and can be used in telecommunications to receive single signals, in particular, to receive 2600 Hz linear signals used on telephone networks represented in the form of inertial companding delta modulation signals.

A digital receiver of single-frequency signals in the form of delta-modulated signals is known, which can be implemented as a delay line, whose taps are connected to the input of an adder via multipliers.

A disadvantage of the known device is its complexity associated with a large number of multipliers. In addition, an increase in the frequency selectivity by increasing the analysis duration leads to distortions of the signal duration at the output of the device.

A delta-modulated digital receiver is known, which contains a synchronization unit, a memory unit, the first and second elements EXCLUSIVE OR with inversion, the first and second reversible counters, the first and second modules for calculating the module, the adder and the threshold device.

In this device, the decision about the presence or absence of the signal frequency in the signal being processed is formed at the end of each processing cycle having a certain specified duration T.

A time delay is introduced into single-frequency receivers of linear signals in order to increase the protection of turn-off triggers from speech signals. If Tmin is the minimum permissible duration of a signal pulse, then it is obvious that to increase the noise immunity, the response delay time is advisable to be close to Tmin, so as not to miss the signal pulse, the distortion of the signal duration at the receiver output should be sufficiently short . An increase in noise immunity is achieved by increasing the filtering selectivity in the device, which requires an increase in the duration T of a single processing cycle, but due to the uncorrelatedness of the beginning and end of the edges of the cycle with the arrival of a signal pulse, an increase in the duration T leads to an increase in the distortion of the signal at the device output

However, increasing T increases noise immunity by increasing the selectivity of bandpass filtering, except for

In addition, it leads to an increase in the duration distortion and a decrease in the permissible value of the response delay and the reduction in noise immunity.

The aim of the invention is to increase the noise immunity and reduce the duration distortion by allowing the device to function with long processing cycle times, but with low signal duration distortions.

The purpose of the invention is achieved by introducing the dependence of the duration of one processing cycle on whether the device is in a triggered (reception) or non-triggered state. Moreover, in the absence of a signal pulse at the device input, the processing time Ti is short (signal search) and the start of the signal pulse occurs with a minimum delay. After triggered, the device goes into a mode in which the cycle time increases to T2 TL, but the decision on the presence or absence of signaling information due to the presence of a system of several thresholds is made in each Ti interval, therefore the deviation of the signal frequency from the specified value or the moment of signal loss is also detected fast (approximately during the current TI interval). As a result of the described processes, the frequency selectivity is determined by the value of T2, which can reach the minimum permissible duration of the entire signal pulse, and the distortions of the duration of the entire signal pulse are determined by the relatively small TL value

Fig 1 shows the block diagram of the proposed receiver; in fig. 2 is a block diagram of a synchronization unit; in fig. 3 is a block diagram of an accumulation control unit; in fig. 4, 5 are timing diagrams for how to operate the device.

The digital receiver contains a synchronization unit 1, the first memory block 2, the first 4-1 and the second 4-2 elements EXCLUSIVE OR with inversion, the first 5-1 and the second 5-2 reversing counters, the second memory block 3, the first 6-1 and the second 6-2 module calculation units, the adder 7, the threshold unit 8, the accumulation control unit 9.

The synchronization unit 1 (FIG. 2) contains a clock generator 10, a frequency divider 11, a switch 12, inverters 13, 14, 17, single-vibrators 15, 18, and delay elements 16, 19,

The accumulation control unit 9 (FIG. 3) contains a D-flip-flop 20 and an AND 21 element.

The proposed digital receiver works as follows.

The input signal, converted to digital form using delta modulation with inertial companding, is fed to the combined second inputs of elements 4-1 and 4-2 EXCLUSIVE OR inversion, in which each delta-modulated symbol x is multiplied signal by one-bit weights, corresponding to the sign values of the sinusoidal and cosine-shaped signals with a frequency equal to the frequency of detection.

The values of these weights are supplied from the respective outputs of the first memory block 2, the address signals for which are formed by the frequency divider 11 (Fig. 2) within the synchronization block 1. The output signals of elements 4-1, 4-2 EXCLUSIVE OR with inversion control the counting direction of clock pulses by reversing counters 5-1, 5-2, with the coincidence of logical symbols (1 or 0) at the input of element 4-1 (4-2 ) EXCLUSIVE OR with inversion, corresponding to multiplying the values of 1 by 1 or -1 by -1, causes an increase in the content of reversible counters 5-1. 5-2 per unit, and the mismatch decreases by one, so by the end of the processing cycle with a length T at the outputs of the reversing counters 5-1, 5-2, the values A, B are formed, corresponding to the real and imaginary components of the spectral count at the detection frequency.

Approximate calculation of the spectral reading module F at frequency f is performed in accordance with the expression F IAI + I B I using an adder 7 and blocks 6-1, 6-2 calculating the module, which can be built as a block of controlled inverters, to information inputs which are connected to the outputs of bits 1G-1

the corresponding reversible counter, and the combined control inputs are connected to the output of the rth discharge, while at the time of initial installation (at the beginning of the cycle, the signal from 2 output of the synchronization unit 1) is discharged 1 g-1 and zeroed out th

the bit is written 1, after which, depending on the value of the r-th bit, by the end of the cycle the output code of the reversible counter is inverted (with r 0) or passes without inversion (r 1) to the inputs of the adder 7.

Thus, the device implements an algorithm for optimal incoherent processing with the following approximations of the values of the weighting factors quantized into two levels.

0

by the formula F1 A 2 4- B 2 is replaced by an approximate calculation using the formula F - IAK IBI, which leads to the preservation of some dependence of the filtering result on the signal phase - the result value can fluctuate within about 3 dB, which slightly affects the characteristics of the device. When processing, the samples of the input delta-modulated signal are taken into account with equal weight, which results in the effect of compressing the dynamic range at the output of the adder 7 compared to the dynamic range of the signal being processed, which is equivalent to the AGC effect, therefore at a fixed integration time a constant threshold can be used in the device In comparison with which in the threshold block 8 the output signal of the adder 7 is compared, the trigger band is practically independent of the level of the signal being processed in a wide range. the level of levels.

In order to quickly recognize the beginning of the signal pulse, the device operates prior to its operation with short processing cycle times (Ti). This is provided as follows. The duration T h of a short cycle is determined by the period of the output signal

® one of the bits (r-th) of the 11 frequency divider of the synchronization unit 1. This signal is shown in FIG. 46 (signal Ui). The leading edges of the signal Ui correspond to the end of the cycle. The inverted by inverter 17 (Fig. 2) signal Ui is applied to the clock input of the D-flip-flop 20 (Fig. 3) of the accumulation control unit 9. On the leading edges of this signal (U, Fig. 4c), the information from the output of the threshold unit 8 is gated to D-flip-flop 20 (Fig. 3). Thus, in the absence of operation (in the absence of a useful signal), the output signal UA (Fig. 4e) of the D-flip-flop 20 is zero. This signal is fed in direct and inverse form to the control inputs of the switch 12 (Fig. 2) of the synchronization unit 1, which causes the short pulses 11 of the frequency (Fig. 2) to flow through the switch 12 to the input of the zero setting of the divider 11 4d), formed using elements 17-19 (Fig. 2) with a delay τ (τ TI) relative to the falling edges of the signal Ui (Fig. 46), coming from the output of the r-bit of the frequency divider 11. So at the end of each

5, the Ti interval (Fig. 46), the frequency divider 11 is reset. (The value of r in Fig. 4 is shown on an enlarged time scale). The bit number g corresponds to the number N of the clock intervals T- | placed on a treatment cycle of Ti (N-2G) duration. Since in the lower address bit of the second memory block 3, the signal is supplied from the (r) -th bit of the frequency divider 11, the address code at the input of this memory block remains zero at the interval Ti. In this case, the smallest of the threshold values (Pi, Fig. 5) is read out from the second memory block 3 to the threshold block 8. The output signal of the switch 12 (Fig. 2) of the synchronization unit 1 also performs the initial installation (zeroing of the significant bits) of the reversible counters 5-1. 5-2. to the beginning of each TI processing cycle. therefore, the output signal U + (Fig. 5) of the adder 7 is also zeroed out.

When a signal pulse (Uex) appears at the device input, the output signal of the adder 7 (and, Fig. 5) in the current interval Ti will exceed the threshold value PL that by the end of this cycle will transfer the i-trigger 20 (Fig. 3) to the single state ( LU, Fig. 4d) and change the signals at the control inputs of the switch 12 (Fig. 2) to the opposite. however, the next impulse (Us. FIG.

4, the time ti) from the output of the delay element 19 (Fig. 2) to the input of setting the zero of the counter of the frequency divider 11 (Fig. 2) does not arrive and the device switches to the processing mode with a long cycle Ta Ti. In the process, the frequency divider 11 (FIG

2) in each interval Ti, the binary code applied to the address inputs of ROM 3 varies. Examples of signals at two address inputs taken from (r + 1) and (r + 2) th bits of frequency divider 11 are shown in FIG.

5. During the intervals r (the magnitude of the delay of elements 16, 19, Fig. 2), after each cycle, there is a distortion of the address signals, which, however, will not affect the operation of the device, since the value of m is extremely small.

A sequential code change at the address inputs of the second memory block 3 will cause a change in the threshold values (Pi, Pa, ...) taken from its output at the threshold block 8. The threshold value is calculated so that when the frequency of the signal pulse is within the specified output limits the signal of the adder 7 in each current interval TI within the processing cycle Ta must be necessarily higher than the current value of the threshold P, while D-flip-flop 20 is continuously held in a single state. At the end of cycle T, the frequency divider 11 (FIG. 2) and the reversible counters 5-1 are reset. 5-2 short impulse formed by elements

14-16 (Fig. 2) with a delay relative to the falling edges of the output signal of the K-th bit of the frequency divider 11. (When D-flip-flop 20 is in the unit state, this pulse passes through switch 12 (Fig. 3). The K number of the bit corresponds to the number of cycles Ti stacked on the cycle duration Ta. It should be noted that the cycle duration Ta can be selected as the minimum values of the signal pulse duration with a corresponding increase in noise immunity. In addition to a system reset on the falling edge of the output signal of the K-th bit of the frequency divider 11, the reversible counters 5-1, 5-2 can also occur when the deviation of sp The structure of the signal from a given (concentrated in the vicinity of a given signal frequency) or when the useful signal disappears. In this case, in the current interval Ti within the cycle, Ta output signal of the adder 7 (U +) does not exceed the current threshold value (threshold Ru). With this, the leading edge of the signal U (Fig. 4e, moment ta) from the output of the delay element 19 (Fig. 2) sets the reversible counters 5-1, 5-2 and the adder 7 to the initial state. Through the element 21 and the same impulse will pass to the output Reset block 9 and can be used, for example, to zero the external drive. An external response time delay is introduced in the external storage device, increasing protection against false positives.

External storage can be performed, for example, in the form of an integrator with a reset,

From FIG. 4-5, the duration of the output signal of D-flip-flop 20 (FIG. 3) approximately corresponds to the duration of the envelope of the signal pulse (accuracy is determined by the duration Ti of the shortest processing cycle).

Claims (2)

Invention Formula The digital receiver of the delta module and the paged signals, containing a synchronization unit, to the first address inputs of which is connected the first memory block, the series-connected adder and the threshold unit, two circuits consisting of the series-connected EXCLUSIVE OR elements with inversion, a reversible counter and the module’s calculation unit, the first inputs of the EXCLUSIVE OR elements with inversion are combined, and their second inputs are connected to the corresponding outputs of the first memory block, clock inputs and reset inputs of the reversible counters The pairs are combined and connected respectively to the first and second outputs of the synchronization block, the outputs of the modules calculating blocks are connected to the corresponding inputs of the adder, characterized in that, in order to improve accuracy, a second memory block and an accumulation control block are inserted, the information input of which is connected to the threshold output block inputs Cm uHQ- oovctu, ucUHO2c exit / 2. Fig 2 the threshold signals of which are connected to the outputs of the second memory unit, the inputs of which are connected to the second address outputs of the synchronization unit, the third and fourth outputs of which are connected to the synchronization outputs of the accumulation control unit, the information output of which is connected to the input of the synchronization unit. TO. / 73U2 to tak.toЈ1M entrances ches / pgi- "/ 5- /, 5-g.  bhoam , but The initial unit is ctemtuKoS 5-i, 5-2. - K. FIRST STROB- input $ sucker 12. k gory stroy- s / toxa (2. / 7М7 ..e ° F (ÁN) Ј ir) tb 66frZCiL Rig 5