SU1732360A2 - Function reproduction device - Google Patents

Abstract

The invention relates to automation and computing and can be used in automation and remote control systems, in analog and digital signal processing. The purpose of the invention is to expand the class of tasks to be solved by organizing the reproduction of function values at separate, arbitrary, predetermined points. The device contains a block 1 setting the parameters of functions, the first and second registers 2, 3 ordinates, the first output 4 of the block 1 setting parameters, the second output 5 of block 1, the first delay element 6, the converter 7 direct code to additional, the first adder 8, the digital block 9 multiplication, clock input 10 of block 1, register 11 for the duration of the section

Description

The invention relates to automation and computing, can be used in automation and remote control systems, in analog and digital signal processing and is an improvement of the device according to the author, St. No. 1644177.

A device for reproducing functions is known, comprising first and second adders, a block for setting parameters of functions, first and second buffer registers, an OR element, first, second and third outputs of a block for setting parameters of functions connected to information inputs of the first and second registers of the section and duration of the section approximation, the output of which is connected to the input of the controlled pulse generator, the output of which is connected to the counting input of the reversible counter, the digital output of which is connected to the ad The digital input of the memory of the argument values, the analog output of the device are connected to the output of the digital-to-analog converter, the information inputs of the digital multiplication block are connected respectively to the outputs of the memory block of the argument values and the first adder, and the output is connected to the information input of the first buffer register, the output of which is connected to the first the input of the second adder, the second input of which is connected to the output of the second buffer register, and the output of the second adder is the digital output of the device and the connection It is connected to the input of the D / A converter; the output of the first ordinate register is connected to the first input of the first adder, the second input of which is connected to the output of the direct code to additional converter, the input of which is connected to the output of the second ordinate register and the information input of the second buffer register, whose recording input is combined with the write input of the first buffer register and connected to the output of the second delay element, the input of which is connected to the start input of the digital multiplication unit and to the output of the first element aderzhki having an input connected to the output

the OR element, whose inputs are connected to the output of the controlled pulse generator and the write input of the reversible counter, which is also connected to the output of the third delay element, whose input is connected to the write inputs of the first and second ordinate registers and the register of the length of the approximation section, with the clock input of the parameter setting unit functions and is connected to the output of the reset sign of the reversible counter, the information input of which is connected to the input of specifying the number of intervals of the approximating function of the device.

This device allows you to reproduce signals in both analog and digital form from two adjacent samples and the time interval between them, and this device reproduces the sequence of all signal values in the intervals between the reference values. In systems of automation and telemechanics that use digital signal processing, it is often necessary to restore the digital codes of signals only at separate, predetermined, generally arbitrary points so that you can determine the signal values at points with predetermined numbers in approximation areas of different durations. . For example, in the first segment of the approximation, select the 2nd and 5th points of this segment, and in the second segment - the 3rd, 4th and 6th points of this segment. Such a need may arise for modeling data with gaps, such as time series of changes in sea surface temperature during processing and experimental studies of hydrometeorological information. It can also be applied when restoring data gaps in such time series, when the number of the distorted point is known as a result of preprocessing. In addition, the need to solve this class of problems arises when various kinds of changes in the scale of the signal display, especially when adapting its discretization and, if necessary, preserve

such adaptability to reduce redundancy and to maintain constant fidelity in the reproduction of sections with different rates of change of the signal. In addition, the need to reproduce the signal is not at all possible points in the order, but at a separately taken, predetermined point, may arise in order to reduce the redundancy associated with different significance for the receiver of signal values at different points in the approximation area, and it can also find application for coordinating the rate of formation of new information — reproduction of signal A — with the performance of specific various information processing devices.

The known device does not allow reproducing the values of the function in separate, predetermined, generally arbitrary points.

The aim of the invention is to expand the class of tasks to be solved by organizing the reproduction of function values in separate, arbitrary, predetermined points.

This goal is achieved by adding a summing counter, an ordinate of the reproduced points, a fourth delay element, a register of the codes of the reproduced values of the function, a block of codes of the reproduced values of the function, the counting input of the summing counter is connected to the output of the OR element, the digital output of the summing counter is connected to the address input of the ordinate memory block of the reproduced points, the one-bit output of which is connected to the input four A solid delay element whose output is connected to the input of a register of codes of reproduced function values, whose information input is connected to a digital output of a device, and the output of a register of reproduced function value codes is an output of function value codes reproduced at individual arbitrary points, the digital output of the device is connected to the information input of the block of codes of reproduced function values, the recording input of which is connected to the output of the fourth delay element, the address input of the block The memory of the codes of the reproduced function values is connected to the digital output of the summing counter.

The drawing shows a functional diagram of the device.

The device contains a block 1 setting the parameters of functions, the first 2 and second 3 registers of the ordinates, the first 4 and second 5 outputs of the block 1 setting the parameters, the first delay element 6, the converter 7 direct code to additional, first

an adder 8, a digital multiplier 9, a clock input 10 of block 1, a register 11 for the duration of the approximation section, a third output 12 of block 1, an analog 13 and a digital 14 outputs of the device, a second adder 15,

0 digital-to-analog converter 16, controlled pulse generator 17, reversible counter 18, first buffer register 19, argument value memory block 20, second buffer register 21, second element 22

5 delays, a third delay element 23, an OR element 24, a summing counter 25, a block of 26 memory of ordinates of reproduced points, a fourth delay element 27, a register of 28 codes of reproduced values

0 function, output 29 function value codes reproduced at individual arbitrary points, and block 30 of the code memory of the reproduced function values. The first 4, second 5 and third 12 outputs of block 1

5 setting the function parameters are connected to the information inputs of the first 2 and second 3 ordinates and the register 11 of the approximation section, respectively, the output of which is connected to the input of the controlled pulse generator 17, the output of which is connected to the counting input of the reversible counter 18, the digital output of which is connected to the address input of the parameter value memory block 20; the analog output 13 of the device is connected to the output of the digital-to-analog converter 16; the information inputs of the digital multiplier 9 are connected s respectively, to the outputs of the memory unit 20

0 values of the argument and the first adder 8, and the output is connected to the information input of the first buffer register 19, the output of which is connected to the first input of the second adder 15, the second input of which is connected to the output of the second buffer register 21, and the output of the second adder 15 is a digital output 14 devices and is connected to the input of the digital-to-analog converter 16, the output of the first register 2

0 ordinate is connected to the first input of the first adder 8, the second input of which is connected to the output of the forward code converter 7 to the additional one, the input of which is connected to the output of the second register

5 3 ordinates and with the information input of the second buffer register 21, the recording input of which is combined with the recording input of the first buffer register 19 and connected to the output of the second delay element 22, the input of which is connected to the trigger input of the digital multiplication unit 9 and with the output of the first delay element 6, the input of which is connected to the output of the element OR 24, the outputs of which are connected to the output of the controlled pulse generator 17 and the recording input of the reversible counter 18, which is also connected to the output of the third delay element 23 whose input is Connected with the recording inputs of the first 2 and second 3 registers of the ordinates and the register 11 of the length of the approximation section, with the clock input 10 of the function setting unit 1 and connected to the output of the sign of zeroing of the reversing counter 18, the information input of which is connected to the input of the number of intervals of the approximating function of the device, the counting input of the summing counter 25 is connected to the output of the OR 24 element, the digital output of the summing counter 25 is connected to the address input of the memory block 26, the one-bit output of which is connected to the input The house of the fourth delay element 27, the output of which is connected to the input of the register entry 28 of the codes of the reproduced function values, the information input of which is connected to the digital output 14 of the device, and the output of the register 28 of the codes of the reproduced function values is the output 29 of the function value codes reproduced at individual arbitrary points The digital output 14 of the device is connected to the information input of the block of memory 30 of the codes of the reproduced function values, the recording input of which is connected to the output of the fourth element 27 of the set ratio, address input unit 30, the memory values of a function code reproduced coupled to the digital output of the summing counter 25.

The approximation of the signal y (t) in the adjacent discrete samples AI and A2, the time interval AT between them, the device implements according to the formula

y (t) Ai + (A2-Ai) F (), (1)

where AT is the time interval between adjacent discrete samples of the AI and A2 signal;

ACh and A2 - first and second discrete signal samples, respectively;

F is an approximating function, F (t) 1.

As a memory block 26, in particular, a random access memory with one-bit organization can be applied, which is pre-programmed so that in each of its cell number K (U - 1) (N + 1) + j 0 1. N + 1 - point number on the plot of approximation; U - number of plot approximation, numbering

starts with N - the number of sub-intervals into which the approximation section is divided) write 1 or 0 depending on whether it is required or not to reproduce on

output 29 value of the function at this point K.

The memory unit 30 is for storing the reproduced function values. Before starting work, codes corresponding to

pass in the data. For example, let the code zero mean that the value of the function at the point in question is not calculated - is absent. When the device operates in those cells of the memory block 30 whose addresses are equal

The addresses of those cells of block 26 in which the units are written record the reproduced function values, the remaining cells of the memory block 30 do not record the reproduced values, and the codes corresponding to the gaps in the data remain in them. Thus, at the end of the work, in the memory block 30, a sequence of codes is recorded such that it contains the codes of the reproduced

values of the function, as well as codes, meaning that at the point whose number is equal to the address of the considered cell of block 3, the value of the reproduced function is omitted. Upon completion of the operation of the device, if necessary, you can read the contents of memory block 30 — a sequence of function value codes and gaps — and apply it, at the discretion of the user. The device works as follows

Before starting work, the information input of the counter 18 is given an N code, which is stored on this input all the time the device is running, the block 1 of setting the function parameters exposes the codes of the values of the second AA, the first AI of discrete samples to their first 4, second 5 and third 12 outputs signal and the interval of AT between them, respectively. Counters 18 and 25 are zeroed by the Start signal. The signal from the output of the sign of zeroing the counter 18 is fed to the inputs of the recording of registers 2, 3 and 11, allowing parallel writing to these registers of the values Aa, AI and T prepared by block 1

respectively, as well as the clock input of unit 1, allowing him to begin preparing data for the next approximation segment. After a time determined by a delay element 23 sufficient to record

codes in registers 2, 3 and 11, the delayed pulse of the sign of zeroing the counter 18 comes from the output of the element 23 to the input of the record of the counter 18, setting the latter to the state N.

At the output of memory block 20, a code of the value of the approximating function F written in the Nth cell is formed, corresponding to the zero value of its argument F (0), which is fed to the first information input of digital multiplication unit 9. Simultaneously, the second information input of the last receives the difference code (Aa - AI) formed at the output of the first adder 8, the first input of which receives the code Aa from the output of the register 2, and the second input - the additional code of the number AI formed at the output of the converter 7, the input of which is supplied with the AI code from the output of the register 3. The pulse of the installation of the counter 18 to the state N from the output of the third delay element 23 is fed to the input of the element OR 24 and from the output of the latter to the counting input of the counter 25, translating it into the 1st state resulting in a The address inputs of blocks 26 and 30 form the corresponding address code, on the one-bit output of memory block 26 — the bit recorded in its 1st cell, for example, one. This signal of the level of the logical unit is fed to the input of the delay element 27, the time of which is chosen not less than the sum of the delay times of the elements 6 and 22.

The output of the element 24 is connected to the input of the delay element 6, the signal from the output of which starts the digital multiplier 9. The delay time of the delay element 6 is chosen sufficient so that by the time the digital multiplication unit 9 starts, its information inputs have generated a code for the value of the function F at the i-th point (from the output of block 20) and the code (Аа - AI) (the latter remains unchanged during the interval of approximation and changes only in the transition to a new interval of approximation). Since F (0) 0, a zero code is generated at the output of digital multiplication unit 9, which is fed to the information input of the first buffer register 19 and is written to this register by the signal from the output of the second delay element 22 delayed by the time required to perform the multiplication operation . On the same signal from the output of the delay element 22, the AI code from the output of the register 3 is written into the second buffer register 21.

The codes from the outputs of the buffer registers 19 and 21 are received respectively at the first and second inputs of the second adder 15. Thus, the AI code is generated at the digital output 14 of the device, and the corresponding analog signal level is formed at the analog output 13. The signal from the output of the delay element 27 is fed to the input of the record of the register 28, allowing (or not allowing,

if in the corresponding cell the memory block 25 is recorded O) parallel recording in it of the code (Ai) formed at the digital output 14 of the device. In this way,

this code (Ai) is generated at the output 30 of the device. At the same time, the signal from the output of the delay element 27 is fed to the recording input of the memory block 30, allowing (or not allowing, in the corresponding cell

memory block 26 is recorded O) recording in its cell at the address formed by the counter 25, code (Ai), formed at the digital output 14 of the device. In addition, after a certain delay time sufficient to write to the register 11 and rewrite the AT to the controlled oscillator 17, the counting pulses begin to flow to the counting input of the counter 18.

The pulse frequency at the output of the controlled oscillator 17 corresponds to the AT register code 11.

After a time interval proportional to AT, to the counting input of the counter 18

a pulse arrives from the output of the controlled oscillator 17 m and transforms counter 18 into the (N-1) -e state. The same pulse, passed by the element OR 24, from the output of the controlled generator 17 is fed to

the counter input of the counter 25 transfers the latter to the next — second — state, as a result of which, at the one-bit output of the memory block 26, a signal of the level of a logical unit or logical zero is generated

depending on what is recorded in the second bit of memory block 26 — 1 or O. This signal is delayed by delay element 27 for a time sufficient to form a code on digital output 14 of the device

one

Ai + (A2 - Ai) F (tl). Simultaneously

the signal from the output of the element 24 enters the input of the element 6 of the delay and after a time sufficient to form at the output

block 20 of the memory recorded in (H-1) -th cell of the code of the approximating function F, starts digital multiplication unit 9, on the first information input of which, at the time of launch, it has time to form

the value code of the approximating function F at point i 1. The second information input of the digital multiplication unit 9 receives the difference code (A2 - Ai) obtained using the converter 7 and the adder 8. At the output of digital block 9

1 multiply the code is generated (Aa - Ai) F (),

which is written to the buffer register 19 at the end of the multiplication process.

Thus, at the output of the adder

15, the value code Ai + (Aa 1 -Ai) xF (mn) is generated, and at analog output 13

devices - corresponding to this code the level of the analog signal. The signal from the output of the delay element 27 allows, if in the 2nd cell of the memory block 26 a unit was recorded, or does not allow parallel recording of the Ai + code otherwise

+ (Aa - Ai) F (j) in register 28 and in block 30

the memory at the address determined by the state of the counter 25. If the recording in block 30 is not made, then in the corresponding cell there is a data skip code recorded there prior to the start of operation of the device. If writing to register 28 is performed, then the function value code generated at the device output 14 is also generated at the device output 29. Otherwise, the state of output 29 does not change. The states of the outputs 13 and 14 remain unchanged until the next, 2nd, pulse appears at the output of the second delay element 22 (the numbering of these pulses starts with zero). In the same way as described, the code Ai + (A2 - Ai) F (-jq) is formed on the digital output 14 of the device;

analog output 13 — an analog signal corresponding to it, and at output 29 it is formed or not formed and in memory block 30 is recorded or not recorded

new playable value code

about function Ai + (A2-Ai) F (jn) depending

on whether 1 or O is recorded in the corresponding — third — cell of memory block 26; On the remaining sub-intervals into which area 0 is broken; And T, the device works similarly.

On the last, N-m subinterval, the device works as follows.

After reproducing the intermediate value of the signal at

time t - r: -dt, corresponding

the value of the approximating function recorded in the 1st cell of block 20, the outputs 13 and 14 of the device are in the state Ai + (A2 - Ai) F j- until

nii

well

until

The counting input of the counter 18 will not receive a regular pulse from the output of the controlled generator 17, which will transfer the counter 18 to the zero state. The pulse from the generator 17, passed by the element OR 24, is fed to the counting input of the counter 25, transferring it to the next state. At the output of memory block 26, a logic unit level or logic zero level signal is generated, depending on whether 1 or O is written in the one-bit cell of memory block 26

at the address whose code is formed at the output of the counter 25. The signal from the output of the memory block 26 is fed to the input of the delay element 27, the delay time of which is not less than the sum of the delay times of the elements 6 and

0 22 and it is enough for the new reproduced value of the function Ai + (A2 - Ai) F (1) to be generated at the output of the adder 15.

The first information input of the digital multiplication unit 9, multiplying, as described above, receives the value code of the approximating function F (1), written in the zero cell of the unit 20. As described, with a delay provided by

0 by connecting the elements 6 and 22 in series, the outputs 14 and 13 are in the state Ai + (A2 - Ai) F (1), corresponding to the signal value at the end point of the approximation interval. The signal from the output of delay element 27 permits or does not allow, similarly to that described, parallel recording of the code Ai + (A2 - Ai) F (1) from output 14 to register 28 and memory block 30. Moreover, F (1) 0, as a result of which

0 we have the code AI, but the value of AI corresponds to the next approximation interval. At the same time, due to the fact that the counter 18 has passed to the zero state, the signal from its output of the zeroing sign is received

5 to the clock input of block 1, permitting the preparation of the initial data for the next approximation area to begin, and the same signal is fed to the recording inputs of registers 2, 3 and 11, allowing parallel recording in them

0 codes of the initial data of the current section of approximation, pre-set by block 1 to its digital outputs 4, 5 and 12, the impulse from the output of the sign of zeroing of the counter 18 is delayed by time,

5 determined by the element 23, to the input of the record of the counter 18 and sets the latter to the state N.

Similarly, the signal from the output of the element 23 of the delay passed by the element OR

0 24, translates counter 25 into the next, (N + 2) -e state, which determines the bit address in memory block 26 and the cell address in memory block 30. In the same way that the first sample of the AI signal was reproduced in the previous approximation interval, the first sample of the Ah signal is reproduced in the new approximation area and recorded or not recorded in parallel, depending on the output state of block 26 in register 28 and memory block 30.

Thus, output device 29 appears or does not appear, and in memory block 30, the address generated by counter 25 records or does not record the new reproduced function value depending on the bit state of memory block 26, the address of which formed by the counter 25. Upon the completion of the operation of the device in the memory block 30, such a sequence of codes is recorded that both the codes of the reproduced function values and the codes indicating gaps in the data are present in it.

Claims (1)

Invention Formula Device for playing functions by author. St. No. 1644177, characterized in that, in order to expand the class of tasks by organizing the reproduction of function values at individual arbitrary predetermined points, a summing counter, a memory block of ordinates of reproducible points, a fourth delay element, a register of codes of reproduced values are entered into it function , the code memory of the reproducible function values, the counting input of the summing counter is connected to the output of the OR element, the digital output of the summing counter is connected to the address input of the ordinate memory of the reproduced points, the single-bit output of which is connected with the entry of the register of codes of the reproduced values of the function, the information input of which is connected to the digital output of the device, and the output of the register of the codes of the reproduced values of the functions and is the output of the function value codes reproduced at individual arbitrary predetermined points, the digital output of the device is connected to the information input of the memory block of the reproduced function values, the recording input of which is connected to the output of the fourth delay element, the address input of the code memory of the reproduced function values connected to the digital output of the totalizer.