SU1688442A1 - Multichannel demodulator - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to provide a demodulation of the signal manipulated by the phase jumps of 180 °. The multichannel demodulator contains synchronizer 1, shift registers 2-4, memory register 5, adders 6 and 7, operational storage units 8 and 10, and switch 9. The synchronizer 1 controls the operation of all demodulator units. Actually demodulation is performed in the adder 7 by algebraically adding P samples of the measuring signal stored in register 5. In this case, the reference signal samples taken in the P high bits of register 4 play the role of the weighting factors -I or -1 with the corresponding readings of the measuring signal. 2 Il.

Description

The invention relates to radio engineering and can be used in various measuring devices and systems.

The purpose of the invention is to provide demodulation of a signal manipulated by phase jumps of 180 °.

Figure 1 presents the structural electrical circuit of a multi-channel demodulator; figure 2 is an embodiment of a synchronizer.

The multi-channel demodulator contains a synchronizer 1, first 2, second 3 and third 4 shift registers, memory register 5, first 6 and second 7 adders, the first random access memory (RAM) 8, switch 9, the second RAM 10.

The synchronizer 1 contains a differentiating unit 11, the first to fifth delay elements 12-16, the first to third dividers 17-19, the clock generator 20, the first 21 and second 22 counters, the first 23 and second 24 decoders, the switch 25. first to third RS -triggers 26-28, first 29 and second 30 keys.

A multi-channel demodulator operates as follows.

At the time Ικ = ΐκ-ι + At, the first register 2 (Fig. 1) receives a complex 2-bit code (g is the number of bits used to represent the readouts of one component of the analytical signal) as an input to the first register 2 (Fig. 1). At the same time, a single-bit reference signal S (t “) is applied to the input of the second register 3, and a pulse accompanying the input data is supplied to the clock input of the synchronizer 1. The value At represents the time interval of the sequence of input data.

With a certain delay after the arrival of the samples from the output of the synchronizer 1, a single pulse is received by shifting the first 2 and second 3 registers by sequentially writing the first 2 and second 3 registers, shifting the contents of the registers one bit forward and writing new data to the vacated space. With the arrival of the next pairs of samples at the signal inputs of the first 2 and second 3 registers, the cycle of writing data to the first and second 3 registers is repeated. At the same time, the synchronizer 1 calculates the accompanying pulses and, after the next group of pulses p arrives at the clock input of the synchronizer 1, a pulse is generated at the seventh output of the synchronizer 1, which ensures that the contents of the first register 2 are rewritten (in parallel code) into the memory register 5, the contents of the second register 3 into third register 4. The volume of memory register 5 is (2 g p), bits, and the second and third registers 3 and 4 are (p + 1-1) bits. In the memory register 5, the next p reports of the measuring signal are stored during the time interval p A t. During this time, demodulation of the measuring signal segment represented by p samples, I by various demodulating reference signals is performed. Actually demodulation is performed in the second adder 7 by algebraically adding p samples of the measuring signal stored in the memory register 5. In this case, the samples of the reference signal, taken from p senior bits of the third register 4, play the role of weighting factors + 1 or -1 at the corresponding samples of the measuring signal. Thus, the frequency result of demodulation for the first reference signal is formed. It should be summed with the contents of the zero double line of the first RAM 8. For this, synchronizer 1 supplies the number 0 to the third output (address signal for the first RAM 8), and then one control signal to the first output (provides reading data from the selected line of the first RAM 8) and through the time interval - to the second output (provides a record of the amount formed in the first adder 6 in the zero line of the first RAM 8). The output of the first RAM 8 is fed to the second inputs of the first adder 6 through the switch 9.

Other (j - e. J = 0, 1-1) reference signals are formed by alternately shifting the contents of the third register 4 one bit forward. The control signals for the shift are generated by the synchronizer 1 at its eighth output. Immediately after the shift, the address signal for the first RAM 8 at the third output of the synchronizer 1 is increased by one. Formed by the second adder 7, the result of the j-ro version of the demodulation of the processed portion of the measuring signal, as described above, is summed with the previously accumulated sum stored in the j-th line of the first RAM 8. For the time interval p · At, I summation cycles are performed in the second adder 7 and taking into account the contributions of private demodulation results to the accumulated low-frequency samples of demodulated signals.

Processing of input data in the conveyor mode is performed on the time interval K1 · ρ-Δτ. Upon completion of the processing of the K1st group of samples of the measuring signal, the generated low-frequency samples should be rewritten in the second

RAM 10. And all the lines of the first RAM 8 are cleared. This is achieved by supplying at the time interval corresponding to the processing time of one group of p samples (equal to p · At) the same control signals to the address inputs and recording control of the first RAM 8 and second RAM 10. and switching the switch 9 to a state providing supply to the second inputs of the first adder 6 numbers equal to zero. At the same time, simultaneously with writing to the second RAM 10 accumulated samples, new private demodulation results are entered into the lines of the first RAM 8.

At the next time interval of duration K1 p At, new samples of demodulated signals are generated. At the same time, from the second RAM 10 at the required speed, the output data of the multi-channel demodulator is output to an external consumer device. In this case, the number of the issued readout is indicated (communicated to the consumer) at the eleventh output of the synchronizer 1. The external consumer should read the next numbers from the output of the second RAM 10 at the moments of the presence of clock pulses at the fifth output of the synchronizer 1.

The pulses accompanying the input data are received at the clock input of the synchronizer 1 (figure 2). After a delay in the first delay element 12, they are fed to the eighth output of the synchronizer 1, providing sequential recording (information shift in the first 2 and second 3 registers. In the first divider 17, the stream of accompanying pulses is thinned by a factor of p. The pulses from the seventh output of the synchronizer 1 provide rewriting of information from the first register 2 to the memory register 5 and from the second register 3 to the third register 4.

Each pulse from the output of the first divider 17 initiates the work of a group of elements of the synchronizer 1, providing the creation of control signals for the first RAM 8, switch 9 and the third register

4. The control signals for the first RAM 8 and the third register 4 are created using the clock generator 20, the first RS flip-flop 26, the first key 29, the second fourth delay elements 13-15, the first counter 21 and the first decoder 23. The pulse from the output of the first the divider 17 sets the first counter 21 and the first RS-flip-flop 26 to zero, the output of which opens the first key 29. The clock pulses from the output of the clock generator 20 through the first key 29 and through the second or fourth delay elements 13-15 begin to arrive n count input of the first counter 21. Thus pulses from the outputs of the second 13 and third 14 delay elements are fed to first and second outputs of the synchroniser 1 (used to control data reading from RAM 8, and the first entry in the first memory 8). The time-shifted signals relative to the recording pulses from the output of the fourth delay element 15 (eighth output of synchronizer 1) are used to shift data in the third register 4 of the demodulator circuit and to change the increase in the address signal for the first RAM 8 (created by the first counter 21 and fed to the third output of the synchronizer 1). The first decoder 23 provides the formation of a short pulse at its output when the first counter 21 shows the number I. The specified signal sets zero the first RS-flip-flop 26, after which the first key 29 closes, stopping the receipt of control signals at the first, second and eighth synchronizer outputs 1. To ensure the operability of the multichannel demodulator as a whole and synchronizer 1, it is necessary that the repetition period of the clock pulses Tgen of the generator 20 clock pulses satisfy the condition

Tg <A t p / 1.

The control signal for the switch 9 is created using the second divider 18 and the second RS-flip-flop 27. Each pulse from the output of the first divider 17 confirms the second RS-flip-flop 27 is set to zero. The second divider 18 decimates the pulse flow. After the second K1 pulse is received at the input of the second divider 18, with a hardware delay m, a short pulse is formed at the output of the second divider 18, which ensures the installation of the second RS-flip-flop 27 into one. In this state, the second RS trigger 27 will remain until the next pulse arrives from the output of the first divider 17. The output signal of the second RS trigger 27 is supplied to the fourth output of synchronizer 1 (used to control switch 9).

A group of synchronizer elements 1, consisting of a second key 30 and a third divider 19, a fifth delay element 16, a second counter 22, a differentiating unit 11, a third RS flip-flop 28, a second decoder 24 and a switch 25, together with a clock generator 20 provides the creation of control signals for the second RAM 10. As described above, the second RAM 10 operates in two modes: overwriting data from the first

RAM 8 and in the mode of issuing data to an external consumer.

In the data overwrite mode, the switch 25 is switched by the output signal of the second RS-flip-flop 27 to the data transfer mode from the output of the first counter 21 to the eleventh output of the synchronizer 1 (address management of the second RAM 10) and from the output of the third delay element 14 to the tenth output of the synchronizer 1 (write control in the second RAM 10).

After the dubbing is completed, the second RS-flip-flop 27 is set to 0 and the switch 25 connects the output of the second counter 22 to the eleventh output of the synchronizer 1 (connected to the address input of the second RAM 10). During the dubbing, this second counter 22 is kept in state 0 at all of its outputs by the signal from the output of the second RS-trigger 27.

Claims (1)

Claim . A multichannel demodulator comprising a first adder, a memory register and a synchronizer, the first, second, third and fourth outputs of which are connected respectively to the read, write and address inputs of the first random access memory unit and to the control input of the switch, as well as a second random access memory unit, the fifth the synchronizer output is the synchronizing output of the demodulator, the logical zero of which is the first signal input of the switch, characterized in that, in order to demodulate the signal pulsed by 180 ° phase jumps, three shift registers and a second adder are introduced, the output of which is connected to one input of the first adder, the other inputs and output of which are connected respectively to the outputs of the switch and to the information input of the first operational storage unit, which is connected to the information input of the second operational a storage unit, the read, write and address inputs of which are connected respectively to the sixth, seventh and eighth outputs of the synchronizer, the ninth output of which is connected to the clock input the first shift register, the outputs of which are connected to the information inputs of the memory register, and the clock input of the second shift register, the outputs of which are connected to the information inputs of the third shift register, the outputs of which are connected to the control inputs of the second adder, the information inputs of which are connected to the outputs of the memory register, the parallel recording input of which is connected to the parallel recording input of the third shift register and the tenth output of the synchronizer, the eleventh output of which is connected to the clock the input of the third shift register, the clock input of the synchronizer and the information inputs of the first and second shift registers are respectively the clock and information inputs of the demodulator, the information output of which is the output of the second random access memory, and the output of the first random memory is connected to the second signal input of the switch. FIG. Ζ