RU2069934C1 - Device searching for noise-like signal - Google Patents

Abstract

FIELD: radio engineering, communication systems with noise-like signals. SUBSTANCE: decrease of search time is achieved thanks to connection of second on-line storage in parallel or in series to first on-line storage, second timing circuit is connected in parallel to first timing circuit and control circuit is inserted. Insertion of second on-line storage ensures uninterrupted operation of device: recording of input retrievals into second on-line storage takes place during reading of retrievals in first on-line storage. Clock frequency of pseudo-random sequence and signal duration of signal recorded into first on-line storage differs as a rule from similar parameters of signal recorded into second on-line storage. That is why timing of copy signal in second detector with alarm point on time axis should be conducted with allowance for these parameters. For this purpose second timing circuit is inserted. EFFECT: decreased search time. 2 cl, 4 dwg

Description

 The invention relates to radio engineering and can be used in communication systems with noise-like signals.

 In communication systems with noise-like signals, it is necessary to coordinate the time and frequency of the received and reference signals. The use of noise-like signals with a large base improves the parameters and characteristics of radio communication systems, does not increase the time to eliminate uncertainties in delay and frequency.

 One of the methods to reduce the search is described in the books of V. Likharev. "Digital methods and devices in radar", M. Sov. radio, 1973 and Viterbi E. D. "Principles of coherent communication", M. Sov. radio, 1970, as well as in Allen, Usterfield's article "Digital time-correlated correlators and matched filters for active sonar", Foreign Radio Electronics, 1964, N 12.

 In these works, it is supposed to write samples of the signal-noise mixture into memory and then quickly read them. The readable mixture of signal and noise goes to the detector.

 However, such devices have a drawback. With repeated cycles of work, it is necessary to spend time writing to the storage device a new set of samples. Repeated cycles of operation are necessary, for example, in standby reception or when searching for a signal at several frequencies.

 The prototype device comprises an analog-to-digital converter, a number register, random access memory, a number register, a first detector, a time matching circuit, and a second detector.

 When an alarm occurs, the cyclical reading of information from the random access memory and the corresponding checks by the detector for the presence of a signal in compressed time continues, and the detector checks the detected signal.

 The matching of the signal copy in the detector with the alarm point on the time axis is carried out by the time matching circuit.

 One of the possible variants of the time matching scheme is given in the prototype and contains pulse shapers, a switch, a group of reversible counters, a circuit for switching signal generators in the second detector.

 When using the prototype in each new cycle of work, samples of a mixture of signal and noise are recorded in the storage device. Therefore, during repeated work cycles, part of the time will be spent on recording samples.

 The aim of the invention is to reduce search time.

 This goal is achieved by the fact that in the prototype device, the second RAM is switched on sequentially or parallel to the RAM, a second time coordination circuit is included in parallel with the time matching circuit, and a control circuit is also introduced.

 The introduction of the second RAM ensures the continuous operation of the device: while reading samples from the first RAM, the input samples are recorded in the second RAM.

 The clock frequency of the memory bandwidth and the duration of the signal recorded in the first RAM differs, as a rule, from the similar parameters of the signal recorded in the second RAM. Therefore, the time matching of the copy of the signal in the second detector with the alarm point on the time axis must be made taking into account these parameters. For this, a second time matching scheme is introduced.

 The control circuit provides the inclusion of write and read modes of the first and second RAM, as well as the independent operation of the two timing schemes.

 The block diagram of the device with a serial connection of two random-access memory devices is shown in figure 1. It consists of an analog-to-digital converter 1, a register of number 2, a slow random access memory 13, a fast random access memory 14, a register of number 4, a first detector 5, a timing circuit 15, a timing matching circuit 2, a second detector 7 , control circuit 17.

 The device operates as follows.

 The input signal is fed to the input of the analog-to-digital converter 1. Digital samples of the signal-noise mixture from the output of the analog-to-digital converter 1 are written to RAM 1 through the register of number 2. 13. The recording interval is determined by the control circuit 17.

 After the recording is completed, overwriting the samples of the signal and noise mixture from RAM1 13 to RAM214 begins. The dubbing interval is determined by the control circuit 17. It is equal to the reading interval of the samples from RAM113 and their recording interval in RAM214, respectively.

 After overwriting, RAM1 13 goes into write mode, and RAM214 into read mode. The intervals of writing to RAM1 13 and reading from RAM214 are also determined by the control circuit 17.

 The read information from RAM2 14 through the register of the number 4 is fed to the input of the first detector 5, which can be performed as a multi-channel correlator. The detector 5 searches for the signal in compressed time. Coordination of a copy of the signal in the second detector 7 with the alarm point on the time axis is carried out by matching schemes in time 1-15 or 2-16.

 When an alarm occurs, the detector 7 checks it. If the detector 7 decided on the presence of a signal, the search is terminated. Otherwise, the search cycle in compressed time repeats.

 One of the possible options for the control circuit when the RAM is connected in series is shown in FIG. 3, where it is indicated: 19 write counter 1.1; 20 write counter 1.2; 21 rewrite counts; 22 read counter 23 - write trigger 1 24 write trigger 2 25 overwrite trigger 26 read trigger 27 logic circuit OR.

 When you turn on the device to the input of the recording counter 1.1-19 received clock pulses "Ti Zap. 1.1". On the second input of the recording counters 1.1-19, the signal "Int. Rec. 1.1" (parallel binary code) is written to the recording counter 1.1-19 as a binary number that defines the recording interval. In this case, the recording trigger 1-23 with the signal "Set Tr. Rec. 1" is set to "1". Triggers: recording 2-24, overwriting 25 and reading 26 with the corresponding signals are set to "0".

 The input signal of the recording counter 1.1-19 goes to the input of the recording trigger 1-23. From the output of the recording trigger 1-23 through the logic circuit OR 27, the control signal "Zap.1.1" is fed to the input of RAM1 13.

 This signal determines the recording interval of the input signal in RAM1 13. The write counter 1.1-19 operates in the "subtraction" mode. Periodically, after a time equal to the recording interval of the samples of the signal and noise mixture in RAM1 13, the recording counter 1.1-19 gives the signal “K.Int.Zap.1.1” to the time matching circuit 1-15.

 With the signal “K. Int. Rec. 1.1”, the recording trigger 1–23 is set to “0”, and the overwriting trigger 25 is set with the signal “Set Tr.Perezap” to “1”. The overwrite counter 21 receives the clock pulses "Tee. Count." The input signal of the overwrite counter 21 goes to the input of the overwrite trigger 25. From the overwrite trigger 25, the signal “Count. 1” is fed to the input of RAM1 13, and the signal “Rec. 2” is fed to the input of RAM2 14. RAM1 13 goes into read mode, and RAM2 14 to recording mode. The recording interval in RAM2 14 is equal to the reading interval from RAM1 13. The recording interval is much less than the recording interval of the input signal in RAM1 13.

 After the dubbing is completed, the dubbing trigger 25 is set to "0", and the triggers for recording 2-24 and readout 26 with the corresponding signals "Set Tr. Rec. 1.2" and "Set Tr. Count." set to "1". From the trigger record 2-24 through the logic circuit OR 27 to the RAM1 13 receives the signal "Zap.1.2", which controls the recording of information in RAM1 13. The reading of the information signal from RAM214 is carried out under the control of the signal "Read.2". The signal "Read.2" is supplied to RAM2 14 from the read trigger 26.

 The interval for reading information from RAM2 14 is less than or equal to the interval for recording information in RAM1 13. After a time equal to the interval for recording samples of the mixture of signal and noise in RAM1 13, periodically, the write counter 1.2 20 gives the signal "K.Int.Zap.1.2". The signal "K.Int.Zap.1.2" arrives at the time matching circuit 2 16. The signal "K.Int.Zap.1.2" writes the write trigger 2 24 to "0", the read trigger 26 is already set or is set to "0" , and the overwrite trigger 25 with the signal “Set Tr. Reset” is set to “1”, and the search cycle in compressed time is repeated.

 When two RAMs are connected in parallel, a block diagram of the device is shown in FIG. 2, where indicated: 1 analog-to-digital Converter; 2 register numbers; 13 random access memory 1; 14 random access memory 2; 4 register numbers; 5 detector 1; 15 timing matching scheme 1; 16 matching scheme for time 2; 18 control circuit; 7 detector 2.

 The input of the device is connected to the input of the analog-to-digital converter 1 and the first input of the detector 2 7. The output of the analog-to-digital converter 1 is connected to the input of the register number 2. The first output of the register number 2 is connected to the first input of RAM1 13. The second output of the register of number 2 is connected to the first the input of RAM2 14. The second and third inputs of RAM1 13 are connected to the first and second outputs of the control circuit 18. The second and third inputs of RAM214 are connected to the third and fourth outputs of the control circuit 18. The output of RAM1 13 is connected to the first input of the register number 4. Output of RAM2 14 soy is dined to the second input of the register of number 4. The output of register 4 is connected to the input of the detector 1 5. The first output of the detector 1 5 is connected to the first input of the time matching circuit 1 15. The second input of circuit 1 15 is connected to the fifth output of the control circuit 18. Second output of the detector 15 is connected to the first input of the time matching circuit 2 16. The second input of circuit 2 16 is connected to the sixth output of the control circuit 18. The output of the time matching circuit 1 15 is connected to the input of the detector 2 7. The output of the time matching circuit 2 16 is connected to another input discover For 2 7. The detector output 2 7 is the output of the device.

 The device operates as follows.

 The input signal through analog-to-digital Converter 1 and the register of number 2 is recorded in RAM1 13. The interval for recording samples of a mixture of signal and noise in RAM1 13 is determined by the control circuit 18.

 After completing the recording of the input signal, RAM1 13 enters the read mode. Information from RAM1 13 is read through the register of the number 4 to the detector 1 15. At the same time, new samples of the signal and noise circuits are recorded in RAM214. The interval for reading information from RAM1 13 and the interval for recording information in RAM214 are determined by the control circuit 18.

 Detector 1 5 searches for a signal in compressed time. Coordination of a copy of the signal in the detector 2 7 with the alarm point on the time axis is carried out by the time matching circuit 1 15. When an alarm occurs, the detector 2 7 checks it. If the detector 2 76 decides on the presence of a signal, the search is terminated.

 Otherwise, information from RAM2 14 is read to the detector 1 15. New samples of the mixture of signal and noise are simultaneously recorded in RAM1 13. The time matching is now carried out by the time matching circuit 2 16. Then, the detector 2 checks again. 7. The signal search cycle in compressed time continues until the signal detector.

 One of the possible control options for parallel connection of two RAM is presented in figure 4, where it is indicated: 28 write counter 1; 29 write counter 2; 30 counter read 1; 31 read counter 2; 32 trigger record 1; 33 trigger recording 2; 34 trigger read 1; 35 read trigger 2.

 When you turn on the device to the first input of the recording counter 1 28 received clock pulses "Ti.Zap.1". On the second input of the recording counter 1 28 the signal "Int.Zap.1" (parallel binary code) in the write counter 1 28 is written a binary number that defines the recording interval. Trigger 1 32 with the signal "Set Tr. Rec. 1" is set to "1". The remaining triggers are set to the "0" position by the corresponding signals.

 The control signal "Zap.1" with a recording trigger 1 32 is fed to RAM1 13. The signal "Zap.1" determines the recording interval of the input signal in RAM1 13. The signal "K. Int.Zap.1" from the recording counter 1 28 periodically, through the time equal to the recording interval of the input signal in RAM1 13 arrives at the time matching circuit 1 15. By the signal "K.Int.Zap.1", the recording trigger 1 32 is set to "0". At the same time, the trigger for recording 2 33 with the signal "Set Tr. Count 2" and the trigger for reading 1 34 with the signal "Set Tr. Count 1" are set to "1".

 From the trigger of recording 2 33 to the input of RAM2 14, the signal "Zap.2" is received, which determines the interval of recording information in RAM2 14. Periodically, after a time equal to the recording interval of the input signal in RAM214, from the write counter 2 29 to the time matching circuit 2 16 the signal "C.Int." Zap.2 "is given.

 At the same time, from the read trigger 1 34, the signal “Read 1” is received at the input of RAM 1 13, which determines the interval for reading information from RAM 1 13.

 After recording the samples of the mixture of signal and noise in RAM214 and reading information from RAM113, the triggers: write 2 33 and read 1 34 are set to "0", and the triggers: write 1 32 and read 2 35 to "1". Thus, RAM 1 13 and RAM 14 operate in opposite modes.

 When RAM1 13 is in write mode, RAM214 is in read mode. Then the RAM switches to opposite modes, which ensures the continuity of the system.

Claims (2)

 1. A noise-like signal search device comprising a series-connected analog-to-digital converter (ADC), a first number register and a first RAM node, a second number register, a first detector, a first matching node, and a second detector connected in series, the device input being connected to the input The ADC and the second input of the second detector, characterized in that, in order to reduce the search time, a second RAM node, a control node and a second matching node, the first input to The second is connected to the output of the first detector, and the output is connected to the second input of the second detector, while the first and second outputs of the control unit are connected respectively to the third and fourth inputs of the first memory node, the output of which is connected to the first input of the second RAM node, the third and fourth whose inputs are connected to the second inputs of the first and second matching nodes, while the output of the second RAM node is connected to the input of the second register of the number.  2. The device according to p. 1, characterized in that the second node of the RAM is connected in parallel with the first node of the RAM, while the first inputs of the said nodes are combined and connected to the output of the first register of the number, and their outputs are combined and connected to the input of the second register of the number.

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