SU1553985A1 - Correlator - Google Patents

Abstract

The invention relates to measuring and computing. The purpose of the invention is simplification. In the correlator, the average product of the two signals is determined without applying the multiplication operation. This is achieved by the fact that one of the signals is recorded in the accumulation mode (summation with the previous record) in a memory block at the addresses determined by the second signal. The resulting record is played in decreasing order of addresses, and the reproduced signal is averaged twice over time. The correlator contains a delay block 1, accumulating adders 2.3, adders 4, 11, memory blocks 5, registers 6, switch 7, blocks 8, 10 of sign inversion, normalization block 9, synchronizer 12. 2 Cp. f-ly, 1 ill.

Description

bm

listened to

go x eo ate

The invention relates to measuring and computing techniques and can be used in signal processing systems.

The purpose of the invention is to simplify the device.

The drawing shows a diagram of a correlator.

The correlator contains a delay unit 1 accumulating adders 2 and 3, adders, C, memory blocks 5, registers 6, switch 7} sign inversion blocks 8, normalization block 9, sign inversion block 10, adder 11, and synchronizer 12.

The correlator works with the following trim.

Coming from the output of block 9 sig

five

39854

After writing to the memory blocks 5 of the part of the corresponding set 1-K

ten

X signal

duration T, the sequential processing of each of the received records begins. At the same time, the record is played in order of decreasing p. Reproducible from the output of block 5, the signal Zh (k) is fed through the switch 7 to the input of the first accumulating adder 2, at the input of which for successive times (steps) we have:

s to

about -

Vi +

Jh-Ј

v,

ZN-4 +

+ Z.

or

N ° Y- is fed to a sign inversion unit 10, where its modulus / Y- | therefore, the size is reduced by one (character bit) t that goes to the address blocks of 50pam and determines the cell address of each of them into which it will be recorded. The contents of this cell are rewritten into the corresponding register 6 and fed to the input of the corresponding adder k, to the second input of which from the corresponding (output of the delay unit 1 through the sign inversion unit 8 the second of the analyzed signals X is fed with the corresponding delay. Since blocks 8 and 10 are controlled by one by a signal (sign Y |) they do not change the sign of the product X; Y ;.

The sum obtained at the output of the adder k is written into the above-mentioned cell of the corresponding block 5o. As a result, the sum with the number n accumulates the sum Zh (k) of those values X; with the corresponding sign for which (V;) n. Consequently,

mi

 Y;

max Y;

n

Zh (k), (1)

Considering that the actual value of YJ is proportional to the value (Y;

- Y +

.)

1) Y; +

for more than 1

 2

evaluating the correlation function, we get the expression AND

Kuliu 21

(n + -) Zn (k),

Consequently, at the output of the second accumulating adder 3 in the penultimate and last step, we respectively:

m- "

five

0

five

0

45

50

five

 and

-, - V

si +

. .. + SM

(Ds

(3)

CNH

zn +

s

(four)

which coincides with the expression МZl (n

From expressions (3) and (k) it can be seen that both СN and Сц give the same estimate of accuracy for the correlation function Hxu (k), respectively, from above and below, up to a constant factor

From expression (4) it follows that at the output of adder 11 (output of the correlator) we obtain expression (2) corresponding to the most accurate estimate of the correlation function RXU (k).

invention formula

Claims (3)

1. A correlator containing a delay unit, two accumulating adders, a synchronizer, the information input of the delay unit being the first input of the correlator, the first synchronizer output connected to the clock input of the delay unit, the second synchronizer output connected to the clock inputs of the first and second accumulating adders, characterized in that, in order to simplify, the correlator contains N memory blocks, N registers, N adders, a switch, and the address inputs of the memory blocks are connected to the second input of the correlator; pa, i-th, ..., N output of the delay block is connected to the first input of the Ј-th adder, the output of which is connected to the information input of the 1st block memory, the output of which is connected to the Ј-th information input of the switch and with the information input of the i-th register, the output of which is connected to the second input of the 1st adder, the output of a com-unit simplification due to decreasing the mutator is connected to the information input of the first accumulating adder, the output of which is connected to the information input of the second accumulating adder, whose direct output 15 is the output of the correlator, the third synchronizer output is connected to the write-read enable input of each memory block, the fourth synchronizer output is connected a clock 20 input of each register, the fifth output of the synchronizer is connected to the control input of the switch. 2. The correlator of claim 1, characterized in that, in order to improve accuracy, it is entered into it (N + D th adder, first and second the inputs of which are connected respectively to the output of the second accumulating adder and with the inverse output of the first accumulating adder, the output of the (N + 1) -ro adder is the output of the correlator. 3. Correll torus on PP. 1 and 2, differing in that, since 50 five the memory of the memory blocks, it contains the (M + 1) sign inversion block and the normalization block, the input of the normalization block is the second input, the correlator, the clock input of the normalization block is connected to the sixth synchronizer output, the i-th output of the delay block connected to the information input of the 1st sign inversion unit, the output of which is connected to the first input of the 1st adder, the output of the rating unit is connected to the information input; the input of the sign inversion unit, the output of which is connected to the address input of each memory block, the sign control input of each sign inversion block is connected to the sign input of the second correlator input.