SU1501087A1 - Device for determining weight functions - Google Patents

Abstract

The invention relates to computing and can be used in the diagnosis of complex dynamic systems. The purpose of the invention is to increase accuracy and speed. The device contains a drive 1, groups of 4.9 multiplication blocks, registers 5, 11, 13, 20, 22, quadrants 16, 18, a divider 19 by a constant coefficient, adders 6, 21, accumulating adders 14, 17, multiplying blocks 8, 12, 15, quadrant 18, group 10 of elements I, synchronization unit 2, dispersion calculation unit 3, memory block 7. Using the a priori known correlation function of the useful signal in the device operation algorithm reduces the transient time and time on each step adaptation. 1 il.

Description

315

The invention relates to computing and is intended to be implemented in diagnostic systems for complex dynamic objects.

The purpose of the invention is to improve the accuracy and speed of the device.

The diagram shows the block diagram of the device.

The device contains a storage unit 1, a synchronization unit 2, a dispersion calculation unit 3, a group of blocks 4 at a log, a register 5, an adder 6, a memory block 7, a multiplication unit 8, a group of multiplication units 9, a group of elements 10, a register 11, a block 12 multiply, register 13, accumulating adder 14, multiplication unit 15, group of quadrants. 16, the accumulating adder 17, the quad 18, the divisor 19 by the constant coefficient j register 20, with amm-ator 21 and the register 22.

The device works as follows

Samples of the random input signal that go to the inputs of the system, accumulator 1 and dispersion calculator 3, are recorded in accumulator 1, in which information of the form X (j) x (j), xCj-l) ,,., () Is stored. , Signals: from the system output go to the inputs of a group of 4-multiply blocks. The trigger signal starts synchronization block 2: The signal from block 2 opens the dispersion calculation block 3, and also enters the input of accumulator 1, providing simultaneous reading of information X (j) to the inputs of blocks 4 and 9 of the multiplication, logic elements And 10 "16" quadrants. On outputs of multiplication blocks 4, vectors y (J) X (j) are formed, which are written one-to-one in register 5. After the time required to perform these operations, the group n of read pulses is generated at the output of synchronization unit 2 consistently arrive at input of memory block 7.

displaced normalized value of the correlation function The values of the normalized correlation function RC (J) are multiplied in block 8 multiply1P1 by the current input signal variance and are subsequently fed to the input of the adder 6, to the second input of which signals from the S register are received sequentially

0

five

0 0

five

0

five

74

pulses coming from block 2. In the sum of the matrix 6, the elements of the multidimensional signal y (j) X (j) and) g are successively added

ry (j) x (j) -Rjj).

. The received signals are recorded in register 13. The synchronization signal c also opens the first of the logical elements AND 10. The signal x (j) passes to all inputs of multiplication blocks 9, to the other inputs of which input elements of the input vector X (j) x (j) x ( jl).,. x (jn).

At the outputs of blocks 9 for multiplying the formotots, the signals of the first row of the matrix X (j) X (j) - X (j) x (j), which are recorded in the register 11, at the same time, at the outputs of the quadrants 16, signals are generated that are proportional to the squares of the input signals, which arrive at the inputs of accumulating adder 17, at the output of which there is a scalar signal} ((j) X (j).

After. performing these otiepations, block 2 generates a signal C2, which is fed to the inputs of registers 13 and 11 and the input of accumulating adder 17. Signals from the outputs of registers 13 and 11 are multiplied element by element in block 12 multiply and fed to accumulating adder 14 , in which the scalar value X (j) x (j) y (j) X (j) R (j) is formed. .

The signal from the output of accumulator adder 17 is fed to the input of the last quad 18, at the output of which a scalar square is formed. signal | 2i (j) x (j) i. This signal goes to the input of the divider 19, at the output of which there is a signal opposite to the input one. This signal is supplied to the input of block 15 multiplication. After executing these operations, unit 2 generates a signal Sz, which is fed to the input of Accumulating .. adder 14, displaced the scalar value - the signal X (j) x (j) x y (.j) X (j) -Rjj) to the input of the block 15 times the output of which will be a number

, w (j) | iMiL y (j) x (j) .R, p),

which enters the register input 20 /

Upon completion of the calculation and recording of tiW (j) in register 20, unit 2 generates a C4 signal, which performs a reset

to the initial registers 11, 13 and 5 and on the power adders 17 and 14.

After that, unit 2 generates a signal C5, which is fed to the inputs of accumulator 1, unit 3 for calculating dispersion, quadrant 16, blocks 4 and 9 for multiplication and element 10. UW (j-I) is formed

X (j) x (j-) rv / Nv -N n

- frlI) x7j) / T L (j) x (j) -R ,, (j) J,

which enters, the input of register 20. So repeats until all values (j) are recorded in register 20.

After writing n values of W (j) to register 20, block 2 generates a signal C,,, which is fed to the inputs of registers 20 and 22, displacing the values of the signals W (j) and the old values of the weight functions W (j) obtained in the previous step in the adder 21, where the formation of a new value of the vector of weight functions W (j + l)

gt

Sh10L Gu (|) x (P (x (j) x (j) | 2

w (j + i) w (j) + -R (j). .

The use of values in the formation of weight coefficients increases the rate of convergence and reduces the gap.

Claims (1)

Invention Formula A device for determining weight functions, comprising a accumulator, first and second multiplication groups, a first register, a group of quadrs, two accumulating adders, a divider by a constant coefficient, a first adder, a memory unit, two multiplication units, the information input of the accumulator being the first the information input of the device, the group of outputs of the accumulator is connected to the first information inputs of the corresponding multiplication units of the first and second groups and with the inputs of the corresponding quadrants of the group, the outputs ryh connected to respective data inputs of the first accumulator, to output a constant divider ratio is connected with first information input of the first multiplying unit, wherein ten t5 010876 that, in order to increase accuracy and speed, a quad, an I, second, third, fourth, and fifth registers group, a dispersion calculation unit, a second adder, a synchronization unit, and a third multiplication unit, the second information inputs of the multiplication units of the first the groups are the second information input of the device, the outputs of the multiplication blocks of the first group are connected to the corresponding bit inputs of the first register, the output of which is connected to the first information input of the first adder, the output of which connected to the information input of the second register, the output of which is connected to the first information input of the second multiplication unit, the outputs of the multipliers of the second group are connected to the corresponding bit inputs of the third register, the output of which is connected to the second 25 information input of the second multiplication unit, the output of which is connected to the information input of the second accumulator adder, the output of which is connected to the second information input of the first multiplication unit, the output of which is connected to the information input of the fourth register, the output of which is connected to the first information input of the second adder, the output of which is connected to the information input of the fifth register and is the output of the device, the output of the fifth register is connected to the second information input of the second adder, the output of the first accumulating adder is connected through the quadrant to the input of the divisor to a constant coefficient, the group of outputs of the accumulator is connected to the first inputs of the corresponding AND elements of the group, the outputs of which are through the i-ro element (, 2, .., N, where N is the sample size, nature The number of the installation OR is connected to the second input of the i-ro multiplication unit of the second group, the information input of the dispersion calculation unit is connected to the first information input of the device, and the output is connected to the first information INPUT of the third multiplier of the multiplication unit, the output and second input of which are connected respectively to the second information input. the input of the first adder and the output of the memory block, a group of outputs of the synchronization block thirty 35 40 50 55 connected to the second inputs of the corresponding; their elements AND groups, with the group of recording enable inputs of the accumulator and through the mounting OR element with the recording resolution input of the dispersion calculating unit, the first output of the synchronization unit connected to the clock inputs of the first accumulating adder, second and third registers, the second the output of the synchronization unit is connected to the clock input of the second accumulating adder, the third output of the synchronization unit connected to the reset inputs of the first and second accumulating adders, first, second and third registers, the fourth output of the synchronization unit is connected to the clock inputs of the fourth and fifth registers, the fifth output of the synchronization unit is connected to the read enable input of the second adder, the sixth output of the synchronization unit is connected with reset inputs - the first and second accumulating adders, with reset inputs from the first to the fourth registers.