SU1713094A2 - Shaper of paired pulses - Google Patents

Abstract

The invention relates to a pulse technique ^ and can be used in automation and computing devices. The purpose of the invention is the formation of output pulses, following in pairs with an interval of several periods of the clock frequency, is achieved by introducing the third element AND-HE 5, the third and fourth triggers 8, 9, and the third input bus 13. The device also includes a generator of 1 clock pulses, the first and second elements AND-NOT 2, 3. first trigger 4, reversible counter 6, second trigger 7, first and second input tires 10 and 11, initial installation bus 12, code bus 14, first and second output tires 15 and 16. Zil.

Description

The invention relates to a pulse technique, can be used in automation and computing devices and is additional to the main author. St. N 1499455

The purpose of the invention is the expansion of the field of application by allowing the formation of output pulses, which follow in pairs with an interval of several periods of the clock frequency.

Figure 1 shows the electrical functional scheme of the device; 2 and 3 are timing diagrams explaining its operation.

The paired pulse shaper contains a generator of 1 clock pulses, the first 2 and second 3 elements are NAND, the first trigger 4, the third element NAND 5, the reversible counter b, the second, third and fourth triggers 7-9, the first 10 and second 11 input tires, initial installation bus 12, third input bus 13. code bus 14, first 15 and second 16 output buses.

The first in; the stroke of the first element AND-NOT 3 is connected to the direct output to the second trigger 7. The second input of the element AND-NE 3 is connected to the first input of the reversible counter 6, to the second input of the second AND-NOT 2. to the first input bus 10, to the trigger setup input 7, to the first setup input of the third flip-flop 8, to the second reset input of the fourth flip-flop 9 and to the first installation booth of the first trigger 4. The third input of the AND-HE element 3 is connected to the third input of the AND-HE element 2, s the second input of the installation of the reversible counter 6, with the second input of the installation trigger 8, with the second input bus 11, with the reset input of trigger 7, with the first reset input of the trigger 9 and with the second input of trigger setup 4. The fourth input of the element AND-NOT 3 is connected to the fourth input of the element AND-NOT 2 and to the output of the generator 1 clock pulses. The first input of the element AND-NOT 2 is connected to the inverted trigger of trigger 7. The first input of the third element AND-NOT 5 is connected to the output of the element AND-NOT 2 and to the summed relay input of the reversing counter b. The second input element AND-NOT 5 is connected to the inverse output of the trigger. 8. The third input of the NAND element 5 is connected to the forward output of the trigger 9. The fourth input of the NAND element 5 is connected to the output of the NAND element 3 and to the subtractive input of the reversible counter 6. The Fifth input of the NAND element 5 is connected to input bus 13. The output of the NAND element 5 is connected to the third input of the reversible counter 6 installation and to the counting inputs of flip-flops B and 9. The first output of the reversing counter b is connected to the first counting input of the trigger 7, to the reset input of the trigger 8 to the first output bus 15. The second output of the reversing counter 6 is connected to the second circuit. the trigger input 7, with the trigger setup input 9 and the second output bus 16. The information inputs of the reversible counter 6 are connected to the code bus 14. The reset input of the reversible counter 6 is connected to the inverse output of the trigger 4. The reset input of the trigger 4 is connected to the initial installation bus 12 .

In Figures 2 and 3, the voltage chart designations correspond to the positional numbers of the circuit elements of Figure 1.

Shaper paired pulses works as follows.

In the first of the two modes of operation of the imaging unit (Fig. 2), a logic level O is continuously applied to the input bus 13, and two pulse sequences are formed on the output buses 15 and 16, which are separated by a time interval in the half-cycle of the clock frequency.

At the output of the element AND-NOT 5 in this case, level 1 is permanently valid.

When entering through the bus 12 pulse

the initial installation at the inverse output of the trigger 4 appears level 1, over which the counter 6 is reset to the zero state, tires 15 and 16 have level 1, i.e. no signals.

The input signal via bus 10 causes trigger 7 to become state 1, count 2 is entered on bus 14 by number 2, where N is the number of bits of counter 6 (a number equal to half: the capacitance of the counter), trigger 4 switches, this, from the input R of counter 6, the blocking is removed, the elements AND-NOT 2 and 3 are locked with the level O from the bus 10. The triggers 8 and 9, switched by input signals, are not

affect the operation of the device, since the element AND-NOT 5 is permanently locked with the level O from the bus 13. After the termination of the signal on the bus 10, the element AND-NOT 3 transmits pulses from the generator output

1 to the subtracting input of the counter 6.

After zeroing the counter 6, the next pulse from the output of the element IS-HE 3 in the estimator 6 is set to 2 - 1, an negative overflow pulse (loan) is received from the output BR of the counter b on the output bus 16. According to this pulse, trigger 7 switches to the zero state, at which the level G appears at the input of the AND-HE element 2, therefore the next pulse from the output of the generator 1 passes through the AND-HE element 2.

On this pulse, the counter 6 has zeroed out, and at its positive overflow (carry) CR output and the output bus 15, a pulse appears that switches the trigger 7. This process repeats until the signal appears on the bus 11. During this signal, the elements AND-NOT 2 and

3 locks, trigger 7 is set to zero, the number 2 is entered into counter 6 After the signal on bus 11 terminates, the IS-NOT element 2 passes pulses from the output of generator 1 to the summing input of counter b until the counter is zeroed out and a transfer signal appears at the output CR

and output bus 15. Next, the process is repeated.

When a signal is sent through the bus 12 trigger

4yctanavlc in the zero state, its signal blocks the counter 6 and the output signals are not generated.

When the first signal arrives on bus 11, trigger 4 switches over input S2, the number 2 is entered into counter 6, and the whole process is repeated,

In the second mode of operation of the imaging unit (FIG. 3), the level 13 is continuously fed to the bus 13, in this case two output sequences are formed on output buses 15 and 16, following pairs in pairs with a time interval of several clock periods (the time interval depends on the number which is recorded in the counter 6).

When a pulse of the initial installation appears on the bus 12, the trigger 4 switches to the zero state, providing the b: 1 lock of the counter b.

On a signal on bus 10, trigger 7 is set to state 1, and the number 6 is entered into counter 6, trigger 4 is switched, blocks are removed from input R of counter b; The I-NOT 2 and 3 elements are locked with the level O from the bus 10. At the same time, the trigger 8 on input 1 is set to one (the level O on the inverse output), and the trigger 9 on input R2 is reset to zero ( level O at the direct output). After the termination of the signal on bus 10, the IS-NOT 3 element starts to pass pulses from the output of generator 1 to the subtracting input of counter 6. Then after its zeroing, the next pulse in counter 6 is set to 2 - 1, and a loan pulse drops to the output bus 16 post from the output BR of counter 6, by which trigger 9 switches to state 1. On the falling edge of the pulse on bus 16, trigger 7 switches to cool

state, level 1 appears at the input of the AND-NOT 2 element, therefore the next pulse of the generator 1 passes through the NE-2 element. This pulse causes the counter 6 to zero and a transfer pulse from the output CR of the counter 6 enters the output bus 15 the trigger 9 switches to the zero state (inverse output level 1). On the right front of this pulse, trigger 7 again switches to state 1. At the same time, it means that level 1 appears at all inputs of the INE5 element, level O starts to act at its output, along which number 2 is entered into counter 6. When the next pulse of the generator 1 appears, the output of the IS-NOT 3 element is set to O, the NE-5 element is switched to state 1, and the triggers 8 and 9 are switched to the 1 and O state on the counting inputs (on the inverse of the trigger output) 8 and at the direct output of the trigger 9 levels O). Then, the reading of the input of counter 6 through the element AND-HE 3 begins to receive pulses from the output of generator 1 to its next zeroing, when the code of number 2 recorded in the counter is fully counted. Further, the work process is repeated.

When a signal is applied to the bus 12, the trigger 4. switches to the O state, and the counter 6 is blocked, while the formation of output pulses on the tires 15 and 16 is suspended.

Similarly, the device operates when the first signal arrives at bus 11. This driver of paired pulses, like the well-known driver, sends a logical 6 signal to the input bus 13 via an external control signal (on bus 10 or 11) through a certain delay, the value of which depends on the code values of the number 2 (a number equal to half the capacity of the counter 6) generates two pulse sequences, the pulses in which are separated in time by a half-cycle of the clock frequency. The phase shift between the pulse sequences depends on which of the input buses 10 or 11 comes a control pulse, in this case, this device can be used, for example, as a gating driver (pulse sequences) for data input from common buses memory devices (codes of increments of coordinates X and Y) to the registers of channels X and Y in control devices for displaying information on a CRT by electromagnetic beam deflection. Depending on which of the i 10 or 11 buses receives the control signal, the increment codes of the X and Y coordinates can be entered into the registers of the X and Y channels or, conversely, into the registers of the Y and X channels.

The delay between the arrival of the control signal, by which the codes are entered - the coordinates Ho, YO of the original image point, and the formation of the output sequences is necessary to complete the transients in the deflection system, i.e. output beam tube at a given point on the screen (coordinates Ho, YO).

In another case, when a local / 1 signal is applied to the input bus 13, this device generates two pulse sequences in which the pulses follow in pairs with a time interval of several periods of the clock frequency (the time interval depends on the code value of the number 2). After the formation of the next pair of pulses on the buses 15 and 16 is completed, due to the fact that the levels 1 appear at all inputs of the NAND 5 element, the number 2 is written to the counter b, i.e. The next pair of pulses is formed at the required interval.

This allows you to use this device in cases where the image consists of a certain number of points with XoYo coordinates; Xi, Yi; Xz, Y2, ... Xn. Yn (Xo, YO - coordinates of the initial point), scattered over a large distance from each other throughout the field of the screen. Each pair of pulses from the sequences is used to input one of the points with coordinates Xk, Yk (, ... n).

/ The indicated time interval between pairs of impulses of sequences nonLJiJllШ :: JШJlЖПЛJL: zLLLLJIJShSh

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go around to complete the transients in the deflecting system after entering the point with coordinates Xk, Yk, since only after the tube's beam has been outputted to a given point of the screen and its display, you can begin to enter the coordinate codes Xk + 1, Yk + i of the next image point.

Claims (1)

Claims of the invention Shaper of paired impulses St. No. 1499455, distinguishing with the fact that, in order to expand the scope of application by providing the possibility of forming output pulses, following in pairs with an interval of several periods-max frequency, a third input bus, a third AND-NOT element, a third and fourth trigger, the first input of the third element AND-NOT is connected to the output of the second element IS-NOT, the second input is with the inverse output of the third trigger, the first input of which is connected to the first input bus, the second input of the installation is connected to the second input of the installation {eversive the reset input is with the first output of the reversible counter, and the counting input is with the output of the third NAND element, with the third input of the reversible counter installation and the counting input of the fourth trigger, the installation input of which is connected to the second output of the reversible counter, the first reset input with the second input bus; agora reset input — with the first input of the first trigger installation, and the direct output — with the third input of the third I-THE element, the fourth input of which is connected to the output of the first AND – NO element, the fifth input-third input bus th .. pppg /five 1PPG / f gplg 1PPGG u e SI 55