SU1707776A1 - Data exchange device in shared-channel communication system - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is the expansion of functional capabilities. The device contains demodulator 1, modulator 2, block 3 of microinstructions memory, shift registers 4-7, detector 8. 9 clock pulse generator, control triggers 10-15, decoder 16. counters 17, 18 and 19, counter of microinstruction addresses 20 , blocks 21 and 22 comparisons, elements AND 23-39, elements OR 40-47, and blocks 48, 49, and 50 delays. The goal is achieved by transmitting information intended for any single group of stations or all stations of the network in one information packet. 1 il.

Description

The invention relates to telecommunications and can be used? transmission ration ^t GOVERNMENTAL messages in communication systems with a common channel as part of the network stations.

The purpose of the invention is the expansion of functionality by organizing the exchange of circular and circular’s electoral information.

The drawing shows a structural electrical diagram of the proposed device.

The device comprises a demodulator 1, a modulator 2, a micro memory instruction block 3, a first 4, a second 5, a third 6 and a fourth 7 shift registers, a detector 8, a clock generator 9, a first 10, a second 11, a third 12, a fourth 12, a fifth 14 and sixth 15 control triggers, decoder 16. first 17, second 18 and third 19 counters. the frequency ^and '1k of 20 addresses of microcommands, the first 21 and second 22 comparison blocks, the first - the seventeenth AND 23-39 elements, the first - the eighth element OR 40 - 47, the first 48, the second 49 and the third 50 delay blocks, the general input - exit 51, additional first - eighth inputs 52-59 and additional first 60, second 61 and third! 5z conclusions.

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With yogi ... but ·· social 1 and triggers 10-15 exercise E ·. : And And, I am walking in · -4 / neFGM competition. l r-og '.-gr? “Tdg. cam-mr;. · code combiner '<pedtwo;: “dznil pg- ^a ” .a package ins: .., .. mg. .and. In counter 19, there was a numerical value of 3 г - -:? - ¹ . about.·. ¹ , '. Ches. t /.-belt intore -. 'rz r 1 t. <pre-limit;·' priority To glaxia (not poyuzan). Said yn fer 'gschich ps steps in the device information received from the packet processing unit (not show) station through assemblies 53 and 57: sstgg; s ^t venno..

In the free mode of operation, if there is a possibility that the station transmits a packet of information, according to the control signal · .. h <after inputs 52,54 and 58 of the device from the processing unit of the transmitted -.-. Packets of the station, the information goes to registers 4 and 'J the shift and the counter 20 are code combinations, ^ responsibly the information and control parts of the transmitted information packet and the value of the initial pointer of the addresses stored in the flea 3 of the memory memory.

The signal The beginning of the transmission, coming from the processing unit of the transmitted packets of information of the station to the input 59 of the device, passing through the open, in the absence of signal transmission in the shared channel, the And 26 element switches to a single state the control trigger, which then opens the And 25, 33 elements and 38 and closes the element And

30. Through the open element And 25 from the first output of the generator 9 clock pulses to the shift input of the shift register 6 receives the clock signals, thereby initiating the reading of the written code combination of the control part of the transmitted information packet in the serial code to its own serial information input and through the OR element 41 to the input of modulator 2, which transmits it to the output 51 of the device in the channel of collective use.

The signals transmitted by the device through the collective channel are received at the input 51 of the device to demodulator 1, then fed to the inputs of the detector 8 and the shift register 7. In this case, a signal appears at the second output of detector 8, which indicates the appearance of any transmitted signals in the collective cant, which switches the control tripper 0 to a zero state, which, in turn, fades the And 26 element, thereby prohibiting arrival π _{ν to the} input 59 of the device of the new signal Start of transmission · '.

By filling in the shift register 7 at the output of the decoder 16, in the case of identification of the code combination of the initial flag of the information packet, a single signal appears, which through the open element And 33 enters the second control input of the shift register 6, thereby initiating the reading of the code combination ide. the gipification code in parallel code to the second group of inputs of the comparison unit 22, the first group of inputs of which receives the code combination of the identification code received from the collective use channel of the information package. In the case of non-comparison, the identification signal, which, when output to the device output 61, notifies the processing unit of the transmitted information packets of the station about the termination of transmission due to a conflict with the packet with higher priority information in the collective channel, and passing through the OR elements 42, 44 and 46. Resets the shift register 7, control triggers 11 and 12, respectively. When comparing 5 17 identification codes at the first output of the comparison unit 22, a single signal is supplied to the second inputs of the elements OR 42 and AND 38. In the first case, it resets shift register 7, in the second, passing through delay unit 50 and delaying for a while, griori-determined assuring that station K, it switches to singly tsgoyani'e zero state and accordingly triggers 12 .. 11 y, - pressure unit signal from the output of flip-flop from control 12 ^ * ^t kryvae aND gates 23 and 39, thereby permitting flow to register input 4 move in! sinhsosigna-'ov with the first, about 9 generatooa output clock momenta In this case, the codeword is part of the information transmitted packet data, stored in the shift register 4, e serial code through the OR Ή reads * * a modulator input and 2. for ^t on exit 51, we’ll arrange the RH into the channel of the collective city. Go to the end of reading the contents of register 4 shift at the output of the element OR 47 is set to zero si, cash. which, passing through the open element And 3 ^e opens the element And

32. Дс *. · Трр 8, having established the fact of the end of the transmission in the channel, “the selective use of signals, it gives a signal at the first output that switches control trigger 10 to a single state

Successfully transmitting a packet of information to the channel. the device switches to the second mode of operation, which implements the collection of confirmations from the recipient stations.

The signals received from the collective channel at the input 51 of the device are fed to the demodulator 1. The output of which passes to the shift register 7 and detector 8. The signal that appears in this case at the second output of the detector 8 switches the control trigger 10 to zero and goes to the delay unit and element And 32. From the output of the delay unit 49, which delays it for the time of recording the received signals in the shift register 7, the signal passes through the open, in case of discrepancy between the initial combination of the received code combination signals the initial flag of the information packet, the AND element 31 to the fifth input of the OR element 42 and resets the shift register 7. At the same time, acting in the open, if there is no shift in register 4 of the information packet ready for transmission, element And 32, the signal then passes to the counter in the input of the counter 18, subtracting from the contents of it equal to the specified number of confirmations for the transmitted to the channel pa76 6 ”em information unit. In the case of resetting the counter 13 from its output, a signal is sent to the device output 62, notifying the processing unit of the transmitted information packets of the station about the acknowledgment of the receipt of the transmitted information packet by all stations by the network recipients, and through the OR element 46. the control trigger 12 switches to the zero state.

In the receive mode from the collective channel of the information packet, the device operates as follows.

The signals received from the channel from the output of the demodulator 1 go to the shift register 7 ι detector 8. Upon completion of the shift register 7 at the output of the decoder 16, in case of identification of the code combination of the initial flag of the information packet, a single signal appears that passes through the open signal, if necessary at the station of transmitting its own information packet, the And element 30 switches the control trigger 13 to a single state. A single signal from the output of the trigger 13 of the control opens the element And 28 and enters the control input of the block 3 of the memory microcommands, thereby allowing the written in it code combinations of addresses in parallel code to the second group of inputs of the block 21 comparison, the first group of inputs of which the code combination destination addresses received from the channel from the record. > * wth in register 7 shift information packet. Comparison of addresses in the block 21 comparison occurs under the control of a clock pulse coming from the second output of the generator 9 clock pulses to the capturing input of the block 21 comparison.

In the case of incomparable addresses, a signal appears at the second output of the comparison unit 21, which arrives at the counting input of the counter 20, increasing its content by one, thereby initiating the reading of microcommands from the memory 3 to compare the code combination of the next address. In the next word, when address codes are completely enumerated, the address combinations stored in block 3 of the microcommand memory are completely enumerated, the unit signal is set to the second output of this block. opening the element And 27, passes through it a signal from the second output of the comparison unit 21. This signal, passing through the OR elements 40 and 42, resets the counter 20 and the shift register 7, respectively.

In the case of address comparison, a signal appears at the first output of the comparison unit 21, which switches the control trigger 14 to the single state. passing through the OR element 40, it resets the counter 20. A single signal from the output of the trigger 14 of the control is output to the device 60, notifying the processing unit of the received packets of station information about the reception of the addressed station information packet, and opens the And 29 element. Upon completion of reception from the channel of the control part a packet of information at the first output of the detector 8, a signal appears, which, having passed the open element And 28, enters the counting input of the counter 17. increasing its content ne unit. At the end of the reception of the information part of the information packet, the contents of the counter 17 also increases ne unit and becomes equal to two. At the same time, a signal appears at the output of counter 17, which resets counter 17 itself, switches control trigger 13 to zero state, resets shift register 7 through OR element 42, and goes to AND element 29.

Here, the device switches to the fourth mode of operation — issuing a confirmation of receipt of an information packet addressed to its station.

After passing the open element And 29, the signal from the output of the food counter 17 switches to a single state trigger 15 of the control, which opens the element And 34, and enters the input Oleg 48 delay. The delay unit 48 delays the signal by the time Ar, after which it enters the first inputs of the elements And 34 and 36. Having passed the openings in the confirmation mode of the And 34 element, the signal goes to the counting input of the counter 19, subtracting the value of Ar from its contents. If there is no transmission of any signals during the time Am in the collective use channel, the AND 36 element is open 40 and the signal, passing it, enters through the OR element 45 and open, in the event that the specified delay time K does not expire, At its priority K, AND element 37 to the second input of OR element 43. thereby organizing the execution of a cyclic sequence of actions that implements the function of issuing confirmation on the received information packet in accordance with the priority of station K.

Upon the discovery of the fact of the beginning of the transmission in the collective use channel of confirmation by any priority station of the network, a signal is generated at the second output of the detector 8, which switches the control trigger 10 to the zero state. The zero signal from the output of the control trigger 10 closes the element. And 36, breaking the organized network through it one of the branches of the cyclic sequence of actions that implements the function of issuing confirmation. In this case, this 5 cyclic sequence of actions is confirmed by means of its second branch, organized through the And 35 element. The signal issued at the end of the collective use confirmation channel 10 from the first output of the detector 8 signal, Passing through the open And 35 element, through the elements OR 45 and AND 37. enters the second input of the OR element 43, thereby providing 15 continuity of the cyclic sequence of actions that implements the function of issuing confirmation. When resetting the counter 19, which means the expiration of the delay time K-At for the confirmation by the given K-th station, a signal appears at its output, which closes the And 37 element, switches the control flip-flops 14 and 15 to the zero state and opens And 24 element. Through the open element And 24 from 25 of the first output of the generator 9 clock pulses to the sync input of the shift register 5 receives the clock signals, initiating the reading in the serial code of the confirmation code written in it. From the 30th output of the shift register 5, the signals are fed to its serial information input and through the OR element 41 to the modulator 2 for transmitting on the output 51 of the device to the collective channel,

Claims (1)

35 claims An information exchange control device in a communication system with a shared channel containing the first and second delay units, a decoder, a clock generator, the first output of which is connected to the second inputs of the first, second, and third AND elements, the outputs of which are connected to the sync inputs of the first, second, and 45 of the third shift registers, a detector whose input is connected to the output of the demodulator, the input of which is connected to the output of the modulator, the input of which is connected to the output of the second OR element, the first input which is connected to the output of the first shift register, the first control trigger, the output of which is connected to the first input of the fourth AND element, whose output is connected to the S-input of the second control trigger, the output of which is connected to the first input of the third AND element, the third control trigger, the output which is connected to the first input of the first element And, the fifth element And, the output of which is connected to the first input of the first element OR, the sixth element And, about the first counter, the output of which is connected to the first input of the seventh AND element, the fourth control trigger, the second counter, the third counter, the output of which is connected to the R-input of the fifth control trigger, while the output and serial input of the second shift register are combined, the output and the Hüller third register of translations input and ^g are combined and connected to the second input of the second OR gate, and a m l h yuscheesya and in that, in order to increase functionality by providing an exchange circular and circularly election of information iey, administered fourth shift register, a sixth control -rigger, two counter microinstruction address comparison unit, the eighth. the ninth, tenth, eleventh, twelfth, eleventh, fourteenth, fifteenth, sixteenth and seventeenth elements I. third, fourth, fifth, neck - the seventh and eighth elements OR. rubs and> C delay log ;! and the memory unit mi, -. RoKSMe-Щ, the circuit of the first outputs of which is connected to the berry group of inputs of the first shear block '·, the first group of inputs of which is connected to the third group of outputs of the fourth shift register, the zeroing input of which is connected to the output of the third OR element, the first input of which is the same as the output of the element I. the input, which is connected to the output ρ ·· '' χπ 6 + 1 which is under k ·. о-ен to the first input of the tenth evil? ^and '.? And ► R-input. · First trigger? upradsh-sh-i and to in; To the output of the detector, the first one. '. od · οτρροΓ; ·, is connected to the S-input of the first control trigger, with the first input of the hexag:: Шр ₍ , ·.,. η. _{Ι (} · the house of the triad-atoge of the element And The output of which is connected to the Persian. The input of the sixth email. is the IZI. The output of which is connected to a single element of the fifteenth element I. The output is connected to the first input of the fourth element OR, the output of which is connected through the first delay block to the first input of the twelfth element AND and to the first input of the fourteenth element I. the output of which is connected to the second / input of the sixth of the first OR element, the inverse input of the fifteenth And element is connected to the output of the third counter, with the R-ehods of the sixth control trigger and with the first input of the second And element, the output of the demodulator is connected to the information input of the fourth shift register, the second group of outputs of which is connected to the first group of inputs of the second a comparison unit, the second group of inputs of which is connected to the group of outputs of the third shift register.The second control input of which is connected to the output of the eleventh element I. The first input of which is connected to the inverter the input of the eighth AND element, with the first input of the sixteenth AND element and with the output of the second control trigger, the R-input of which is connected to the output of the fifth OR element, the first input of which is connected to the fifth input of the third OR element, to the first input of the seventh OR element and to the second the output of the second comparison unit, the first output of which is connected to the fourth input of the third OR element and to the second input of the sixteenth element I. whose output, through the third delay unit, is connected to the second input of the fifth OR element and to the S-input of the third a control trigger whose R-input is connected to the output of the seventh OR element, the second input of which is connected to the output of the second counter, the counting input of which is connected to the output of the tenth element I. The second input of which is connected to the output of the seventeenth element I. The single input of which is connected to the output of the third trigger control, the group of outputs of the first shift register is connected to the group of inputs of the eighth OR element, the output of which is connected to the inverse input of the seventeenth element AND the first group of outputs of the fourth shift register and connected to a group of inputs of a decoder, the output of which is connected with the inverse of the ninth element AND, with the second input of the eleventh element And and with the single input of the eighth element I. The output of which is connected to the S-input of the fourth control trigger, the output of which is connected to the control input of the unit memory of microcommands and with the second input of the sixth element And, the output of which is connected to the counting input of the first counter, the installed input of which is connected to the first input of the seventh element I. with the R-input of the fourth control trigger and the third input of the third OR element, the second input of which is connected to the output of the fifth element I. The first input of which is connected to the output of the micro-command memory block, whose address input is connected to the output of the micro-command address counter, the counting input of which is connected to the second input of the fifth AND element and to the second output the first comparison unit, the first output of which is connected to the S-input of the fifth control trigger and to the second input of the first OR element, the output of which is connected to the installation input of the micro-command address counter, information and the control inputs of which are combined, the second output of the clock generator is connected to 1 1 control input of the first comparison unit. the output of the fifth control trigger is connected to the second input of the seventh control element And whose output is connected to the S-input of the sixth control trigger and to the second input of the fourth control element And whose output is connected to the input of the first sound block, the output of the sixth control trigger is connected to the second input of the thirteenth control element and the second input of the twelfth element And, the output of which is connected to the counting input of the third counter. information and control inputs of which are combined, the third input of the second OR element is connected to the output of the second shift register, information and control inputs of which are combined, the output of the first control trigger is connected to the second input of the fourteenth element And, while the control and information inputs of the first shift register are combined, control and the information inputs of the first counter are interconnected, the control and information inputs of the third register are combined and the control and information inputs are third Its counter are interconnected.