SU1698995A1 - Device for matching digital data flows while transmitting audio signal - Google Patents

Abstract

The invention relates to computing and communication technology. Its use in digital broadcasting systems with independent sync generators improves transmission accuracy by eliminating distortions in the transmitted signal when matching the speeds of digital streams. The device consists of a transcoder 1, containing memory blocks 5,6, a switch 7 and a control signal generator 8, and a decoder 2 containing a switch 13 and a driver of 14 clock sequences. By introducing microprogram control blocks 3.4 into the transcoder 1, and in decoder 2 - blocks 9,10 of microprogram control and RAM blocks 11, 12, information is recorded alternately with one clock frequency and read it with another clock frequency with addition in transcoder 1 not Remaining samples of zero insertions and removing them in the decoder 2. 2 z.p.f- ly, 4 yl. (Л С Фм1 ою 00 О ю ел

Description

The invention relates to computing and communication technology and can be used, for example, in digital broadcasting systems with independent synchronous generators.

The purpose of the invention is to improve the accuracy of transmission by eliminating distortions of the transmitted signal when matching the speeds of digital streams,

Figure 1 shows the block diagram of the device; Figures 2 and 3 are examples of the execution of the transcoder control signal generator and the decoder clock pulse generator, respectively; 4 shows the principle of operation of the device.

The device consists of a transcoder 1 and a decoder 2. Transcoder 1 includes the first and second blocks 3 and 4 of the firmware, the first and second blocks 5 and 6 of the RAM, the switch 7 and the driver 8 of the control signals. The decoder 2 contains the first and second blocks 9 and 10 of the firmware control, the first and second blocks 11, 12 of the main memory, the switch 13 and the shaper 14 of clock sequences. In FIG. 1, information inputs 15, first and second clock inputs 16, 17, and device outputs 18 are also designated.

The shaper 8 control signals of the transcoder 1 are made (Fig. 2) on the pulse counter 19 on the NI and on the counter 20 on the N2 pulse, where NI and Na are the smallest possible integers satisfying

CONDITION Nr fT2 N2 fn, frl And tr2

the first and second clock frequencies respectively (at inputs 16 and 17). In Fig. 2, the first and second outputs 21 and 22 of the former 8 are designated (the first output 21 is the output of the counter 20 to N2 and vice versa).

The shaper of 14 clock pulse sequences contains (fig.Z) synchronizer 23, pulse counter 24 on N2, first and second counters 25 and 26 pulses on NI, first and second elements 27.28 I. Figure 3 shows information inputs 9 , the first and second clock inputs 30 and 3b (the first clock input 30 is the input of the first counter 25 to NI), the first to third outputs 32-34 (the first output 32 is the output of the first element 27 And).

Blocks 3, 4, 9 and 10 of the firmware can be pulse distributors.

Switch 7 at the end of the release of information from the next block of RAM creates at its outputs zero signals.

The synchronizer 23 of the driver 14 serves to match the time of operation of the counters 24-26 and can be performed, for example, as a set of buffer registers with decoders of various code combinations and trigger drivers of triggering (bumping) pulses.

Timing diagrams in FIG. 4 explain the principle of operation of the device for matching flows with a first clock frequency of 32 kHz and a second clock frequency of 48 kHz.

The device works as follows.

A digital audio signal (CAC) with the first clock frequency (Fig. 1a, samples conventionally shown in AIM format) is received at information inputs 15 into the transcoder and is simultaneously fed to the information inputs of its first and second memory blocks 5 and 6. Under the action of the pulses of the first clock frequency fVi, which arrives at the first clock input 16, the first firmware control unit generates recording signals, which are received from its first output to the input of the recording section of the first operating memory unit 5 for storing the first sample from the NI samples of the original CES. The number of samples N1 depends on the multiplicity of frequencies fT2 and fn and is determined from the expression NI fT2 N2 fri, where N2 is the minimum integer satisfying this expression and the condition that the ratio N2 / Ni is greater than or equal to one. This implies the requirement to fulfill the condition fV2 fri necessary for correct operation of the device. After storing the first NI samples in the first RAM block 5, the first firmware block 3 generates recording signals at its second output that arrive at the write resolution output of the second RAM block 6 to memorize a second sample of NI samples. While this recording of the second sample from the NI samples to the second RAM block 6 occurs, the second microprogram control unit 4 under the action of the pulses of the second clock frequency fT2. Arriving from the second output 22 of the imaging unit 8, to which the second clock frequency f is supplied from the second clock input 17, generates, at its first output, read signals that are received both into the first RAM memory unit 5 and the read resolution readout and prepare the data stored in it , to output to the trans decoder output 1. The normalizer is 8 in

this time, on the first output 21, generates a control signal to the control input of the switch 7, which switches the outputs of the first RAM block 5 to the transcoder 1 outputs. Thus, a sample of NI samples stored in the first block 5 of the operative memory, comes with a second clock frequency to the outputs of the transcoder 1. Since fri. then the number of samples following the second clock rate during the sampling period of the hub, should be greater than NI and equal to Na. Therefore, the imaging unit 8 all samples with numbers N NI zeroed em (in this example, the third count zeroed), i.e. controls switch 7 in such a way that at the time of the arrival of the clock pulse of the second clock frequency fT2, a zero voltage level is generated at the output of transcoder 1.

After the end of the entire cycle — writing samples to the second RAM block 6 and simultaneously reading from the first RAM block 5 — the entire operation is repeated, only with a count of samples in the first RAM block 5 and reading from the second block 6 RAM. Trachcoder's work

It will consist in the alternation of the described operations: At the outputs of the transcoder 1, a hub with the second clock frequency and additional zero readings will be formed (fig.4b).

The decoder 2 performs the inverse transform. The coded (with zero samples inserted) CCD with the second clock frequency fT2 simultaneously enters the decoder 2 to the information inputs of the first and second RAM blocks 11 and 12 and the former 14. The latter is synchronized according to the information sequence and begins to form clock sequences with clock frequencies fTi and fT2 which are output to the first and second microprogram control units 9, 10, respectively. Under the action of a sequence of clock pulses of the second clock frequency fr2, the second decoder unit 10 records NI sample samples. The DSP in the first memory unit 11 under the influence of signals from the second output 33 of the former 14, which produces at its first output 32 write signals, discarding inserted zero counts. At the end of the cycle of recording NI samples in the first block

I1, the second memory unit 10 of the firmware control starts you

50

five

0

n 5 0 5

five

working out the recording signals at its second output 33, connected to the recording enable input of the second RAM unit 12. These signals are used to record the next NI samples in the second RAM block 12. At the same time, the first microprogram control unit 9, according to a sequence of clock pulses with the first frequency, fri starts generating, on its first output, connected to the read enable input of the first main memory unit 11, read signals, which prepare the data for output to the decoder 2 output. At the same time, the former generates, via its third output 34 to the control input of the switch 13, control signals switching the outputs of the first RAM 11 to the outputs 18. Thus, at outputs 18, an initial information sequence is formed with the first clock frequency f without inserted zero samples, absolutely identical to the initial CCD. After issuing the NI samples, the entire cycle is repeated, only with the recording of the NI samples in the first memory block 11 and the reading from the second memory block 12, etc. alternating cycles and switching to the outputs 18 of the first and second blocks 11 and 12 of the RAM memory alternately

The operation of the shaper 14 is carried out by the synchronizer 23 on the allocation of a code combination. The combination of recorded samples can be as follows: zero and the following two informational ones (flash combination); informational, nupozoy and informational (second); two informational and zero (one third); two zero - from, 3 (the rest of the combinations are so useful, so that they can not be taken dims knowledge).

These combinations play an important role only at the moment of synchronization of the decoder 2; after synchronization is achieved, the synchronizer 23 does not affect the formation of clock sequences arriving at the outputs of shaper 14. In the case of recording of the null combination (pause), the synchronizer 23 does not start until the information sequence contains no samples other than zero. At the outputs 18, zero readings are respectively formed.

Thus, the output information 18 forms the original information sequence of the hub with the clock frequency fn without

the introduction of a graded code of zero samples,

co o u m v a “I. About 6 p and e and 1. / a r.ls; „} of matching the digits no iOKor, - jy to the audio signal, consisting1 13 tpc decoder and decoder, finskotsup eo; rrv - .: iT perpyy and The second blocks are about. eeti; 0y p0m ;. h switchboard and formac opag; 1 b, reinforcing signals; decoder with d h rk switch and shaper vj M --rioG8. e / ibHoe n clock pulseso, o and -f a; o y oo with the fact that, with a chuyu po.-ji.ii; ig uchmistm transmission for smog ydpa:: the - the transmitted signal by; -, - с -.- U.h, and the speed of the digital polchk, r. .-p4i. “. : Soder entered the first and BTOpoi i tViori. by jspa jihoro control, first i / i. OiJb; is; of the first block of the program yi j: P; enich are connected to the inputs of the resolution, respectively, of the perabgp and ij-r-jvoro blocks of the operational storage unit, part of the operating and information system, which are entered. are combined and are fori-forio-i-e (1 device inputs, the first and the outputs of the second unit nporpofilpogo at p & n: and connected to the choder pr -:; p Mije ii. yani respectively and memory, i rc- -I of which are connected to the respective switches of my switch and the second information of the switchboard, the outputs of which are shi and puhsdam transcoder, the second one of the second driver of the control unit 7 cwr ;, j / iOB .. evdimenes corresponding to the cinema with vi; i; -wL -f: ou "vi input of the switch and input of the top of the program control, the decoder is inserted period and second oh SxriOKt -, program management "first pstroy blocks of operative network, many different types of information" -5 komm;: correspondingly: otshono oyipeny with information- and. (the forwarder should be followed.) the decoder inputs, the first and the iypdc.ru outputs of the program control unit connect with the SMMg resolution inputs, respectively the first and second RAM blocks, the outputs (seven of them are connected respectively to the first ii second forms of the common comm inputs (agora, .. d whose odes are zyhodemi and ush ne vy and second outputs expensive used, program control NGL: o8dkg; ene minutes with odazdi resolution avidly, n; rn; i ;;; o the first and second.

BLOCK IN PARITIMPSY PL.YA GI. Gyrvpl - Grove

The clock pulse shaper outputs are connected respectively to the inputs of the first and second software control blocks and the control input of the switch, the first clock input of the decoder clock pulse shaper is combined with the input of the first transdecoder software control block, and the second clock input of the driver decoder clock sequences combined with control signal generator input grancoder a is the second clock input of the device

2. The device according to claim 1, so that the driver of the transcoder control signal contains a pulse counter for NI and a pulse counter for N2 (Ni and N2 are the minimum possible integers that the condition NI fT2 N2 fn, fn fi2. tVi and Ira are the first and second clock frequencies of the device), the counting inputs of which are combined and are the input of the former, the output of the pulse counter on N2 is connected to the zero input of the counter of the pulse on Ni and is the peep output of the former, the output of the pulse counter on the ISH - the second output of the driver.

3. The device according to claim 1, that is, so that the driver of the sequence of clock pulses of the decoder contains a pulse count on Hz, the first and second pulse counters on Ni, the first and second elements And, and the synchronizer the inputs of which are information inputs of the imaging unit, the first - third outputs of the synchronizer are connected to the inputs - zeroing, respectively, the pulse counter on N2 and the first and second pulse counters on NI, the counting input of the first pulse counter on NI is combined with the first input of the second zlemeite And The first clock input of the imaging unit, counting pulses of the pulse generator on N2 and the second pulse counter on the MI are combined with the first input of the first element And are the second clock input of the imaging unit, the outputs of the second and first pulse counters on the NI are connected to the second inputs of the first and second elements, respectively And, the outputs of which are, respectively, the first and second outputs of the driver, the output of the pulse counter to the No. is the third output of the driver.

29

R

© -

thirty

-t-

AND

ig. 2

14

23

26

27

J /

Jj

J

No. / .J

figl

Claims (3)

For rmu l a b o 1. A device for matching digital streams when transmitting an Audio signal, consisting of transcoders and a decoder, a transcoder contains the first and second RAM blocks, a switch and a shaper of control signals, the decoder contains a switch and a pulse sequence generator. Due to the fact that, in order to improve the accuracy of transmission, by eliminating distortions of the transmitted • signal when matching the speeds of digital streams, the first and second program management blogs are introduced into the transcoder, the first and the second outputs of the first program control block are connected to the recording permission inputs, respectively (of the first and second blocks of random access memory, the information inputs of which are respectively combined and are the information inputs of devices ^, the first and second outputs of the second block · -. control grammars are connected to the permissions to read the corresponding veins of the first and-old RAM blocks, the outputs of which are connected respectively to the first and second information inputs of the switch, the outputs of which are transcoder outputs, the first and second inputs of the control signal generator are connected Accordingly, with the control input of the switch and the input of the second program control block, the first and second program control blocks are inserted into the decoder to the first and second operational blocks memory, the information inputs of which are respectively combined with the information inputs of the generator of a sequence of clock pulses and are the inputs of the decoder, the first and second outputs of the first block of program control are connected to the read permission inputs of the first and second blocks of RAM, respectively, whose outputs are connected respectively to the first second information inputs of the switch the outputs of which are the outputs of the device, the first and second outputs of the expensive software control unit connected to the recording permission inputs of the first and second blocks of the steratis memory, the first - the third outputs of the clock sequence generator are connected to the inputs of the first and second program control blocks and the control input of the switch, the first clock input of the decoder clock sequence generator is combined with the input of the first block program control transdecoder and is the first clock input of the device, the second clock input of the former after ovatelnosti clock decoder integrated with the input of the transcoder control signals and the second clock input of the device, 2, The device according to nJ, further that the transformer encoder control signal generator contains a pulse counter on Νι and a pulse counter on N2 (N1 and Nj are the minimum possible integers satisfying the condition N1 · f _T2 = = N2 ' fn, ίιι <ίτ2. ίτι ^and ίτ2 ^_ first and second clock frequencies of the device), counting inputs of which are combined and are the input of the pulse counter output to N2 is connected to the reset input of the pulse counter at N1 and the first output generator, the pulse counter output on Νι - second output shaper I. 3. The device according to claim 1, the other is that the decoder of the clock sequence of the decoder contains a pulse counter on N2. first and second pulse counters on N1, first and second AND elements and a synchronizer, the inputs of which are information inputs of the driver, the first and third outputs of the synchronizer are connected to the inputs · zeroing respectively the pulse counter on N2 and the first and second pulse counters on N1, the counting input the first pulse counter on Nt is combined with the first input of the second element And is the first clock input of the driver, the counting inputs of the pulse counter ma N2 and the second pulse counter on Μι are combined with the first input ne the first element And are the second clock input of the driver, the outputs of the second and first pulse counters on N1 are connected to the second inputs of the first and second elements And, the outputs of which are the first and second outputs of the driver, the output of the pulse counter on N2 is the third output of the driver, Fig 2 Fig. 3 to JU) Fig. 4