SU1695311A1 - Multichannel device for interfacing computers - Google Patents

Abstract

The invention relates to computing and can be used in computing systems for interfacing two and several digital computers with different data representations. The aim of the invention is to improve the efficiency of diagnostics of malfunctions by automating fault finding, increasing the depth of control and its resolution. The device contains firmware accumulators, current address registers, subroutine address registers, base address triggers, micro-command registers, address selector, address register, condition multiplexers, clock generators, trigger, e-OR, counters, and control register - OR, RAM blocks, data multiplexers, bus drivers, micro-command decoder, serial code register, decoder, multiplexer. 6 Il. “

Description

The device relates to computing technology and can be used in computing systems for interfacing two and several digital computers with different data representations.

The aim of the invention is to improve the efficiency of diagnostics of malfunctions by automating fault finding, increasing the depth of control and its resolution.

Figure 1 shows the functional diagram of the device; Fig. 2 is a timing diagram of a data write operation in any program accessible memory element; FIG. 3 is a timing diagram of a read operation for a given any program-accessible functional element; 4 is a timing chart for reading data from

RAM in sequential code; Figures 5 and 6 show device control algorithms.

The multi-channel device for interfacing a computer contains a second drive of microprogram 1 (a block of permanent memory), a second register 2 of the current address, a second register 3 of the address of the subroutines, a second trigger 4 of the base address, a second register of 5 micro-instructions, an address selector 6, an address register of the 7, the second multiplexer 8 conditions, the second generator 9 clock pulses, the trigger 10, the second element AND-OR 11, the counter 12 addresses, the register 13 control and management, the first element AND-OR 14, the third group 15 elements AND-OR, the second block 16 operational memory, second multiplex op data 17, the third multiplexer 18 Dang GOVERNMENTAL, the second bus driver 19. The bus 20 parallel clock

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interface (MPI), parallel data input / output highway 21, first drive 22 of firmware (permanent memory unit), first register 23 of the current address, first register 24 of the address of the subroutines, first trigger 25 of the base address, first register of 26 microinstructions, first generator 27 pulses, the fourth group of 28 elements AND-OR, the first multiplexer 29 conditions, the decoder 30 micro-commands, register

31 consecutive codes, first counter

32 addresses, the first group of 33 elements AND-OR, the first block 34 of RAM, the decoder 35, the second group of 36 elements

1 AND-OR, multiplexer 37, first bus driver, buses 39 serial channels, bus 40 output serial code, bus 41 clock signals of the serial interface, the first multiplexer 42 data.

This device allows the conversion of information and its control. At the same time, several modes can be distinguished as transformations: the transformation of parallel code into serial; converting sequential code into parallel; conversion of sequential code to sequential.

Consider the operation of the device at. as converting a parallel code into a serial one.

The device is configured to transmit a serial code by submitting to the parallel I / O lines (DIM) 21 the corresponding address in the data write operation. The data transmitted over the serial channel is presented in the data phase of the IIP. The command given from the MPI bus is executed as follows. In the address phase, an address code is transmitted, which is accompanied by an exchange signal (MBP). In this case, on the leading edge of the OBM signal, the address is recorded in the address register 7. In the data phase, the data code is formed on the same buses, and on a separate clock signal, a write signal is generated with a delay relative to the leading edge of the data (Fig. 2). After receiving the address and data, the subscriber, who receives them, generates an OTV response signal. On the leading edge of the PTS response signal, the DZP signal is picked up, and on the falling edge of this signal, the MBP data exchange signal is recorded.

According to the timing diagram (Fig. 2), the address code is fed through an open micro-command bus driver 19 to the address register 7, where it is fixed by the leading edge of the exchange rate signal received at the control input of the address register 7. The address code fixed on register 7 is converted to address selector 6 into a subroutine number code, which is fixed to register 3 of the address of the subroutines. The microcommand is formed during the analysis of the OBM signal in case of OBM 1. The analysis of the OBM signal is performed by executing microcommand words selected from the zero and first addresses of the microprogram 1 accumulator, from the zero cell of which, starting from the initial state, the microinstruction word is selected. contains the code of the current address, i.e. control transfer code for the next cell of this accumulator. This code, read from the accumulator, enters the information inputs of the register 2 of the current address, where it is recorded by the front

0 pulse front generator 9 pulses. Thus, in the next cycle, the contents of the first cell, i.e. alternate reading of information from the zero, first and second cells of the storage device until the exchange signal of the exchange rate is equal to one. From the zero cell of the accumulator 1, the microprogram reads the "Year of control of the multiplexer 8

0 conditions. This code is fixed at the corresponding register bits of 5 micro-instructions on the leading edge of the inverse pulse value from the pulse generator 9 and is fed to the control input of the multi-type 5 conditioner 8. Under the action of this code, the conditions multiplexer switches the exchange signal of the exchange rate to the information input of the trigger 4 of the base address. In this case, if the signal of the exchange rate is zero, then the trigger 4

0, the base address of its value does not change and the control code is transmitted to the second cell of firmware accumulator 1. If the signal of the exchange rate is 1, then the trigger of the base address 4 on the leading edge of the generator 9

The 5 pulses will change to a single value and control is transferred to the address of the firmware accumulator.

In the next cycle, the firmware will be read from cell 0003.

0 A microprogram word read from a cell with this address contains the code of the current address and a micro-command. This micro-command allows writing into the register 3 addresses of the subprograms of the code of the number of the sub-program,

5 corresponding to the address fixed in register 7 of the address, and fixed in register 3 of the address of the subroutines. At the same time on the register 2 of the current address, the code At 02c is fixed., The trigger 4 of the base address takes a zero value, since closed condition multiplexer 8 forms a zero potential at its output.

In the next steps of the firmware, an analysis of the DGP signal is performed.

The analysis of this signal is performed 5 in the same way as the analysis of the exchange of exchange signal described above, with the only difference that the multiplexer 8 of the conditions is configured to switch information from the second channel, while the control in the case of signal-10. The CCD 1 is transferred to the addresses of the drive 1 of the firmware.

At the address of the accumulator 1 of the firmware, a code is selected that arrives at the information input of the register 24 of the address of 15 subprograms, which corresponds to the number of the subroutine of the sequential code. On the leading edge of the pulse from the generator of 27 pulses, the code is entered into the register 24 of the addresses of the subroutines.

At the address of the SSLA, a code is selected from the accumulator 22 of the firmware and the cell goes to cell 0102b. At this address, from the microprogram accumulator 22, through the micro-command register 26, the value 25 of the address of the memory unit cell is selected through a group of 36 AND-OR elements. Data from the MPI will be posted to the data input of the RAM block 34 from the output of the bus maker 38 through a group of 33 elements 30 AND-OR. The same signal is used to select the value of the next current address of the firmware accumulator and the value for generating the CE 1 signal (crystal sampling signal) for all bits of the RAM block 35 34 in the mode of recording information from MMM. Thus, information is recorded from the MPI in the RAM block 34. Next, a transition occurs to the address 0104a from the accumulator cell, 40 liters, the value is selected, at which the Start 1 bit is written to the O register register 31 of the sequential code. A group of bits decoder 30 microinstructions forms. a control 45 write signal for writing the Start bit from the output of multiplexer 37 to the O bit de register 31 of a sequential code. The drive goes to the address OUOe, from which, at the output of the register of 26 micro-commands 50, codes are formed that correspond to reading from the bit of the RAM block 34 at its zero address 1 bit of information in the bit of the serial code register and its appearance on the bus 55 40 output serial code. Then there is a transition to the address 0110a accumulator 22 firmware. At this address, a code is selected, according to which multiplexer 37 is configured to transmit 2 bits.

information that corresponds to the removal of the CE signal with O of the RAM block size. Next, the address 0112s is transferred, at which signals from the accumulator 32 of the microprogram receive signals corresponding to the formation of the CE signal from the zero decoder for the first bit from the output 34 memory and transfer it to the output bus output serial code. Further, the procedure continues in a similar manner until two Stop bits are issued. At this, the exchange ends and the firmware drive 22 returns to its initial state. It should be noted that at the second step, the output of the accumulator 22 of the microprograms generates a signal that goes to one of the inputs of the multiplexer 8 conditions and informs the microprogram 1 thus that the reception of information from the MPI is completed and the microprogram 1 produces the signal OTV to the MPI highway. Upon receipt of the signal, the following command may appear on the MPI.

Timing diagrams of the converter from the parallel code to the serial are presented in FIG. 4.

It is possible to interface a computer that performs conversion from a serial code to a parallel one. The operation of the device is as follows. The conditions multiplexer 29 is configured to receive a clock signal over one of the channels of the serial interface. When a serial channel (Start) appears on the sync bus, the firmware accumulator proceeds to the execution of the serial code reception program in the RAM block 34. At the same time, the output of the accumulator 22 of microprograms by a group of bits forms the addresses of the cells of block 34, coming through a group of elements OR-36. After the address arrives, control signals are generated to the input of the operating memory 34 (recording signals and a signal of sampling the chip for the first digit the cell of the RAM unit 34) and the first bit of the cell of the RAM unit 34, through the group of elements AND-OR 33, the corresponding bit of the serial code is transmitted through the corresponding channel. After receiving the first bit, the address and control signals are formed again and the second bit of the information word is entered in the second bit of the memory cell. In order to transmit the parcel to the MPI, it is therefore necessary, via the serial channel, to receive a 16-bit parcel for transmission to the MPI address and

16-bit package for data transfer. After receiving the required number of bits of information, the firmware accumulator is configured to transmit information in parallel code. At the same time, control signals are generated from firmware accumulator 22, necessary for organizing work in a parallel code (MBP, DZP and DCB), which are fed to the condition inputs of condition multiplexer 8, and microprogram memory 22 begins to generate signals necessary for reading information from block 34 memory to the input of the bus driver 38. To read information from the memory block 34, it is necessary to submit the address to the input of the block 34 again, and the address is the same as the fipn receiving information on the block 34 in series m code. Then, the sampling signals are formed (on all 16 bits) simultaneously and on the read signal from the memory block, information is read out and transmitted to the parallel interface buses after the signal is sent to the control input of the bus driver 38. In the same way, data is transmitted to the parallel bus. interface with the only difference that at the output of the accumulator 22 of the microprograms, the address of the Next cell of the RAM unit 34 is generated.

This device provides the ability to convert from serial code to serial. In this case, for this conversion, you must first convert the serial code into parallel, and then parallel into serial, as described above.

The control of the operation of the multichannel control device for interfacing is carried out in several modes: control of the 16.34 memory blocks; control registers 5.26 microinstructions; control in the mode of formation of micro-commands of the accumulator 1 of microprograms.

Each of the control modes consists in registering the contents of the above components through multiplexer 18 and bus driver 19 in the computer connected to the MPI for further analysis. In this case, there are two possible modes of information transfer to a computer; directly through data multiplexer 18; through block 16 of RAM.

The control through the RAM block 16 allows you to accumulate information and then transfer it to the computer at the right time, which allows you to have a photo of the contents of drive 1 of the microprogram and also remove the trace of the firmware in real time. Algorithms of control of the accumulator of the microprogram in the mode of formation

microinstructions and in trace mode are presented in Fig.5.6.

The analysis can be performed by sequential comparison or by calculating checksums using a computer,

0 connected to MPI. The monitoring mode is specified by the monitoring and control register 13. At the same time, each of its bits performs the corresponding function of setting the monitoring and control modes of the switching of the corresponding information to be registered.

The assignment of register bits 13 for monitoring and control is as follows:

a group of bits 0–3 provides control over data multiplexer 18;

4 - bit control bits of the mode of operation of block 16, with 4 0 - recording information, with 4 g 1 - reading information; 5 - bit control sampling mode

5 of the memory block 16, with 5 O the sampling is prohibited, with 5 1 the sampling of information is allowed;

6 — address memory management of the RAM block 16, with 6 1 — resolution of the RAM block operation according to the value of the address counter 12, with 6 0 — resolution of the RAM block operation at the firmware 1 address of the microprogram;

5 7.8 — increment mode of the address code of the RAM block; with 7 1 — increment from the external signal; with 8 1 — increment from the generator 9 pulses.

The register and control register 13 is loaded from the parallel data input / output highway 21 by a microinstruction.

Reading information from the register 13 of the control and management is performed according to

5, in the first three steps of the subroutine, the exchange signal is analyzed. A signal is exchanged. In the presence of an exchange signal, the address of the subroutine record is selected (in this case, the third subroutine) into the register 3 of the subroutine and the address input of accumulator 1 the firmware is given the address. At this address, the value of the current address of the next microcommand is selected from the accumulator 1 of the microprogram and the subroutine proceeds to the analysis of the read signal of the CTD from the MPI. In this case, a code is selected from firmware accumulator 1 for analyzing the DFT reading signal on the multiplexer 8 conditions. After the DTPP signal has appeared, it goes to the address. From the accumulator 1 of the firmware, the values are selected and the response signal of the FCV to the DIM trunk is generated. The data multiplexer 18 is opened in the first channel, which corresponds to reading information from the control and monitoring register 13 via the bus driver 19. In this case, the control signal takes a value equal to zero, which corresponds to switching the bus driver to transmitting data in the MPI. After receiving the response signal from the DIM, the DFR reading signal should be cleared, which is also analyzed by the condition multiplexer. After removing the signal from the FFS, a transition occurs to analyze the MBP signal. After receiving the OBM 0 signal, the drive goes to the address and the end of operation signal is generated, according to which the drive 1 of the firmware changes to the initial state.

Using the memory block 16 through the data multiplexer 17, it is possible to monitor the drives 1 of the microprograms through the register 5 of the microprograms and the control of the address registers of the drives: register 2 of the current address, register 3 of the address of the subprograms, trigger 4 of the base address. Through the data multiplexer 18, after switching the bus drivers 19 to the information transfer mode in the DIM, counters 32.12 of the address, blocks 34 and 16 of the RAM, register 31 of serial codes, register 13 of monitoring and control can be monitored.

When using memory block 16 in the firmware trace mode, it is necessary to preset the register in software. 13 monitoring and control. When tracing microprograms from the accumulator 1 of the microprogram, the monitoring and control register 13 is configured as follows:

bits 0-3 0010 - opens the data multiplexer 17 for receiving in the block 16 an operative memory of the lower bits of the register of 26 micro-instructions;

4 0, 5 1, 6, 7 1 - setting up the memory block 16 for information recording mode.

After the described preparation, any investigated firmware is executed for the accumulator 1 of the microprogram with the addressing of the RAM block 16 from the counter 12 of the address with its subsequent updating. When implementing the program under study, at the sixth step of its execution, a microcommand is formed that sets trigger 10 to one state. This trigger by single signal allows operation of the AND-OR element 11, which commutes the flow of pulse generator from pulse generator 9 to counting input of counter 12. Thus, after triggering 12 is set to one at each step of microprogram execution, the contents of counter 12 will increase by one (increment 1), therefore, the information supplied to RAM 16 from the register outputs 5 microinstructions will be fixed in the cells of the block RAM. It should be noted that the sync pulse fixing the address of the RAM block is formed on the AND-OR element 14, which should not only perform direct fixation of the logical multiplication, but also the delay function, i.e. the delay time of the signal on this element should be longer than the delay time on the element AND-OR 15. This can be achieved by applying the element AND-OR 14 with a longer delay time than the element AND-OR 15. After the operation is completed, at the 12th step a microinstruction which sets the trigger 10 to the zero state, and the writing to the memory unit 16 is stopped.

In the RAM block, the sequence of the formation of micro-instructions from the accumulator 1 of microprograms via the register 26 of micro-instructions is fixed, which can be read out to the main 21 using a special reading command.

The implementation of the read command of the RAM block 16 is carried out similarly to that already described. This command is implemented using a read command (PAD) from the parallel I / O bus 21 to the special address reserved for this command. This address is sent in the address cycle to the address register 7, then decrypted on the address selector 6 to the address of the corresponding subroutine, in the process of realization of which a sampling pulse of the RAM and a counting pulse that increments the address of the memory 16 operation block is formed. In addition, a code Hs 01 is generated, which commits the information read from the RAM block 16 to the parallel I / O line 21. Thus, by repeatedly performing the described operation, the cells of the RAM memory block 16 will be read, starting with An + 1, where n is the number of read operations performed from the RAM memory block 16, An is the starting address recorded on the counter 12 of the address team

In addition, the monitoring and control register 13 must also be pre-configured to read information from the operational memory block 16 based on the contents of the address counter 12. The procedure for configuring the memory block 16 is described above. Obviously, if the monitoring and control register 13 is configured in a part of the group of bits controlling multiplexer 17 to another code, then a photograph (sequence) of any other sequences connected to the information inputs of the multiplexer 17 can be taken in the described manner. At the beginning of the described monitoring mode, the register 13 for controlling and controlling the bit would be set to addressing from the address component, i.e. 6 1, then, when performing the same operation, the specified information will be sequentially recorded, the sequence of registration in which memory block 16 is determined by the sequence of changes in the address part of drive 1 of the microprograms. The feasibility of implementing this control mode is determined by the need to control the contents of the accumulator 1 of the microprogram when the address of the accumulator is naturally accessed.

The trace mode on the counter 12 addresses provides a linear control of the firmware and is mainly used to monitor when setting up the device itself and when debugging the working programs of both firmware drives, providing trace of the firmware.

The control mode for the address component of the accumulator 1 of the firmware provides control of the formation of micro-commands of the accumulator 1 of the microprograms on each sample of their sample from the accumulator, as well as the sequence of the sampling during the implementation of the functional subprogram. Monitoring of the RAM unit 16 itself can be carried out by recording information in the cells of the RAM 16 and the counter 12 of the address. In this case, the monitoring and control register 13 is configured to write to the RAM 16 via the first channel of the multiplexer 17c by addressing through the address counter 12 and the address of the cell itself will be written in each cell of the RAM 16.

Claims (1)

Invention Formula A multichannel computer interface device containing the first bus driver, the first input of which is the input I / O input of the device, and the output is connected to the first group of inputs of the first group of AND-OR elements, the outputs of which are connected to the information inputs of the first RAM block, the second group of inputs of the first group of AND-OR elements are connected to the outputs of the first data multiplexer, whose inputs are the input inputs of the device serial code, the first and second inputs of the first group of AND-OR elements are connected to the first output of the first register microinstructions, the control inputs of the first memory block are connected to the outputs of the decoder, the inputs of which are connected to the first group of output i of the first register of microcommands, the address inputs of the first block The operating memory is connected to the outputs of the AND-OR elements of the second group, the outputs of the first RAM block are connected to the second input of the first bus driver, to the information inputs of the first address counter and to the information, multiplexer inputs, and the first and second information inputs of the multiplexer respectively, with buses of single and zero potentials, the control inputs of the multiplexer are connected to the second group of outputs of the first register of micro-instructions, to the inputs of the decoder of micro-instructions and to the control moves the first data multiplexer. the multiplexer outputs are connected to the information inputs of the serial code register, the outputs of which are the output outputs of the serial code of the device, and the control inputs of the serial code register are connected to the outputs of the micro-command decoder, the clock input of the first address counter is connected to the second output of the first micro-command register, the outputs of the first address counter connected to the first group of inputs of the second group of elements AND-OR, the second group of inputs of which is connected to the third group of outputs of the first reg the micro-command source, the first and second inputs of the AND-OR elements of the second group are connected respectively to the third and fourth outputs of the first register of micro-commands, the fifth output of which is connected to the control input of the first bus driver, the information inputs of the first register of micro-commands are connected to the first group of outputs of the first firmware accumulator , the second group of outputs of which is connected to the information inputs of the first register of the current address, the outputs of which are connected to the first group of address inputs of the first Ithel firmware, second group of address inputs "which is connected to the outputs of the first PE gaetra subroutine addresses significant bit of the address of the first accumulator yhoda firmware is connected to the output of the first trigger of the base address, the control inputs of the first micro-command register and the first register of the current address are connected to the outputs of the AND-OR elements of the third group, the first input of which is connected to the output of the first pulse generator and the synchronous inputs of the first subroutine address register and the first trigger the base address, the second input of the third group of AND-OR elements and the first control input of the first multiplexer of conditions are connected to the device control input, the information input of the first trigger The base address server is connected to the output of the second condition multiplexer, whose inputs are the clock inputs of the device's serial interface, the control inputs of the second condition multiplexer are connected to the fourth group of outputs of the first microinstruction register, in order to improve the efficiency of fault diagnosis by automating fault finding , increasing the depth of control and its resolution, the second bus driver, address register, selec are entered into the device the address torus, the second trigger of the base address, the second register of the current address, the third condition multiplexer, the second address register of the subroutines, the second firmware memory, the second register of microcommands, the trigger, two AND-OR elements, the control and management register, the fourth group of AND-OR elements, the second memory unit, the second pulse generator, the second and third data multiplexers, the second address counter, the output of the second data multiplexer via the second bus driver connected to the output of the information bus pairs The first input of the second data multiplexer is connected to the outputs of the first register of microcommands, the second input of the second data multiplexer is connected to the outputs of the first RAM block, the third input is with the address inputs of the first firmware accumulator, the fourth input is the input input the serial code of the device, the fifth input of the second data multiplexer is connected to the output of the first address counter, the sixth input - with the output of the second address counter, with the first group of inputs four of that group of AND-OR elements and the first input of the third data multiplexer, the seventh input - with the outputs of the second RAM block, the eighth input - with the output of the monitoring and control register, the ninth input - with the outputs of the second trigger of the base address, the second register of the address of the subroutines, the second register of the current address, with the address inputs of the second accumulator of microprograms, with the second group of inputs of the fourth group of AND-OR elements and with the second input of the third data multiplexer, the output of the second bus driver the address, the second counter of the address, the monitoring and control register and the third input of the third data multiplexer, the output of the address register is connected to the first group of inputs of the selector Dres, which outputs 5 are connected to the information inputs of the second register of subprograms, the second group of inputs of the address selector is connected to the information inputs of the second register of the current address and the first group of outputs of the second accumulator of microprograms, the second group of outputs of which is connected to information inputs of the second register of micro-commands, the first output of the second clock generator pulses 5 is connected to the synchronous inputs of the second trigger of the base address, the second register of the address of the subroutines, the second register of the current address and the first input of the first element AND-OR, the second output of the second generator 0 clock pulses are connected to the sync-clock of the second register of micro-instructions, the data input of the second trigger of the base address is connected to the output of the first condition multiplexer, whose information inputs are 5 are the sync signal inputs of the device’s parallel interface, the first information input of the first condition multiplexer is connected to the address register clock input, the control input of the first 0 condition multiplexer is connected to the sixth output of the first register of micro-instructions, the address inputs of the first multiplexer of conditions are connected to the first group of outputs of the second register of micro-instructions, the second group of outputs of which is connected to information inputs of the first register of the subprograms, the third group of outputs of the second register of micro-commands is connected to control inputs the second data multiplex; the first to the sixth outputs of the second micro-command register are connected respectively to the third input of the third group AND-OR s, setup and trigger reset inputs, second input 5 of the first AND-OR element, the synchronous input of the control register and the first input of the second AND-OR element, the first, second and third groups of outputs and the first to the sixth outputs of the second micro-command register are connected to the eighth input of the second data multiplexer, the output of the trigger is connected to the third the input of the first AND-OR element, the outputs of the control and control register, respectively, with the fourth and 1 th inputs of the first AND-OR element, with the third and fourth inputs of the fourth group of AND-OR elements, with the second and fourth inputs of the second element is the AND-OR, a first control input of the second block of RAM memory and to the control input of the second bus driver, an output of first AND-OR coupled to the input of the second counters nym address counter and the third input of the second element AND-OR, the outputs of the elements AND-OR of the fourth group are connected to the address inputs of the second RAM block, the group of outputs of the monitoring and control register is connected to the control inputs of the third data multiplexer, whose outputs are connected to the data inputs of the second RAM block ti, the second control input of which is connected to the output of the second AND-OR element, the outputs of the second data multiplexer are connected to the second inputs of the second bus driver. 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