SU1691791A1 - Simulator of voltage failures of mains - Google Patents

Abstract

The invention relates to a measurement technique and can be used to simulate transients of a network voltage when testing various radio navigation devices. The purpose of the invention is to improve the accuracy of imitation of voltage dips. P - 2 controlled valves 13.1 - 13.p - 2 are introduced into the device, output voltage selector 14 and new functional connections are formed. The device also contains a generator 1, a voltage divider 2, controlled valves 3, b, current sensor 4, null organ 5, elements 7, 8, trigger 9, shift register 10, counter 11, starting element 12, group of m elements} L 15.1-15. t, element 16 matches. 2 Il.

Description

The invention relates to measurement technology and can be used for. imitations of voltage transients in the network when testing various radio navigation devices.

The purpose of the invention is to improve the accuracy of imitation of voltage dips.

FIG. Figure 1 shows the simulator structure; in fig. 2 is a voltage chart of his work.

The mains voltage dip simulator contains a generator 1, a voltage divider 2, the first controlled valve 3, the current sensor 4, the null organ 5, the second controlled valve 6, the first 7 and the second 8 elements And, the trigger 9, the shift register 10, the counter 11 and the starting element 12. In addition, the network voltage dips simulator contains (p-2) controllable valves 13.1 - 13.-2), the first inputs of which are connected to the corresponding outputs of the divider 2, and the outputs are combined and connected to the sensor input 4 currents, selector 14 output voltages, the outputs of which are connected to the second inputs the corresponding controlled gates 13, and the first inputs are connected via a group of m elements 15.1 to 15.t, where 1 iЈm, to the information outputs of the t-bit shift register 10, the second inputs of the elements 15.1 to 15.m are combined and connected to the inverted output of trigger 9, and the third inputs are combined and connected to the output of the null organ 5. The forward output of the trigger 9 is connected to the input for selecting the operating mode of the shift register 10 and the second input of the second element And 8, and the counting input of the trigger 9 is connected to the first output of the starting element 12, the second output of which through p The first element 7 is connected to the input of the counter 11, the output of the counter 11 is connected to the first input of the coincidence element 16,

cl

with

oh oh

 Yu

the second input of which through the selector 17 time intervals connected to the information outputs of the register 10 shift. The output of the coincidence element 16 is connected to the second clock input of the shift register 10 and the second input of the first element 7, the output of the m-th digit of the shift register 10 is connected to the input of the trigger element 12.

The network voltage dip simulator operates as follows.

When operating in the absence of dips, the initial state of the first output of the starting element 12 is logical O, and the second - logical M. At the same time, the clock pulses from generator 1 pass only to the clock input of the shift register 10. The trigger 9 is in the initial state: at the direct output - the level of the logical unit, on the inverse - the logical zero. The level of the logical unit from the direct output of the trigger 9 is fed to the first input of the element 8. At the moment of transfer of the load current through 0, the current sensor 4 generates a signal that the null Organ 5 carries to the second input of the element 8 as a logical signal H1, The output of which forms a pulse that acts on the controlled valve 6, through which the nominal voltage of the network from the input of the simulator enters the output bus through the current sensor 4.

If it is necessary to simulate a flash, pressing the button affects the starting element 12 (the button is not shown in Fig. 1), Logic level 1 appears at its first output, Logic O. appears at the second output. Logical 1 signal turns on the first input of the element is And 7, the most prohibition is lifted, and at the output of the element And 7 there appear clock pulses Coming from generator 1 to the counting input of Counter 11. The logical signal O from the second output of the starter 12 acts on the trigger 9, as a result MOM trigger output 9 - a logical signal O, and on the inverse - logical. The logical 1 signal from the inverse output of trigger 9 removes the ban on all m elements 15, and the logical 0 signal from the direct output of trigger 9 bans the element 8 and also switches the shift register 10 from write mode to read mode .

As a result, a logical signal G appears at the first input of the first element And 15 and at the moment the load current passes through 0 from the current sensor 4 through the null organ B, a logical signal 1 arrives at the second input of the element 15.1, at the output of which a signal is generated which, through the output voltage selector 14, turns on a controlled valve from the n valve group 13 or valve 3, which corresponds to the specified code of the voltage value sequence. As a result, the input voltage through the voltage divider 2, this controlled valve and the current sensor 4 falls on the output bus simulator. The open state time of a given controlled valve is determined by a code that is preliminarily recorded in the selector 17 of the time intervals.

In the match element 16, a comparison is made of the code from the selector 17 of the time intervals and the code coming from

5 counter 11. If they coincide, a signal is generated to switch the shift register 10 to the next step. Then, the simulator operation algorithm is repeated.

As a result, when the load current goes over 0, this controlled valve turns off and the next one turns on. The code by which the selection of controllable gates is made is pre-recorded in the selector 14 of the output voltages.

5 The simulator operation algorithm is repeated m times, after which the end of cycle signal is generated, which returns the trigger element 12 to the initial state. Trigger 9 triggers, which locks the element AND

0 15.1 - 15.т and removes the prohibition from the AND 8 element, as a result, when the load current goes over 0, the controlled valve from the valve group 13 or valve 3 turns off and the valve 6 turns on, which connects the output bus of the simulator to the nominal mains voltage.

The time diagram of the voltage dips simulator in the case of receiving two pulses of different duration and amplitudes is shown in FIG. 2

Claims (1)

Claims The network voltage dip simulator containing a generator, serially connected input terminals, a five-way divider, the first controlled valve, a current sensor and a zero-organ, the second controlled valve, the output of which is connected to the output of the first controlled valve, the first input second controlled valve 0 is connected to the input terminal, the first and second elements are And, the trigger, and the output of the null organ is connected to the first input of the second element And, the second input of which is connected to the forward input of the trigger, output 5 of the second element I is connected to the second input of the second controlled valve, the shift register, the counter and the starting element, f f, which means that, in order to increase the simulation accuracy, (p-2) controlled valves are introduced into it, the first entrances of which connected to the corresponding outputs of the voltage divider, the outputs of controlled valves are connected to the input of the current sensor, an output voltage selector, the outputs of which are connected to the second inputs of the corresponding controlled valves, and each of the first inputs of the output voltage selector connected to the information output of the t-bit shift register, the second inputs of all elements in the group of elements I are combined and connected to the inverse output of the trigger, the third inputs of all elements in the group of elements And are combined and connected with the output of the null organ, the direct output of the trigger 0 connected to the output of the shift register operating mode selection and the second input of the second element I, the counting trigger input is connected to the first output of the trigger element whose second output is connected to the first input of the first element AND whose output is connected to the counter input, the output of the counter is connected to the first input of the coincidence element the second input of which is connected via a time selector with informational outputs of the shift register, the output of the coincidence element is connected with the second input of the shift register and the second input of the first element And that, the output of the last discharge shift register connected to the input of the trigger. figure 1