SU1683022A1 - The unit interface a computer with groups of peripherals running at different speeds - Google Patents

Abstract

The invention relates to devices of computer technology and automation and can be used to create various systems of automated control and automatic control. The aim of the invention is to increase the speed by eliminating the dependence of the speed of the device on the type of control computer and expanding the field of application of the device due to the emergence of the ability of the computer to interface with various external devices. The device contains switching units, computer communication units, communication units with an external device, 9 Il.

Description

The invention relates to devices of computer technology and automation and can be used to create various systems of automated control and automatic control,

The aim of the invention is to increase speed by eliminating the dependence of the speed of the device on the type of control computer and expanding the field of application of the device due to the emergence of the ability of the computer to interface with external devices that have exchange rates both above and below the speed of the computer, i.e. . with different speed external devices.

FIG. 1 shows a block diagram of the device; in fig. 2 is a block diagram of a computer communication unit; Fig, 3 is a block diagram of the switching unit; in fig. 4 is a block diagram of a communication unit with an external device (IU); in fig. 5-7 - timing charts of the device, in FIG. 8 shows an example of connecting the device's interface nodes with external devices; FIG. 9 shows a table of signals from a communication unit with a slave unit. FIG. 1 designates the channels - U interface, switching unit 2, computer communication unit 3, WU communication unit 4, computer exchange line 5, Input signal line 6, Output signal line 7, CHA signal line 8, SIP signal line 9 , group of lines 10 signals Address, group of lines 11 signals Data 1, lines 12 signals Ready, group of lines 13 signals Data 2, lines

14 signal Requirement of VU exchange, line

15 signal WU operation mode, signal line 16 WU signal exchange gate, signal line 17 End of WU exchange, group of lines 18 signals WU data, signal line 19 Allow computer exchange, 20 signal line Transfer 1, signal line 21 Transfer 2, signal line 22 Enable WU exchange resolution, signal line 23 Permission of transmission of a VU / ZU, group of lines 24 signals Selection of a charger, group of lines 25 signals Address from a computer, group of lines 26 signals Address from a VU, group of lines 27 signals Selection of a communication unit with VU, line 28 of a signal Computer exchange gate, signal line 29 Sample, signal line 30 Requirement of computer exchange, line 31 of the signal Filling from the computer, line 32 of the signal Filling from the slave, line 33 of the signal Operating mode of the computer, line 34 of the signal Resolution of the transmission of a computer / charger. FIGS. 2 denote the second and third channel receivers 35 and 36, the first group 37 channel receivers, the fourth and fifth channel receivers 38 and 39, the second group 40 channel receivers, the second bus driver 41, the second and third elements And 42 and 43, the first comparison element 44, the second and third triggers 45 and 46, the control register 47, the fourth element AND 48, the delay element 49, the first element OR 50, the first trigger 51, the decoder 52, the pulse generator 53, the second counter 54, the first counter 55, the first channel receiver 56, fifth element And 57, seventh element And 58 , first element AND 59, elements OR 60 and 61, first bus driver 62, sixth element AND 63, fifth element OR 64, second element 65 comparison, third counter 66, AND-NE element 67, first, third and second ring registers 68 - 70, the fourth element OR 71, the group of elements And 72. the group of address inputs 73. In FIG. 3 marked the fourth trigger 74, the first element is NOT 75, the fourth and second elements are OR 76 and 77, the second and third elements are HE 78 and 79, the first and second triggers are 80 and 81, the fourth, first, second and third elements are AND 82 - 85, the first element OR 86, the second and first counters 87 and 88, the fifth, third, sixth and seventh elements OR 88 - 92, the fourth and fifth elements NOT 93 and 94, the eighth and ninth elements OR 95 and 96 and the third trigger 97 FIG. 4 shows the switch 98 addresses, a group of elements And

99, first element EXCLUSIVE OR

100, the first and second elements are NOT 101 and 102, the first and second elements are AND 103 and 104, a group of elements OR 105, an element OR-NOT 106, a storage device 107, the second and first groups 108 and 109 of data switches, the second element EXCLUSIVE OR 110 FIG. 5 are designated: A1 - the time diagram of signals in a cycle Output on lines x 10, 11 and 13 (10 - Address, 11 and 13 - Data); A2 is a timing diagram of a signal on line 8 (CIA); A3 - on line 7 (Conclusion); A4 - on line 9 (CIP).

FIG. b marked: B1 - time diagram of signals in the cycle Input on lines x 10, 11, 13 and 12 (10- Address, 11 and 13- Data, 12 - Bit data, for example, 15th bit); B2 - the timing diagram of the signal on line 8 (CIA); VZ - on line 6 (Enter); B4-on-line 9 (CIP),

FIG. 7 are designated: C1 - the timing diagram for counting the number of blocks filled with charger by the counter 87; C2 is a timing diagram for counting the number of blocks 4 filled with charger by counter 88; Sz - timing diagram of the signal on line 30; C4 - on line 23; C5 - on line 22; C6 - on line 7; C7 - on line 20; C8 - on line 8 of register yes 47 (End of Exchange); C9 - on line 14; CU - on line 34; C11 - on line 19;

C12-on line 16; C13-on line 17; C14- on line 21; C15 - on line 15; C16 - on line 33;

FIG. 8 designates a group of 111 logic elements, an AND-HE element 112, a channel transmitter 113, And 114 and 115 elements, an Address / data bus 116, Zi - a set of matching resistors (ZH 250 Ohms), 2z - the same (ZH 120 Ohms).

The operation of the device will be considered on the example of its use for interfacing an Electronika-BO computer with L groups of M external devices.

Information word size

Computer (bus 13) 16 bits. The maximum number of groups (L) is 17 (determined by the load capacity of the computer). The number of external devices in group (M) is 16 (determined by the size of the used ring shift registers and counters).

The volume of the memory is 1024 words x16 (4 chips of type 541 RU2). The amount of memory in the communication unit with the VU (K) 16. The information word of the VU (bus 18) is 256 bits.

Control signal on line 14 from the slave

formed as a result of adding the readiness signals from the slave to I, i.e. exchange of knowledge only when all units are ready for operation. A signal on lines 16 and 17 is formed at

the result of combining the exchange gate signals from each IU with respect to I (i.e., the control units are gates from the fastest VU). Signal line 15 is connected to all slaves.

To the inputs of the channel receivers37-39

Thirteen and two bits of the address are received, respectively, to the inputs of the channel receivers 40-16 data bits.

The output 9 of the bus driver 62 is connected to the CIP (passive device response signal) circuit of the computer interface. The input 6 of the channel receiver 56 is connected to the Input circuit of the computer interface, the input 7 of the channel receiver 35 is connected to the circuit Output of the computer interface, the input 8 of the channel receiver 36 to the SIL circuit.

Output 12 is connected to the bit (for example, 15) in line 13. In the device, bus drivers and channel transmitters can be implemented on the basis of K 559 IP1, K585 AP16, K 585 AP26, or similar microcircuits. Channel receivers can be implemented on-chip type K 559 IP2 or similar. A node consisting of a counter 54, a reference element 65, and an NE-NE element 67 can be implemented on a K 155 EEH or IC chip.

The inputs of the D-flip-flops 80 and 81 are connected to the circuit Gen. The switches 98, 108 and 109 of the address and data are implemented on sixteen elements of NAND, which corresponds to the size of the counters 54 and 55 and the memory 107.

The device operates in the following modes: entering information from a computer to a charger, outputting information from the charger to an slave unit, entering information from the slave unit to the charger, outputting information from the charger to the computer.

At the initial moment, the counters 54, 55, 87, and 88 and the flip-flops 80, 81, 97, and 74 are installed in the zero state, the first outputs are set to one, and all other outputs of the ring registers 68 to 70 are in the zero state. installation not shown). In this case, the potentials in accordance with C1 - C16 (Fig. 7) and D1 (Fig. 9) are set at the outputs of the device. The priority of entering information into the memory from a computer or a VU is arbitrary, but when pulses are simultaneously applied to lines 14 and 30, the priority of the beginning of the exchange remains behind the computer, since the triggers 80 and 81, indicating the direction of the exchange, cannot simultaneously be found in a single state. When a flip-flop 80 is set to one, the pulses of exchanging the line 14 to the flip-flop 81 are prohibited to pass, and a zero potential is applied to the zero input of the flip-flop 81, resetting the flip-flop 81 to the zero state.

Entering information into the memory of the computer.

The input of information into the memory occurs when the programmatic access of the computer to the device registers in the cycles of Input and Output,

Device registers: РКСвв write control code to register 47. РКСвв-read readiness bit at the output of the And 48 element, PD - write information to the memory 107i - 107 and read information from the memory 107i - 107К.

The control code recorded in register 47. has the following format. (1 5) -th bit is the frequency code (used to set the exchange frequency with the slave. In the case of

they have no sync pulse shaping nodes); 6th bit is the control mode (1 is control from a computer, 0 is control from a control unit); The 7th bit is the exchange requirement, the 8th bit is the end of the exchange. Active high

0 signal level. Address part of the cycle.

In accordance with the time sequence of signals of the computer interface at the beginning of the cycle, forms on the lines of the address highway 10 the address of one of the registers

5 channel 1 of the interface with which information is to be exchanged. Older bits of the address through the first group of channel Z7 receivers arrive at the first group of inputs of element 44

0 To the second group of inputs 73 of the comparison element 44, the node address code is not (group code). If the code of the corpse coincides with the signals of the higher bits of the interface address at the output of element 44,

5, no logical unit signal is generated that arrives at the D-input of the D-flip-flop 51. After issuing the address, the computer generates an SIA signal, which is fed through the channel receiver 36 to the write input C of the transceiver 51

0 setting it to one. The SIA signal also sets the triggers 45 and 46 to a state determined by the low-order address bits coming through the channel receivers 38

5 and 39 to the D inputs of 45 m trigger 46. The low-order code identifies the selected register. The signals from the ipnrrepos outputs are fed to the inputs of the decoder 52. Which is selected by a low level signal with

0 reverse trigger output 51. A single signal from the output of the decoder 52 arriving at the input of the control register 47 and allowing it to work. After the task of the SIA computer signal, the address is removed and the signals are generated. The data is received through a group of 40 cabling receivers at the inputs of the register 47 and representing the code of controls with the exchange requirements set in the 7th bit (Fig, 5. Ai, A2),

0 After this, the computer generates a signal Output on line 7 of FIG. about. A3}, On the back of the signal, the progress of the controls of the zapksyazet- to the register 47 and on line 30 a high level signal appears. At the same time, the high-level signal from the output of the AND 43 element enters the input element © OR 50 and generates a high-level signal at its output. From the output of the element OR 50, the high level comes from the first exit of the bus driver 62 and through the zgmep-, 49 supply to its second input. As a result, at the output 9 of the bus driver 62, through the time Determined by the delay element 49, a low level signal r (CIP) is generated, which is analyzed by the computer and perceived as the result of the completion of the operation Output. When a CIP signal is received from a computer device, it removes a signal. Output-l removes data. The device removes the SIP signal, completing the operation of receiving data (Fig, 5, A4). The computer removes the STR signal, completing the channel cycle Output,

The high level signal from the output of the 7th digit of the register 47 through 30 30 goes to the input of the element HE 75 and from its output goes low through the element OR 76 to the S input of the riggers 80 and 74 and sets the MV to one. When signals on lines 23, 22 and 33 appear, the following signals appear: on line 23 - a low level, allowing the transfer of information through data switches 108 in the direction from 3V to VU; on line 22 - low level, prohibits the passage of gating pulses from the VU; on line 33 - high level, determines the readiness of the device for operating a computer with a memory device (when reading a computer, РКСвв device).

The computer in the Eddy cycle accesses the RCS, while the output of the decoder 52 is a high level, which goes to the choices of the And 48 element and allows the ready bit to be transmitted on line 33 to line 12 when the Input signal comes to line b (Fig. 6, B1-B4). The computer, having made sure that the device is ready for operation in the address cycle, accesses the PD, and at one of the outputs of the decoder 52 a single signal appears, which enters the input of the And 59 element and together with the high level signals on lines 19 and 20 permits passing pulses output. Impulse The output at input 7, the minimum duration of which is equal to the data writing cycle in memory 107, gates the input data via bus 13 (FIG. 6, B1, OT).

During a pulse output at the output 28 at the output of a group of elements AND 99 and OR 105, a single signal is formed that selects memory 107i and allows the data switch 109i to operate at the transmission direction from bus 13 to memory, as single signals occur at the first outputs of registers 68 and 70 and on line 34, on line 23 is low, therefore, at the output of the element OR-NOT 106, a low signal level is formed and the first word is recorded in the memory 107i of block 4i at the zero address specified by counter 55 (Fig. 9. D2) . The falling edge of the signal

The output 28 strobe the input data is set to the second state of the second bit and to the zero state of the first bit of the register 68, therefore during the input of the next data word (the next memory access cycle) a single signal is formed at the second output of the group of elements And 99 and OR 105 and the next word is recorded in

The memory 1072 through the switch 1092 of the block 4i is also at the zero address. After recording the first K words of the entered data in all the memory 107i - 107K of the first block 4i with the falling edge of the signal from the K-th output of the ring register 68

the counter 55 increases its content by one, therefore, the following K input words are recorded sequentially in the memory 107i - 107k of block 4i at the first address specified by the counter 55., etc.

Each arrival of a signal. The output at input 7 is accompanied by the formation of a CIP signal at output 9 through At, which is determined by delay element 49. The duration of the delay is chosen greater or

equal to the propagation time from the output of the channel receiver 56 to the output of the element OR 105 of the group. After finishing the input of the data array with a length less than the capacity of the memory of the 4i block of the computer, it registers to the control register 47 and writes down the bit of the end of the exchange in the 8th bit bit d-O, and in the 6th bit d-bit of the speed control (in case of an increase in the exchange rate), the positive signal from the 8th bit

initializes the register 68 and the counter 55, the second bit into the single state and the first bit of the register 70 into the zero state; therefore, writing the next data array is performed by the communication unit 42 with the VU 107i at the zero address. At the same time, the signal from the output 31 increases the content of the counter 87 by one unit, which leads to the formation of a single signal

at the output of the element OR 89 on lines 22 and 15 and to the destruction of the output of information from the communication unit 41 with the control unit (Fig. 7, C1, N3, C5, C8, C15 for t ti).

If the length of the input array is greater than the capacity of the storage unit 1071-107K of block 4i, then at the moment of overflow of the capacity of the counter 55, a single signal is generated at the output of the overflow, which shifts the single signal in the ring register 70, increases the contents of the counter 87, and thus entering the data array continues in unit 42 of communication with the VU in the storage unit 107i at the zero address (Fig. 7, C1 for t 12), and at the outputs 22 and 15 there are single signals allowing the VU to exchange information with the device (Fig. 7, C5, C15).

To avoid double operation of the ring register 70 and counter 87, when entering arrays with a length equal to the storage capacity of one communication unit 4 to the control unit, the second input of the And 57 element is blocked with a zero signal from the output of the OR 60 element. If all the memory 107i - 107 blocks 4i - If the 4M communication with the VU is filled with information, then at the output 20 of the overflow of the counter 87, a zero signal is generated, which closes the AND 59 element and prohibits further information input until the memory 107 of the 4i-4M communication with the VU is released (Fig. 7 , C1, C7 at t ts).

When a single signal from the output of 6 bits of the register 47 arrives at the input of the element NE-NE 67, pulses with a frequency specified by a computer appear at the output of this element, which are used in the absence of sync pulses from the VU or during operation of the VU at frequencies greater than the cycle frequency control computer exchange.

Information output from the memory in the VU.

Information output from the storage device 107 on line 18i - 18M VU is possible only after filling at least one communication unit 4 with VU with the data array of the storage device 107t - 107K. In this case, a single signal is generated at the output of the overflow of the counter 55, which shifts the single signal in the ring register 70, increases the contents of the counter 87, and at the output of the OR 89 element and on the lines 22 and 15 there appear single signals allowing the exchange between the slaves and charger (Fig. 7, C1, C15 at t t2).

Information output from memory 107 is performed by P-bit words, moreover, R R K, where R is the word width entered in the memory; K - the number of memory 107,

WU, having received a single work enable signal via line 15, generates on line 16 signals strobe the input data with a minimum duration equal to the read cycle from memory 107. During a single signal, one of the inputs of the And 63 element at the output of the And 63 also is a single signal, since the inputs 21 and 22 have high level signals. During the action of a single signal at the output of the AND 63 element, a single signal appears at the first output of the group of elements AND 72, since at the first output of the ring register there was a single signal after the initial setup.

A single signal at the output 29i leads to the formation of single signals

at all outputs of the group of elements OR 105 of the block 4i of communication with the VU, at the outputs of the crystal chip of the switches 108i are 108m data and at the inputs of the mode of all the memory 107i 107k (at the output of the element OR NOT HE 106), therefore, the data output from the memory 107i - 107K at the zero address specified by the counter 66, through the switches 108i - 108y arrive on the bus 18. The falling edge of the unit

0 of the output signal from AND 63, the output address counter 66 increases its content by one, therefore during the operation of the next single signal at input 16 of the device, data is outputted simultaneously from memory 107i - 107 of block 4i at the following address specified by counter 66 (FIG. 7, C2, C12 t t2 and FIG. 9, D3).

When outputting an array of information in length, the larger capacity of the memory block 4i, to the output

0 and overflow of the counter 66 and on the line 292, a high level signal is generated allowing the output of information from the memory unit 42 (when the ring register 69 is shifted). To eliminate false positives

5 blocking the input of the element AND 58 by a zero signal from the output of the element OR 71 was introduced. If, after reading an array of information, the filled memory 107, i.e. counter 87 is set to zero

0 a state and at the output of the element OR 89 there appears a cool signal, under the action of which the trigger 80 goes into the zero state (Fig. 7, C2, C4, C15 for t-14). At output 15, a low level signal appears and the further output of information from the memory device will be stopped. In this case, the leading edge of the low level signal on line 22 sets the register 70 to the initial state, i.e. prepares it for withdrawal

0 information from the memory.

Enter the information of the memory from the VU. The input of information from the memory to the memory occurs after the output of the previously recorded information; when resetting the counter 87

5 and if there is a negative potential on line 15. WU exposes on line 14 a negative level & signal shade. In this case, the trigger 81 goes into one state and on lines 34 and 19 appears zero

0 signal (Fig. 7, C9, CU. C11 for t -1, Fig. 9, D4) These signals set the recording mode s of the memory of block 4 and prohibit the passage of pulses to the output 28. Trigger 97 is set to one, and

5, at output 15, a single signal appears determining the operation of the TD.

WU, after analyzing the signal on line 15, exposes to the bus 18 information and to line 16 gating pulses (as 4 as gating pulses are added along

And, the resulting frequency is determined by the speed of the most high-speed slave, in the absence of synchronization pulses from the slave, a positive potential is placed on line 16 and the gating is performed by pulses from a controlled frequency divider).

During the action of a single signal at the input of the element And 63, a single signal appears at its output, which leads to the formation of a single signal at the output of 29h. A single signal at output 29i leads to the formation of single signals at the sun, the outputs of a group of elements OR 105 of communication with the slave and at the inputs of a sample of kgggalls of data switches 108i - 108y data. The output of the element OR-NOT 106 results in a low level signal, the coir determines the recording mode From the charger (Fig. 9. D4), therefore, the data located on the J8 bus is accessed through the switches 108 and the charger inputs are recorded at the zero address specified by the counter 66. The rear single signal from the output of the And 63 element counter 66 increases its content per unit, so in time of action of the next single signal at input 16 of the device The data input is performed simultaneously in see memory 1071-107k of block 4i at the following address given by counter 66 (Fig. 7, C2, C12 with t = n, ts). At the moment of termination of the information array, a single signal arrives at the device input 17 (Fig. 7, C13 for t tg), while information is shifted in the ring register 69, and a pulse appears on the circuit 32, under the action of which the counter 88 increases its content per unit.

When a data array with a length greater than the storage capacity 107i-107K of block 4i is input, a single signal appears at the overflow output of the counter.66, under the action of which information is shifted in the register 69, and at the outputs 29g, 19 and 33 a high level signal appears allowing the entry of information into the memory unit 42 and reading it (Fig. 7, C11, C16) of the computer.

When all the storage units 107i-107k are filled with blocks 4i-4M, a low level signal appears on the overflow output of the counter 88 and on line 21 (Fig. 7, C2, C14 for t no), under the action of which on line 15 low level, prohibiting the work of the slave.

Information output from the memory in the computer.

Information output from the device memory 107 to the bus 13 of the computer is possible only after filling at least one communication unit 4 with the slave with the data array of the memory 107i-107K. Wherein

at the output of the overflow of the counter 66, a single signal is generated, which shifts the single signal in the ring register 69, increases along the circuit

32, the contents (zero) of the counter 88, and at the output of the element OR 91 and on the lines 19 and 33, there are single signals allowing the exchange between the slave and the computer (fmg. 7, C2, C11. C16 for | 1h).

0 A single signal on line 33 is fed to the input of the element And 48, together with a ready-cut device for exchange with a computer,

The computer in the address cycle refers to the PKC output and in the Input cycle reads the big

5 readiness in the 15th category of data. The computer then, in the address cycle, accesses the PD and, in the Input cycle, reads the data on bus 13. In this case, the reading strobe (Input signal) enters via line 7 through AND 43 and OR 50

0 to the input element AND 59.

During the pulse input at the output 8, at the output of a group of elements AND 99 and OR 105, a single signal is formed, which selects the memory 107i and allows the data switch 109i to operate at the transmission direction from the memory to the pin 13, since the single signals occur on the first outputs registers 68 and 70 and on line 23, and on line 34 a low signal level, therefore, a high signal level is formed at the output of an IL AND NES 106 element, and the first word is read from the memory 107t of the 4U communication unit with the VU at the zero address specified by counter 55 (Fig. 7, C1, Fig.

5 9, D5). The trailing edge of the input signal on line 28 is the setting of the second state in the single state and in the zero state of the first state of the register 68, so the next time the PD is accessed

0, a single signal is generated at the second output of the group of elements AND 99 and OR 105 and the next word is read from memory 1072 through the switch 1092 of block 4i also at the zero address.

5 After reading the first K words from all the memory 107i - 107K of block 4i with the falling edge of the signal from the K-th output of the ring register 68, the counter 55 increases its contents by one, therefore reading the following K words

0 is performed sequentially from the memory 107i-107k of block 4 at the first address specified by the counter 55, and so on.

If the length of the readable array is greater than the capacity of the storage unit 107i - 107K of the block 4i, then at the moment

5, the overflow counter 55 generates a single signal at its overflow output, which shifts the single signal in the ring register 70, reduces the contents of the counter 88, and thereby reads the data array from the memory 107 of the communication unit 42 to the slave at the zero address. In this case, a single signal appears at the output 21 of the transfer of counter 88 (if there was a zero signal as a result of filling the memory of all blocks 4i - 4M, Fig. 7, C1, C14).

When reading the memory of the last filled 4M block, the counter 88 is nullified and at the output of the OR 91 element and on line 19 a low signal level appears, under the action of which the trigger 81 goes to the zero state, register 69 goes to the initial state, on line 34 A single signal appears, which returns the signal on line 19 to the single state (Fig. 7, C1, CU, C11 at t tio or t tia). In this case, a low-level signal appears on line 33, which notifies the computer (while reading the RCS) that the data output from the charger is complete. The computer, having made sure that the exchange with the first group of controllers is finished, addresses in the address cycle to the interface 12 of the next group and similarly organizes the exchange of information with the control unit of this group. When recording and reading information from the memory by external computer devices for the purpose of elimination, it can simply turn to the following channels. mates, i.e. organize a serial exchange with groups of WUs with a program interrogation of their readiness flags (РКСвв) and with installation for them in РКСв if necessary, of known speed coefficients.

Claims (1)

The invention device for interfacing a computer with multi-speed groups of external devices, comprising a switching unit, a communication unit with a computer and M communication units with an external device, each of which contains a switch, and the switching unit contains two elements NOT with a computer contains a reference element, two bus formers, the first trigger, two groups of channel receivers, a register, a descrambler, three channel receivers, an AND-NOT element and a delay element, the first, second and third control inputs of the computer communication unit are with the device inputs for connecting to the input, output and synchronization of the computer, respectively, the first output of the computer communication unit is the output of the device for connecting to the computer synchronization input, the second output of the computer communication unit is connected to the first input of the switching unit, the address input group and the data of the computer communication unit form the device input groups; for connecting to the address buses and computer data, the input-output groups M of the communication blocks with the external device form the device input-output groups for connecting to the information group of the corresponding external devices, the first corpse of the outputs of the communication unit with the computer is connected to a group of inputs for selecting the memory of communication units with an external device, the second group of outputs for a computer communication unit connected to the first inputs of a sample of M communication units with an external device; the inputs of the first, second and third channel receivers are respectively the first, second and third the control inputs of the computer communication unit, the inputs of the channel receivers of the first and second groups form, respectively, the group of inputs of the address and data of the computer communication unit, the outputs of the first and second bus drivers are respectively the first and third outputs g Fig1 communication with a computer, the first latch clock terminal 0 is connected to the output of the third j receiver, the outputs of the channel receivers of the first group are connected to the first group of inputs of the comparison element, the output of which is connected to the information input of the first trigger, the second group of inputs of the comparison element forms the group of inputs for specifying the device address, it is different that, in order to improve speed and expand the area of application, L-1 switching units, L-1 communication units with a computer and M (L-1) communication units with an external device, are introduced into it, forming L interface channels groupism from M external devices, and in each of the L blocks Five switching units introduced nine OR elements, four triggers, four K elements, three NOT elements and two counters, and seven AND elements and five OR elements were entered into each of the L communication units with a computer. two 0 flip-flops, two channel receivers, three counters, a pulse generator, three ring registers, a reference element and a group of elements, And, -l each of the M-L communication units with an external device is entered 5 group of elements 11, two elements NOT, two elements EXCLUSIVE OR, group of elements OR, s; zyment OR NOT, two elements AND, K of P-bit storage nodes, two groups of MS N data switches, 0 and the first, second and third control inputs of the computer communication unit of each of the L-1 interface channels are inputs of the device for connecting computer input, output, and synchronization to the computer, respectively, the first output of the computer communication unit of each of L The -1 channel of the interface is the output of the device for connecting to the synchronization input of a computer,. each of the L-1 interface channels, the second output of the communication unit with the computer is connected to the first input switching unit, address input groups and data of communication unit with computer each of L-1 interface channels form device input groups for connecting address and data of computer in each of L-1 interface channels, input-output groups M st blocks with an external device form input-output groups for connecting the corresponding external device to the input-output, the first group of outputs of the computer communication unit is connected to the input selection group of the memory of communication units with an external device, the second group of computer outputs is connected to the computer The inputs of the M blocks of communication with an external device, and in the computer block each of the L-1 interface channels, the inputs of the first, second, and third receivers are respectively the first, second, and third control inputs of the communication unit With a computer, the channel detectors of the first and second groups form, respectively, a group of inputs of the address and data of a communication unit with a computer, the outputs of the first and second bus drivers are respectively the first and third outputs of the communication unit with a computer, the synchronous input of the first trigger is connected to the output of the third channel receiver, the outputs of the channel receivers of the first group are connected to the first group of inputs of the comparison element, the output of which is connected to the information input of the first trigger; the second group of inputs of the comparison element forms a group of inputs for specifying the address and the interface channel, and in each interface channel the second input the switching unit is the input of the device exchange requirements, the first output of the switching unit is the corresponding output of the device mode, the fourth control input of the communication unit with the EV M is the corresponding input of the Strobe device exchange, the output of the readout of the computer communication block is the corresponding output of the readiness of the device, the fifth control input of the communication unit with the computer is the corresponding input of the readiness of the device, the output is filled from the memory of the communication unit with the computer with the third input of the switching unit, the second output of which is connected to the control input of the communication unit with a computer, the seventh control input of which is connected to the third output of the switching unit, the fourth output of which is connected to the eighth control the input of the computer communication unit, the ninth control input of which is connected to the fifth output of the switching unit, the sixth output of which is connected to the tenth control input of the communication unit with the computer, the seventh output the switching unit is connected to the transmission enable inputs of M communication units with an external device, the output of communication unit exchange requirements with a computer is connected to the fourth the input of the switching unit, the third group of outputs of the communication unit with a computer is connected to the first groups of address inputs of communication units with an external device, the second groups of address inputs of which are connected to 0 by the fourth group of outputs of the communication unit with a computer, the fourth output of which is connected to the inputs of the exchange gate of communication units with an external device, the second inputs of which are connected to the outputs of the fifth The 5 groups of a computer communication unit, the second groups of input / output data of communication units with an external device are a group of input / output devices for connecting to a computer data bus, and in the unit 0 communication with the computer of each of the L channels of the interface, the output of the first element OR is connected to the first input of the first bus driver, to the first input of the first element AND, and to the input of the delay element, output 5 of which is connected to the second input of the first bus driver, the outputs of the first and second channel receivers are connected respectively to the first inputs of the second and third elements And, the second inputs of which are connected to the direct output of the first trigger, the inverse output of which is connected to the input of the decoder sample, the first and the second inputs of which are connected to the outputs of the second and third triggers, the synchronization inputs of which are connected to the output of the third channel receiver, the information inputs of the second and third triggers are connected Nena respectively to the outputs of the fourth and fifth channel pri0 emnikov whose inputs are connected with the first group of address input unit communication link with a computer, an output of second AND gate connected to the first input of the first AND element IL, and to a first input of the fourth AND element, 5 whose output is connected to the input of the second bus driver, the output of the third element I is connected to the second input of the first element OR and to the synchronization input of the control register, information 0 whose inputs are connected to the outputs of the channel receivers of the second group, the input of the control register sample is connected to the first output of the decoder, the second output of which is connected to the second input of the even element And the third input of which is the tenth control input of the communication unit with the computer, the first the output of the control register is connected to the inputs of the initial installation of the first ring shift register and the first counter and to the first input of the fifth AND element, the second input of which is connected to the output of the second OR element, whose inputs are connected The outputs of the first counter are the third group of outputs of the computer communication unit, the third output of the decoder is connected to the second input of the first element I, the third and fourth inputs of which are the sixth and seventh control inputs of the computer communication unit, the fourth output which is connected to the output of the first element And and is connected to the input of the shift of the first ring register, the outputs of which are the first group of outputs of the communication unit with a computer, the output of the senior bit of the first ring register is connected to the counting input ne The first counter whose transfer output is connected to the first input of the third element OR, the second input of which is connected to the output of the fifth element AND, the output of the third element OR is the second output of the communication unit to the computer and connected to the shift input of the second ring register, the initial setting which is connected to the first input of the sixth And element, the outputs of the second ring register are the second group of outputs of the computer communication unit, the fourth control input of which is connected to the second input of the sixth And element, the third input of which Connected with the output of the element IS-NOT, the first input of which is connected to the second output of the control register, the third output of which is the fifth output of the communication unit with a computer, the group of outputs of the control register is connected to the first group of inputs of the second comparison element, the second group of inputs of which is connected with the group of outputs of the second counter, the counting input of which is connected to the output of the pulse generator, the reset input of the second counter is connected to the output of the second comparison element and the second input of the NAND element, the fourth and first inputs of the pole The first element And are respectively the eighth and ninth control inputs of the communication unit with a computer, the output of the sixth element And is connected to the first inputs of the elements And group and with the counting input of the third counter, the reset input of which is the fifth control input of the communication unit computer and connected to the first input of the seventh element AND, the second input of which is connected to the output of the fourth element OR, whose inputs are connected to the outputs of the third counter and are the fourth group of outputs of the communication unit with a computer, the transfer output of the third counter with the first input of the fifth element OR, the second input of which is connected to the output of the seventh element AND, the output of the fifth element OR is the sixth output of the computer communication unit and is connected to the shift input of the ring register, the initial installation input of which is connected to the sixth control unit the input of the computer communication unit, the outputs of the third ring register are connected to the second inputs of the elements AND groups, the outputs of which are the fifth group of outputs of the communication unit with the computer, each to the switching unit, the first input is connected to the first inputs of the first and second elements AND, the output of which is connected to the subtracting input of the first counter, the summing input of which is connected to the output of the third element AND, the first input of which is the third input of the switching unit and the first input of the fourth And, the second input of which is connected to the second input of the first element AND, with the first inputs of the first and second elements IL IL-with the direct output of the first trigger, the inverse output of which is the seventh output of the co mmutation connected to the first input of the third the OR element and with the reset input of the second trigger, the direct output of which is connected to the second input of the second element AND, the first input of the third element AND, and the first input of the fourth element OR, the second the input of which is connected to the output of the first element NOT, the output of the fourth element OR is connected to the installation input of the first trigger, the synchronization input of which is connected to the output of the second element NOT, the input of which is connected to the third input of the fourth element OR. with the output of the fifth OR element and with the second input of the third OR element, the output of which is the fifth output of the switching unit, the fourth the output of which is connected to the output of the trans; The second counter, the outputs of which are connected to the inputs of the sixth OR element, the subtracting and summing inputs of the second counter are connected to the outputs of the fourth and first AND elements, respectively, the second input of the switching unit is connected to the second input of the second OR element, the output of which is connected to the second trigger input, the inverse output of which is connected to the second input of the first element OR, the output of which is the eighth output of the switching unit and connected to the first input of the seventh OR element, the second input of which dinene with the output of the sixth OR element, with the third input of the second OR element and with the input of the third element NOT, the output of which is connected to the synchronization input of the second trigger, the inputs of the fifth OR element are connected to the outputs of the second counter, the transfer output of which is the third output of the switching unit, the first and second outputs of which are connected to the outputs of, respectively, 5 of the third trigger and the seventh element OR, the input of the first element is NOT the fourth input of the switching unit, the inverse output of the third trigger is connected to its information input, the synchronization input 10 of the third trigger is connected to the output of the eighth element OR, the first input of which is connected to the output of the third OR element, the second input of the eighth element OR is connected to the output of the fourth 15 element NOT, the input of which is connected to the transfer output of the first counter, the installation input of the third the trigger is connected to the output of the second element OR, the direct output of the fourth trigger is the sixth 20 output of the switching unit, the transfer output of the second counter is connected to the input of the fifth element NOT, the output of the cat is connected to the first input of the ninth OR element, the output of which is connected to the synchronization input of the fourth trigger, whose information input is connected to its inverse output, the installation input of the fourth trigger is connected to the output of the fourth OR element, the second input 30 of the ninth OR element is connected with the output of the seventh element OR, and in each communication unit with an external device, the first sample input is connected to the first control input of the address switch and 35 is connected to the first inputs of the AND elements of the group, the first input is first The EXCLUSIVE OR element is the first input of the transmission permission of the block sv-cm to an external device and is connected to the first 40 inputs of data switches of the first group, the second inputs of which are connected to the first inputs of the OR elements of the group and to the outputs of the AND elements of the group whose inputs are a group of inputs of the selection 45 of the memory unit of the communication unit with an external device, the second group of address inputs which is connected to the first group of inputs of the address switch, the second group of inputs of which is the first group of address inputs of the communication unit with an external device, the second sample input of which is connected to the first input of the first And element, the output of which is connected to the second control input of the address switch and connected with the second input of the first element EXCLUSIVE OR, with the first inputs of data switches of the second group and with the second inputs of the OR elements of the group, the outputs of which are connected to the inputs of the sample storage devices, in the mode moves of which are connected to the output of the element OR NOT, whose inputs are connected to the outputs of the first and second elements EXCLUSIVE OR, the first input of the second element EXCLUSIVE OR is the second input of the transmission permission of the communication unit with an external device and connected to the second inputs of data switches of the second group , the first group of input-output of which is connected to the first group of input-output of data switches of the first group and with the input-output of data of memory devices whose address inputs are connected to the outputs of the comm address, first and second groups of inputs and outputs of the communication unit with an external device are connected to the second group of inputs-outputs of the first and second groups of data switches, respectively; input The exchange gate of the communication unit with an external device is connected to the first input of the second element, whose output is connected to the third inputs of the AND elements of the group, the second input of the second element AND is connected to the output of the first element NOT, the input of which is connected to the first input of the first element AND, the second input of which is connected to the output of the second element NOT, in d is connected to the dog - vym input of the second AND gate, whose output is connected to a second input of the second exclusive OR element. gi g I computer j s % l1 Lj   b ,. 7t you P | ± nd t 8Umi II 0. / CV CM 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