SU1149239A1 - Information exchange device - Google Patents

Abstract

A DEVICE FOR INFORMATION EXCHANGE, containing a buffer data memory, a group of interface blocks of subscribers, a memory block of commands and operands, a block for selecting commands from a memory, the information input / output of the buffer data memory being connected via the first information bus to the information inputs / outputs of the interface blocks group subscribers, the information input / output of the command selection block from the memory through the second information bus is connected to the information input / output of the memory block of commands and operands, which With the fact that, with the extension circuit of the application area, due to the possibility of connecting subscribers with different interfaces and speeding up, a control signal generation unit, a data buffer storage control unit and a group of interface control units are introduced in the Negro, and a group of information inputs of control units the interface of the group and the group of informational inputs of the block Formation of control signals are connected via the second information bus to the group of informational outputs of the block selection commands from the memory, the first group of command outputs of the command selection block from the memory is connected to the group of command inputs of the control signal generating unit, the group of control inputs of the subscriber signals of which are the device of the same name as the device, and the group of control of the subscriber outputs of the same name device outputs and connected to a group of control inputs of each interface control unit group, a group of signal outputs of which is connected to a group of like-named inputs of the form block (Le l kntsih sound control signals, the group of control inputs connected to the output interface units errors group forming unit output control signals coupled to the CIM blokiruk input sample block commands from the memory, the output koto4; connected to the input of the memory block of commands and operands, QD is the second group of command outputs of the block to fetch commands from the memory connected to the permitting inputs of the control blocks; about the interface interface whose interface control outputs and address outputs are connected respectively to the control inputs of the interface the blocks of the group and the group of inputs of the control block of the buffer memory of data, the first and second groups of outputs of which are connected respectively to the group of address inputs of the buffer memory of the data and the resolution ayuschimi input interface block group, the block generating the control signals

Description

contains a command latching node, two switches, an interrupt mask register, a control signal register, a group of I-NLI elements and a group of signal conditioners, the group of informational inputs of the block is connected to the information inputs of the command latching node and the interrupt mask register, which controls and the control inputs of the first switch and the driver of the parameters of the signals of the group form the group of command inputs of the block, the group of information inputs of the drivers of the parameters of the signals of the group and the first switch is connected to the output group of the second switch, the outputs of the signal conditioners of the group signals are connected to the first input group of the second switch and together with the output group of the control signal register form the control subscriber output group of the unit, the output switch group of the first switch whose group of codes is connected to the first inputs of the elements. Commodity AND-OR groups and the second group of inputs of the second switch, the third and fourth groups of inputs of which are the group of inputs of control signals of subscribers and the group of control inputs of the block, the group of outputs of the register of the interrupt mask are connected to the second inputs of the elements of the I-III group, whose outputs form the output of the block, the second group of control inputs of the first switch is a group of signal inputs of the block, the outputs of the command latching node are connected to the command inputs of the signal conditioners of the group signals and the first comm In addition, each interface control unit of the group contains a resolution trigger, a command latching node, two multiplexers, three counters, an AND element, a deputirator, a memory reference node, and a gate driver, and a single resolution trigger input and control of the first inputs multiplexer, command latching node and memory accessing node form the block enable input, groups of information inputs of the first and second multiplexers - a group of control inputs of the block, zero input and output of the trigger events are connected

correspondingly with the output of the And element and the enabling input of the first multiplexer, the group of control inputs of the first and second multiplexers, the enabling input of the second multiplexer, the installation inputs of the gate generator of the memory reference node, the first, second and third counters, the first input of the And element and the first group the decoder inputs are connected to the corresponding bit outputs of the command latching node, the output of the first multiplexer is connected to the enable inputs of the gate generator the memory access node, counted by the inputs of the first, second and third counters, the control input of the second multiplexer is connected to the output of the second counter, the output of the second multiplexer is connected to the fault inputs of the first, second, third counters that block the input of the memory access node by the second input element I and the first input of the decoder, the output of the first counter is connected to the control inputs of the gating pulse shaper of the memory access unit and the second inputs of the decoder, the third input of which is connected to the output the house of the third counter, the outputs of the gating pulse generator and the memory access node are respectively the control and address a & block codes, the decoder group of outputs — the group of signal outputs of the block, the information inputs of the command latching node and the address node of the memory form the group of information inputs the block, in addition, the data buffer storage control block contains a request fixation node, a priority node, three OR elements, a group of elements AND, a trigger, a delay element, and a group of elements AND-OR, and The node of the request fixing node and the I-SHW element of the image block group of block inputs, the outputs of the request fixation node are connected to the priority node inputs, the first and second groups of outputs of which are connected respectively to the inputs of the first and second OR elements, the outputs of which are connected to the first through the third SHSh element the trigger input and through the delay element - with its second input, the trigger output is connected to the enable input of the priority node, the intermediate codes of the delay element are connected to the first inputs of the AND groups, the second inputs which are connected to the outputs of the priority node, and their outputs form the second group of ka, the outputs of the first and the cops OR, and the outputs of the AND-OR form the first moves of the block.

one

The invention relates to computer technology, in particular, to information exchange systems, and can be used to construct computer channels that provide exchange with dissimilar input / output devices, to build control devices for external devices (input / output devices) that enable the exchange of dissimilar channels. Computer, and when building self-contained interface devices to ensure the exchange between computer heterogeneity and (or) dissimilar input-output devices.

A device for exchanging information is contained, comprising communication units of input-output devices and computer channels (hereinafter referred to as subscriber interface units) and a processor controlling the data buffer and interface units, with a memory for instructions and operands, a priority unit control unit and units commutation

A disadvantage of this device is its limited versatility when communicating with heterogeneous subscribers.

The closest to the invention in its technical nature is an exchange device containing a buffer data memory, interface blocks, a memory of instructions and operands controlled by a C23 processor.

The disadvantages of the known device are the lack of versatility when working with heterogeneous subscribers and low speed ;.

The aim of the invention is to expand the scope of use by providing connectivity to subscribers with different interfaces and improving speed.

The goal is achieved by the fact that the device contains; a buffer data memory, a group of interface units of subscribers, a memory block of commands and operands, a block of selection of commands from the memory, and the information input-output of the buffer data memory is connected to the information inputs-outputs of the interface blocks of subscribers of the group via information first. the input-output block of the selection of commands from the memory through the second information

the bus is connected to the information input-output of the memory block of commands and operands, the block of the formation of control signals is entered, the block of control of the buffer memory of data

and a group of interface control blocks, the group of information inputs of the interface control blocks of the groups and the group of information inputs of the control signal generation block are connected via the second information bus to the group of information passes of the command selection block from the memory, the first group of command outputs of the sampling block connected to the G1 uppo command inputs of the block of the forging control signals, the group of control inputs to the subscribers of which signals is a group of like

device inputs, and the group of control to the subscriber outputs cx is a group of like outputs; device and connected to the group of control inputs of each interface control unit of the group, the group of signal outputs of which is connected to the group of the same name inputs of the control signal generation unit, the group of control inputs of which is connected to the error outputs of the interface blocks, the output of the control signal generation unit is connected blocking the input of the instruction sampling block from the memory, the output of which is connected to the address input of the memory block of instructions and operands, the second group of command outputs of the block commands from the memory are connected to the enable inputs of the interface control blocks of the group, the interface control outputs and address outputs of which are connected respectively to the control inputs of the interface blocks of the group and the group of inputs of the buffer memory control block, the first and second groups of outputs of which are connected respectively to a group of address inputs of the buffer memory dann and permissive inputs of the interface blocks of the group, with the block forming the control signals containing the command fixing node, two switchboard, interrupt mask register, control signal register, group of AND-OR elements and group of signal conditioners, the group of information inputs of the block is connected to the information inputs of the command latching node and the interrupt register, the control inputs of which and the control inputs of the first the switch and driver of the signal parameters of the group form a group of command inputs of the block, groups of information inputs of the driver of the signal parameters of the group and the first switch are connected to the group the outputs of the second switch are connected to the first group of inputs of the second switch and, together with the group of outputs of the control register, form the control group of the subscriber outputs of the block; the group of outputs of the first switch is connected with the group of inputs of the control register; group of outputs which is connected to the first inputs of the elements of the AND-OR group and the second group of inputs of the second switch, the third and fourth groups of inputs of which are a group of inputs the equalizing signals of subscribers and the group of control walks of the block j the group of outputs of the register of the stop mask is connected to the second inputs of the elements of the AND-OR group whose outputs form the output of the block, the second group of control inputs of the first switch includes the group of signal inputs of the block, the outputs of the latching command node soy dinens with. command inputs of the parameters of the group signals and the first switch; in addition, each group interface control block contains a resolution trigger, a command latching node, two multiplexers, three counters, an AND element, a decoder, a memory reference node and a gating driver, and the single input of the trigger trigger and the control inputs of the first multiplexer, the command latching node, and the memory access node form the enabling input of the block, the group of information inputs of the first and second multiplicates The eXors image5pot rpjmny control inputs of the block, zero input and output of the resolution trigger are connected respectively to the output of the element N permitting input of the first multiplexer, control groups of the first and second multiplexer inputs, enabling input of the second multiplexer, setting, inputs of the gate generator pulses of address access memory these first, second and third counters, the first input of the element And and the first group of inputs of the decoder are connected to the corresponding output of the 1st outputs of the command fixing node, The output of the first multiplexer is connected to the enable inputs of the gating pulse generator and the memory accessing node, the counting inputs of the first, second and third counters, the control input of the second multiplexer is connected to the output of the second counter, the output of the second multiplexer is connected to the fault inputs of the first, second and third the counters, the blocking input of the memory access node, the second one by the input of the AND element and the first input of the decoder, all the first counter is connected to the inputs # 1 of the aerobilizer pulses, the memory access unit and the second input of the decoder, the third input of which is connected to the output of the third counter, the outputs of the pulse strobe generator and the memory access node are respectively the control unit and the address outputs of the unit, the decoder sysods group the block outputs, the information inputs of the command latching node and the memory access node form a group of informational inputs of the block, in addition, the data buffer storage control block contains a request latching node, ate priority three elements; OR, a group of elements AND, a trigger, a delay element and a group of elements AND-OR, and the inputs of the request fixing node and the elements AND-OR of the group form a group of block inputs, the outputs of the request fixing node are connected to the inputs of the priority node, the first and second groups of outputs of which connected respectively to the inputs of the first and second elements OR, the outputs of which through the third element OR are connected to the first input of the trigger and through the delay element to its second input, the output of the trigger is connected to the enable input of the priority node, intermediate the outputs of the delay element are connected to the first inputs of the AND elements of the group, the second inputs, which are connected to the outputs of the priority node. and their outputs form the second group of block outputs, the outputs of the first and second OR elements, and the outputs of the AND-OR elements form the first group of block outputs. FIG. 1 shows a block diagram of the device i in FIG. 2 is a block diagram of the interface control unit; in fig. 3 shows a structural scheme of a control signal generating unit; in fig. 4 shows an example of a possible construction of a buffer data storage control unit. The device contains a buffer memory 1 data, a group of interface units 2 subscriber, a unit 3 for sampling mandas from the memory (processor), a storage unit 4 for commands and operands, a unit 5 for generating control signals, a group for control unit 6 for interface, a block 7 for buffer control data memory, data bus 8, subscriber data bus 9, multiplexers 10 and t1, trigger 12 times, counters 13-15, AND 16 element, strobe pulse generator 17, memory access node 18, decryptor 19, fixation nodes 20 and 21 commands, switches 22 and 23, regis p 24, control signals the interrupt mask register 25, the interrupt signal generator 26, signal conditioners 27-29 parameters, fixing unit 30 queries. priority node 31, elements OR 32-34, trigger 35, delay element 36, AND 37 group, AND-OR 38 group of elements. The device operates as follows. Before starting work, when assembling a system into a permanent memory, which is part of the memory block of 4 instructions and operands, the program of the processor operation and the constants necessary for its execution are entered, a fixed part of the control information is dialed on the switching fields of the nodes 20 of the interface control blocks 6 required for the operation of these blocks (for example, an indication of whether pteidal or impulse signals should be given to the subscriber by the corresponding interface unit 2, the duration of the output pulses, etc.), In the first switching field of node 21 of block 5, the constant part of the control information necessary for the operation of this block is recruited (for example, indications of the polarity and duration of the output signals of the autonomous signal processing nodes), the second switch 23 of block 5 establishes a certain switching of inputs for signals control, nocTynaicaiix from subscribers to the inputs of the block and its own outputs, the outputs of block 5 are connected to the wires for transmitting control signals to the subscriber, and the information inputs and outputs of the currents 2nd information number of subscribers (input-output devices and / or computer channels). Further operation of the device is carried out under the control of the program of the processor 3. When executing certain commands (i.e., commands with certain operation codes), the processor organizes reading of block 4 of the variable parts of the control information from block 5 or block 6 and generates signals respectively The rta outputs for control signals, on receipt of which in block 5 or in one of the blocks 6, information is received from the information bus of the memory block 4 into the comaid word register, has a position in the composition 21 of block 5, or in the command word register of node 20 of block 6. Similarly, the processor (when executing instructions with other operation codes) organizes a transfer of information from memory 4 of block to register 25 of the interrupt mask, which is part of block 5, and to registers of the initial address of node 18 in blocks. The processor program can be constructed so that in the further operation of the device, the processor assumes all the functions for managing the interface. Consider this option. Option A. The wiring of control signals from subscribers on switch 23 and the information in register 25 of the interrupt mask of block 5 are such that any control signal coming through the interface from a subscriber to one of the inputs of block 5 always causes a signal to appear on one of the of the outputs of block 5, arriving at the corresponding 5 input from among the inputs for interrupt signals of processor 3. This signal initiates the execution in program 3 of the program, which processes the necessary response to the incoming control signal from the subscriber. In turn, the processor, when executing certain commands (with certain operation codes), sends signals to its outputs for control signals which, arriving at the inputs of block 5, and inside block 5, at the inputs of switch 22, set to state 1 or O triggers in the control signal register 24, while the outputs of block 5 generate control signals for subscribers. The exchange of information between subscribers and data storage 1 in the considered variant of work organization is carried out as follows. Initially, the processor establishes in node 20 of block 6, connected via block 2 with this subscriber, information that, together with the control information gathered on the switching field of node 20, indicates that multiplexers tO and 11 should not be triggered by signals on their informational. inputs, and also contains instructions on the direction of exchange, format of the subscriber, whether there are information on the subscriber’s work, bits of control bytes mod 2 and the polarity of the control signals, the form and duration of the output information signals for the subscriber, the number the shifts to be completed to fill or release the shift register in block 2 prohibiting the output of the output signals by the second and third counters 14 and 15 for the case when information is transmitted in the direction from the subscriber, and during transmission Formations in the opposite direction - about the number of input signals of the second counter 14, upon reaching which the output signal should be generated, TpetbeMy counter 15 does not allow output signals in this variant for any exchange direction, about the format of accessing the data memory 1 in the interests of information exchange with this subscriber. Next, the processor 3 generates signals at one of its outputs for control signals, which are connected by one of the inputs of the necessary block 6. These signals are passed directly to the output of the first multiplexer to and from it to the counting input of the first counter 13 17 and to the input of node 18. Thus, in the situation under consideration, the first signal, outputted by the processor 3 at that of its outputs for control signals, which inside the considered block 6 is connected to the auxiliary input of the first multiplexer 0, ultimately e leads to the reception in the shift register of block 2 of the group of bits from the information bus of the subscriber, the group size corresponds to the subscriber format and the subsequent shift of information in this register by the same number of bits, as well as an increase by one code in counter 13 in the block 6, associated with this block 2. Until the shift register in block 2 is filled after the signals at the same output of the processor will produce a similar action. When filling the shift register in block 2 {i.e. when the amount of information in the register will be equal to the specified format for accessing the dunk buffer) the code accumulated in

counter 13, coincides with the code set in advance at those outputs of node 20, which are connected to the installation inputs of the specified counter 13, with the result that the signal received at its counting input causes the output signal to appear. The output of the first counter 13 is connected to the control input of the driver 17 and to the input of the node 18..

The input of the generator 17, the output signal of the counter 13 blocks the shift signals so that the last of the signals arriving at the input of the generator does not cause a control signal to appear. The output shift, but in the usual way forms a receive gate in the shift register, as a result The last group of bits from the subscriber is received in the svdigovy register of block 2.

The total number of signals triggered by the processor 3 for a one-time operation of the block for performing one communication session is generally the ratio of the format of accessing data memory 1 to the subscriber format. For example, if the subscriber format is 1 byte, and the memory access format is 4 bytes, then the number of processor signals is -. but 4. There may be exceptions to this rule, for example, if the subscriber format is 1 bit, the subscriber word has a format of 27 bits, and mod 2 control is not used, then the number of processor signals to perform a communication session is 27, the memory recording format 1–4 bytes with the formed check and bits (36 bits in total), but in the last byte 5 data bits are not filled. Depending on the subscriber properties, the processor program either independently determines the time intervals between the specified signals or relies on an interrupt signal generated from control signals from the abrnent.

A special case of the described exchange session is that the subscriber format is equal to the access format: the data buffer. In this case, in node 20, the code must be set ... 0001 in those output bits that are connected to the installation input of counter 13, the first signal from the processor that passed through the input of the first multiplexer 10 to

its output also passes to the output of the counter 13. As can be seen, no shifts in the shift register of block 2 occur, and immediately the node 18 triggers writing data information received from the subscriber to the shift register of block 2 into memory 1.

The subscriber exchange session with the data memory t in the case where information is transmitted in the direction from the data memory to the subscriber, for the considered operation of the device, is similar to the above described case of information transmission in the opposite direction with the following differences.

The first processor-initiated signal, which passed in block 6 through multiplexer 10, enters the input of shaper 17. The same signal, arriving at the input of node 18, passes through it to that of the outputs of the signals and memory access addresses of data 1 from block 6 as signal reading. Other circuits of node 18 operate in the same way as when writing (see above). The Read signal from block 6 goes further to one of the inputs of block 7, as a result of which, one of the outputs of block 7 of the data buffer management is formed with the Read command (and the Write command at the output). The output signal for the response signals of block 7, which was blocked in the write cycle in block 2, in this case, at the appropriate time, allows reception into the shift register of block 2 of information from the information bus read from data memory 1, passes through the corresponding the input for the control signals of block 2 to the input for the reception strobe, which is among the inputs for the control signals of the input logic circuits

If the subscriber format is smaller than the format for accessing the data memory, then the second signal, initiated by the processor and passed to the output of multiplexer 10 in block 6, is fed to the input of the driver 17 and forms the Shift command. Output signal

entering through one of the outputs of block 6 to the corresponding input for the control signals of block 2 is a gate for extracting information from the shift register of block 2 to the subscriber. At the same time, inside the imager 17, the output signal passes the pulse generator signals to the counting input of a counter (not shown). When the number of passed pulses is compared with a given code of the output signal duration, it is received from node 20 to the group of inputs of the generator 17 which is connected to the installation inputs of the counter, the output of which removes the strobe information to the subscriber. If the highest bit of the pulse duration code contains one, then the output signal of the specified counter is blocked, and block 2 picks up potential signals to the subscriber. In fact, when transmitting pulsed signals, the Shift command must be delayed by the duration of the shift register shift register. Each of the subsequent signals from the output of multiplexer 10 also causes a shift in the shift register of block 2 and the generation of the strobe to transmit the next group of bits to the subscriber. This happens until simultaneously with the signal at the output of the multiplexer tO, the signal at the output of counter 13 also does not appear, which in this case indicates the release of the shift register in block 2 and arriving at the input of the ramp 17 and at the input of the node 18. Unlike situations when information is transmitted from the subscriber to the data memory and when the number of signals that the processor must initiate at the output of multiplexer 10 to drop a single communication session with the subscriber is generally the ratio of the format to the data buffer to the forms At the subscriber’s time, in the considered situation the number of these signals should be one more. Since the first of these signals is spent reading information from memory 1 of data into the shift register, the signal of the shift register filled (released) is actually generated by the counter 13 in block 6 the moment when the release of the shift register is not yet completed and an additional one-time operation of the autonomous control unit by the interface is required. The specified additional signal from the output of multiplexer 10, arriving at the input of the driver 17, does not cause the output Shift command to occur. The particular case of the described exchange session, when the subscriber format is equal to the format for accessing the data buffer, differs from the above special case for transmitting information in the direction from the subscriber. If, when transmitting information from the subscriber to the indicated particular case, the processor should initiate only one single triggering signal of the autonomous control unit of the interface, then two such signals are necessary. The code installed in node 20, as well as when receiving from the subscriber, must be. ,, 0001. Therefore, the first one-time signal triggered from the output of multiplexer 10 simultaneously causes the signal. The shift register is filled (released) at the output of the counter 13 node. These two signals, arriving simultaneously at the inputs of the imaging unit 17, cause the read and modify address signal to appear. In order for the next signal of one-time operation of block 6 not to cause the occurrence of a repeated signal. Reading and another modification of the address, the code ,,, 0010 must be preset at the inputs of counter 14. Then, simultaneously with the second one-time actuation signal of block 6, a signal appears at the output of counter 14, which passes directly to the output of multiplexer 11. The second one-time actuation signal of block 6 arrives at the input of the forerunner 17 and starts strobe information from the shift register of block 2 to the subscriber . At this time, the session with the subscriber ends. Consider a variant of operation of the device, in which all signal processing for subscribers, that is, the exchange of information between subscribers, on the one hand, and memory 1 of data on the other, continue, as in version A, under direct control of processor 3, but essentially the possibilities of block 5 and blocks 6 are used, as a result of which it achieves a significant economy. in the number of processor operations per generation of a single control signal for the subscriber and for the implementation of the actual exchange. The indicated savings in this variant, hereinafter referred to as variant B, are achieved in cases when a series of signals of the same type are to be formed and sessions of communication with the subscriber are made of the same type. Option B. If the subscriber has to generate control signals for the subscriber from the series, the processor initially falls asleep (as it was described above) in the register of node 21 of block 5, which together with the information typed on the switch after the specified block contains instructions which from the outputs of node 21 are fed to the code inputs of any of the formers 27-29 about the required time delay of the output signals relative to the processor signals, which further trigger the operation of this / node about d output polarity. Next, the processor only needs to execute just one command, forming a control signal on that of its outputs, which is connected to a defined Hbw input for controlling the formers 27–29, and as a result, the output of this driver, is one of the outputs of block 5 and connected to one of the wires for transmitting control signals to the abonent, a signal is generated, the duration of which, the polarity and time delay relative to the control signal emitted by the processor are predetermined, and the need for processor operations for switching the trigger in the control signal register, counting the required duration of the control signal and returning the trigger in register 24 to the initial state (after the required pulse duration has elapsed) disappears. The processor programs are also greatly simplified for the case when the output signal has to be related to the time of the actual exchange with the subscriber (shifts in the shift register of the interface unit, generation of issue gates from the shift register, etc.). And 9 When organizing the actual exchange with the subscriber in the considered variant of organizing the operation of the device, it is assumed that homogeneous sessions of information exchange between the subscriber and the data memory will be repeated many times, and sequential addresses will be selected in the data memory. If the number of exchange sessions is large, then the address area should be limited and closed in a ring. Initially, as in option A, the processor dumps the mapping information into the register of node 20 of block 6 and the address, corresponding to the starting address of the allocated address area in data memory 1, into the register of starting address at node 18. Information sent to the command spruce register , together with the information typed on the switching field of node 20, should, in addition to what was required for option A, contain an indication of the need to organize a ring in the data buffer and the size of the ring (in the form of a unit on one and Input node 18, otherwise the ring is not organizuets). Unlike option A, in cases where a processor program must respond appropriately to the completion of the exchange of a certain amount of information (for example, filling in or clearing half of the address space allocated in the buffer), and / or if the number of homogeneous exchange sessions is known in advance, to be executed, after which the processor program must perform some new operations, the information in the register of node 20 and on the switching field of node 30 must contain codes for the inputs of counters 15 and 14, allowing the generation of a signal and corresponding to the number of one-time block operations at which the intermediate signal for the processor should be terminated and / or the specified number of homogeneous exchange sessions completed. In addition, at the outputs of node 20, there should be set codes transmitted to the inputs of the decoder 19 corresponding to the register bit numbers 24 to which intermediate sigals for the processor and the signal about the completion of a specified number of homogeneous exchange sessions to be transmitted (if the need for transmission the signal is missing, the code input is set to code 01 ... 00), and in the interrupt mask register 25, such information must be sent so that the signals arriving at the specified bits of register 24 cause the appearance ignalov interrupt to processor. After the specified information is set in the corresponding registers, the processor remains only to initiate signals of a one-time operation of the unit for autonomous control of the interface. If information is transmitted in the direction from the subscriber, then each of the communication sessions with the subscriber is almost completely analogous to the described type (in option A). As can be seen, at the end of each communication session, the last signal triggered by the processor for one-time operation of the autonomous interface control unit calls the write register from the shift register to the data memory 1 and at the same time adds to the contents of the register a modifier having 18 access to the data buffer. (In the particular case when the subscriber format is equal to the format for accessing the data buffer, the entire communication session consists of one one-time response of the URI unit 6). If the next session is immediately followed by this session in the same way, then writing to the data memory occurs at the address incremented by the recording format (i.e., into the next memory bytes), etc. In the case when information is transmitted towards the subscriber, the first session is similar to the communication session specified in option A: the number of signals generated by the processor 3 dp of one-time operation of unit 6 is one more than the ratio of the data memory format 1 to the subscriber form (in case of equality 50

formats, the number of signals is two), the first signal reads from memory 1 of data, the subsequent ones form Shift commands and information entry gates from the shift register of block 2 to the subscriber, which relates to the last signal, then in the driver 17 this signal is the same as

A block associated with node 18 is a count of the number of calls to the data buffer and the associated address modifications.

However, a much greater gain is achieved in the variant of the organization of work (hereafter variant B), in which processor 3 of variant A, produces a strobe formation, but without the Shift command. At node 18, the action of this signal (unlike option A) is not blocked by the signal arriving at the input of the node, but, like the first signal in the session, generates a signal for reading and initiates a modification of the address. Thus, the last one-time operation signal of block 6, ending the first communication session, begins at the same time the second session (reception in the shift register of new information from memory 1 of data occurs with a delay of read time, which is generated in block 7, t. e. after sending to the subscriber of the last group of bits from the information of the previous session). Therefore, the number of one-time triggers of block 6 for performing the second and each of the subsequent communication sessions with the subscriber is equal to the ratio of the format of accessing the buffer to the format of the subscriber, i.e. one less than for the first session, and equal to the number of one-time unit trips. Required to perform a session with the subscriber in the opposite direction. In the particular case of equalizing the format of accessing the data buffer to the subscriber format, the first communication session is performed in two one-time triggers of block 6, and all subsequent ones in one, and the very first triggering consists in organizing reading from memory 1 of data in the shift register of block 2 and modifications of the address, and all subsequent ones (except for the most recent) in the subscriber’s information, read during the previous triggering, organization of a new reading from the memory 1 of the data and modification of the address. In any case, both when transmitting information to the subscriber, and when receiving information from the subscriber, counters 14 and t5, which are included in the block, when performing a sequence of homogeneous sessions with a subscriber, only general indications of blocks 6 and 5 and, possibly, is included to work out critical situations or change the mode of operation of the device, and all processing operations. control signals from subscribers, developing response signals for subscribers, organizing the actual exchange of information between Onentami and memory 1 data and determine situations when you need to contact the processor, are organized by block 5 and blocks 6 in interaction with blocks 2, memory 1 data and its control block, and the interaction of blocks 6 with each other and with block 5, and Also, calls to processor 3 (through its interrupt system) are organized through block 5. Option B, At the beginning of the program execution, the processor sends command words to node 21 and interrupt mask register 25, to node 20 command registers and node initial address registers. 18 block in 6. The contents of the register of node 21 in the aggregate with the information selected on the switching field of this node should form the following instructions in the form of signals at the outputs of node 21 of this block: the signals of which must be selected for a given node as signals Y and X; about the logical operation that should be performed on the signals Y and X j about whether to stop the further operations of the node from the input signals Y and X after its first operation (until a new resolution from npouiaccopa); about the time delay of the output signal of the node relative to the signal initiating its actuation; about the duration and polarity of the output signals - similar to that specified in variant B. The contents of the register of the node 20 in combination with the information typed on its switching field of each of the blocks, should form the following indications on the outputs of node 20 on the number of the output signal of block 5, which should initiate a one-time serv. blocking, about the method of finishing work on a given command word, the end of a command word can be fixed either by the number of information transmitted, or by an external signal for a given block, or mixed by one or another sign; about the direction of exchange with the subscriber, the associated block 2 is associated, about the format of this subscriber, about whether the subscriber has information on which the subscriber works with, mod 2 control bits, and about polarity of control signals about the form and duration the output information signals dp of the subscriber, the number of shifts to be made to release or fill in the shift register in lock 2, the format for accessing data memory 1 in the interests of exchanging information with the subscriber is similar to the instructions in variants A and Bj whether or not the organization exchanges a ring in the data buffer with this subscriber and the size of this ring, the number of one-time triggers of block 6 at which the intermediate signal should be generated and the digits of the register of control signals to which this intermediate signal should be transmitted and a signal about the end of work on this command word (or about the absence of the need to transfer this signal to the control signal register) —a analogous indication in option B, but with the difference that The codes on the code inputs of the decoder 19 can indicate both the need for setting a certain bit of the control signal register to one, and the need to set the need or not to transfer the output signal of the counter 13 in block 5, also the number control register bit, where this signal should be transmitted and to which input of the specified bit (unit setting or zero) as a code on those outputs of node 20, which are connected to akho d vi Ator ash 19; about the need for its absence, stop the operation of block 6 according to the signals from block 5 when the signal for the end of work on this command word is sent. Spreading the control information into the registers of block 5 and blocks 6, processor 3 is further in the order determined by its program, hiding the permissions for operation of the formers 27-29, which are part of block 5 for processing the output signals of the switch 23 of this block and the resolution for triggering blocks signals from the outputs of block 5 signals in accordance with the instructions in the control information. For this, the processor performs the operations that form the control signal sig nals, respectively, at its outputs dp control signals connected to the inputs of the block5, and inside this block to the control signal inputs of the drivers 27-29, as well as generating control signals at the outputs controls connected to the inputs of the blocks 6, and inside these blocks to the inputs for switching the resolution triggers 12, the resolution triggers in the formers and in the blocks 6 are set to state 1. Before or after this, the processor 3, it is possible (in accordance with its program), generates some initial control signals at the outputs of block 5 (as in variants A and B) and initiates the initial operations of blocks 6 (as in variant B, for example, in order make the first reading from the data memory I of information in the shift register of block 2 for the subscriber: which then receives information on signals generated in another way), then goes into standby mode. Thus, block 5, in accordance with the initial g4ytation, produced in advance on the first and second co-operation fields, and the control information set by processor 3 in its register of node 21, may work in conjunction with those block fi 6, which are used as scaling circuits, processes all control signals j from the subscriber, signals generated inside the device, and extracts control signals for subscribers, signals to initiate triggers of blocks 6 and to form in these blocks x signals of an eye of work on the set command word. 1 920 The actual exchange of information between subscribers and the memory 1 of the data is generally the same as option B with the following three differences. First, the one-time operations of the blocks 6 are initiated not by the processor, but by signals coming from the outputs of block 5 to the inputs of block 6 autonomous, but inside this block, in particular, to the information inputs of the multiplexer 10, where the desired signal is selected according to the preset on the code input. Secondly, the output signals of the meter nodes 13-15, the passage to the outputs in accordance with the codes that are set in advance at the inputs of the decoder 19, going further to the inputs of block 5, can set certain bits of the control signal register 24 in this block as in state 1 and to state O (depending on the codes located on the above code inputs of the decoder 19), and are generally not intended to interrupt processor programs, but to generate control signals and organize the interaction of blocks 6 between Oh, and with block 5. Thirdly, the end of work of some block 6 by a given command word can be determined not by the amount of information passed between the subscriber and the data memory 1, or not only by this quantity, but also by one of the signals coming from the conclusions of the block control signals 5 to the inputs of block 6. When there is a permitting signal at the input of the second multiplexer 11, the signal that passes to the output of the multiplex is selected from the signals from the inputs of the block connected to the inputs of multiplexer 11, according to the number indicated by the code at its input ora, sets counters 13–15 in O, passes through a decoder 19 to one of the outputs of the block and further to the corresponding input of the control signal block 5, and at node 18 either writes to the memory 1 of data in case the exchange goes from the direction the subscriber, even if the shift register is not. Fully full, or blocks reading from the data memory 1, if the transmission goes in the direction to the subscriber, and the signal for the end of the exchange according to the control word coincides with the data release signal of the data memory 1. The interaction of the device blocks with each other in version B is carried out mainly through block 5. The possibilities that can be realized at the same time are quite diverse; one

FIG. 1 922, the specific features of the interaction, as is clear from the preceding, are determined by the control information at nodes 20 and 21. Thus, the invention improves the efficiency of the device.

rfi

four

I

/ V

  Urfn 2 1 f I I

 I II I

hi t

Js

.lyv:

17t ..... .... ..:

Claims (1)

DEVICE FOR INFORMATION EXCHANGE, containing a buffer data memory, a group of interface blocks of subscribers, a memory block of commands and operands, a block of fetching commands from the memory, the information input-output of the buffer data memory via the first information bus connected to the information inputs and outputs of the interface blocks of subscribers of the group, the information input-output 'of the block of fetching instructions from the memory through the second information bus is connected to the information input-output of the memory block of commands and operands, which is different that, in order to expand the scope by providing the ability to connect subscribers with various interfaces and improve performance, it includes a control signal generation unit, a buffer data memory control unit and a group of interface control units, and a group of information inputs of the group interface control units and a group the information inputs of the Generating unit of r control signals are connected via the second information bus to the group of information outputs of the block of sample commands from Namely, the first group of command outputs of a block for selecting commands from memory is connected to a group of command inputs of a block for generating control signals, the group of inputs of control signals of subscribers of which is a group of inputs of the same name, and the group of control of user outputs is a group of outputs of the same name and connected to a group of control inputs of each the control unit of the group interface, the group of signal outputs of which is connected to the corpse of the same inputs of the control signal generation unit , the group of control inputs of which is connected to the error outputs of the interface blocks of the group, the output of the block for generating control signals is connected to the blocking input of the memory instruction block, the output of which is connected to the address input of the memory block of commands and operands, the second group of command outputs of the sampling block commands out of memory connected to interface control blocks enable input group interface control outputs and address outputs ³ are connected respectively to the control inputs of the interface x block group and a group of input data into the buffer memory control unit, the first and second groups of outputs koto1149239> They are connected respectively to a group of address inputs of the data buffer memory and enable inputs of the interface blocks of the group, the control signal generating unit comprising a command fixation unit, two switches, an interrupt mask register, a control signal register, and a group. poo of AND-OR elements and a group of signal parameter generators, the group of information inputs of the block connected to the information inputs of the command fixation node and the interrupt mask register, the control inputs of which and the group of control inputs of the first switch and the signal conditioners of the group form a group of command inputs of the block, information groups the inputs of the shapers of the parameters of the signals of the group and the first switch are connected to the group of outputs of the second switch, the outputs of the shapers of the parameters of the signal group connected with the first group of inputs of the second switch and together with the group of control signals form a group of register outputs control outputs subscriber unit, a group of first switch outputs coupled to inputs of the register group of control signals which output group coupled to first inputs of elements. of the AND-OR group and the second group of inputs of the second switch, the third and fourth groups of inputs of which are the group of inputs of the control signals of the subscribers and the group of control inputs of the block, the group of outputs of the interrupt mask register is connected to the second inputs of the elements of the AND-OR group, the outputs of which form the output of the block , the second group of control inputs of the first switch is a group of signal inputs of the block, the outputs of the unit for fixing the command are connected to the command inputs of the conditioners of the signal parameters of the group and the first comm At the same time, each group interface control unit contains an enable trigger, an instruction fixation unit, two multiplexers, three counters, an And element, a decoder, a memory access unit and a gate pulse generator, with a single enable trigger input and control inputs of the first multiplexer, unit fixing the command and the memory access node form the block enable input, the group of information inputs of the first and second multiplexers - the group of control unit inputs, the zero input and output of the enable trigger connected respectively with the output of the And element and the enable input of the first multiplexer, the group of control inputs of the first and second multiplexers, the enable input of the second multiplexer, the setup inputs of the gate driver of the memory access node, the first, second and third counters, the first input of the And element and the first group of inputs the decoder is connected to the corresponding bit outputs of the command fixing unit, the output of the first multiplexer is connected to the enable inputs of the gate generator LSS and the memory access node, the counting inputs of the first, second and third counters, the control input of the second multiplexer is connected to the output of the second counter, the output of the second multiplexer is connected to the reset inputs of the first, second, third counters, blocking the input of the memory access node, the second input of the element And with the first input of the decoder, the output of the first counter is connected to the control inputs of the gate pulse generator, the memory access unit and the second inputs of the decoder, the third input of which is connected the output of the third counter, the outputs of the gate pulse generator and the memory access node are respectively the control and address outputs of the block, the decoder output group is the group of signal outputs of the block, the information inputs of the command lock node and the memory access node form a group of information inputs of the block, in addition, the block buffer data management contains a request fixing node, a priority node, three elements OR, a group of AND elements, a trigger, a delay element and a group of AND-OR elements, and The s of the request fixing node and the AND-OR elements of the group form a group of block inputs, the outputs of the request fixing node are connected to the inputs of the priority node, the first and second groups of outputs of which are connected respectively to the inputs of the first and second OR elements, the outputs of which through the third OR element are connected to the first input of the trigger and through the delay element with its second input, the output of the trigger is connected to the enable input of the priority node, the intermediate outputs of the delay element are connected to the first inputs of the elements AND groups, the second inputs to toryh connected to the priority output node, and their outputs ob1149239 block form a second group of outputs, outputs of first and second OR elements and outputs of the AND-OR block form a first group of outputs.