SU1129601A1 - Firmware device for applying control and exchanging data - Google Patents

Abstract

1. FIRMWARE FOR DATA MANAGEMENT AND DATA EXCHANGE, containing a command switch, an address switch, an exchange control block, an interrupt block, a issue register, a buffer register, an address bus, a data bus, and the information input of the output register, interrupt code input group and block mask code interrupts via the data bus are connected to the input-output of the peripheral device, and the first group of information inputs of the address switchboard forms the input of the sign of the direction of the exchange device, the group of information inputs A local loop forms the input for interrupting and exchanging the device, the second group of information inputs of the address switch is connected to the group of information outputs of the interrupt unit, the first output of the exchange control block is connected to the input of the attribute of the fixed address of the block of distorts and the permitting inputs of command switches and addresses whose groups of outputs the address bus is connected to the corresponding group of inputs of the lower bits of the buffer register, the inputs of the higher bits of which are connected to the group of outputs The masking bits of the interrupt block, the group of address inputs of which are connected via the address bus to the group of corresponding outputs of the address switches and commands, the output of the presence of interruptions of the interrupt block is connected to the interrupt input of the exchange control block whose input of the exchange is part of the group of inputs of the interrupt request and exchange device, the second code of the exchange control block is connected to the sample input of the address switch; the third output of the exchange control block is the output of the exchange resolution device Va, characterized in that, in order to increase the speed of data exchange and expand the scope of application by implementing buffering. translations of data and implementation of exchange algorithms using hardware and firmware tools, a permanent command storage unit, an online storage unit, a basic operational storage unit, a microprogram control unit, a synchronization unit, a control signal switch, an information switch, a counter are entered into the device. commands, address counter, sample counter, cycle counter, three blocks of trunk elements, central address bus and central data bus, the first information input d block firmware

Description

a lot of control forms the input of the logical conditions of the device, a group of information outputs of the information switchboard, a fixed storage block of commands, information inputs / outputs of a random access memory block, information inputs of command counters, addresses, samples and cycles, a second group of information inputs and a third information the input of the microprogram control unit through the data bus is connected to the inputs-outputs of the peripheral device; the first group of outputs of the microprogram control block forms the output to the external micro-operation of the device, the first and second groups of information inputs-outputs of the central operational storage unit, the first group of information inputs of the information switch and the group of outputs of the first block of main elements, the second group of information inputs of the information switch and the group of outputs of the second block connected to it trunk elements through a central data bus connected to the input-output of the central processor. group of address inputs of the central operational order the central unit address bus is connected to the group of outputs of the third block of trunk elements and to the group of address outputs of the central processor, the first input of the synchronization unit is the device start input, the first to fourth outputs of the synchronization block are connected to the first to fourth clock inputs of the block firmware control, the first and fourth outputs of the synchronization unit are connected respectively to the first and second synchronization inputs of the exchange control unit, the third and fourth The third outputs of the synchronization unit are connected respectively to the first and second inputs. The synchronization unit, the first and second groups of outputs of the microoperations of the microprogram control unit are connected respectively to the input group of the microoperations of the exchange control unit and the interrupt unit, the first sixth outputs of the third group of microoperations of the microprocessor control unit connected respectively to the control inputs of the recording of the issue register, the address counter, the command counter, the buffer register, the sample counter, s The cycle timer, the seventh - tenth outputs of the third group of micro-operations of the microprocess control block are connected respectively to the counting inputs of the address counter, command commands 4, the sample counter and the cycle counter, the eleventh-twentieth outputs of the third group of micro-operations control microprocessor outputs are connected to the second synchronization block input respectively , the input of the command switch sample, the control input of the permanent memory block of commands, the first, second control inputs of the operative first storage unit, the first, second control inputs of the information switchboard, the control inputs of the first, second, and third blocks of trunk elements; the twenty-first to twenty-fifth outputs of the third group of micro-operations outputs of the microprogram control unit are connected respectively to the first-fourth inputs of the control signals switch and the output of the requirement of direct access of the device, the outputs of the command counter and the address counter are connected respectively to the first and second information inputs and The command switch, the first output of the exchange control block is connected to the first control input of the microprogram control unit, the second control output of the microprogram control block is connected to the first control input of the exchange control block and the output end of the device exchange, the address inputs of the permanent command block and an operational storage unit are connected via the address bus to the outputs of the command and address switches, the group of outputs of the buffer register is connected to the third group of information inputs On the information switch, the counter output of the cyclone is connected to the second control input of the microprogram control unit, the output of the register is connected to the information inputs of the first and second block of main elements, the access and recording inputs of the device are connected respectively to the fifth and sixth inputs of the control switch, the first output of which is connected to the first control input of the central storage unit, the second control input of which is connected to the second and third switch codes of the control their signals, the output of the sampling counter, besides the low-order bit, is connected to the input of the third block of main elements, the lower bit of the address bus is connected to the fourth information input of the microprogram control unit and the third control input of the information switch, the exchange control block containing elements And, the OR element, the register, the enable trigger and the inhibit trigger are NAND elements, the first synchronization input of the block is connected to the first inputs of the first, second and third NAND elements, the second sync input is bl The first input is connected to the first input of the fourth NAND element and the register synchronization input, the first input of the group of micro-operations inputs of the block is connected to the first input of the OR element, the second input is connected to the first inputs of the first and second elements AND, the third and fourth inputs are connected to the second inputs of the first and The second NAND element, the first and second control inputs of the block are connected respectively to the second inputs of the fourth AND NAND element and the first AND element, the output of which is connected to the second input of the OR element, the information input of the block is connected to the second the second element's input, the output of which is connected to the third input of the element OR and the first information input of the register, the output of the element OR is connected to the second information input of the register, which is the first output of the block, the second output of the register is connected to the second input of the third element AND NAND and the second output of the exchange control unit, the outputs of the third and fourth elements AND-NOT are connected respectively to inverse single and zero inputs of the resolution tripper, the output of which is the third output of the unit, output The first and second elements of the NAND are connected respectively to inverse single and zero inputs of the inhibit trigger, the output of which is connected to the third input of the second element I. 01 2. The device according to claim 1, characterized in that the microprogramming unit contains a memory unit microinstructions, address register, first switch, second switch, address switch, logical conditions multiplexer, fourteen AND elements, two NAND elements, .OR-NOT element, NOT element, and micro-operations register, with the first information input of the block. firmware control is connected to the first information input of the logical conditions multiplexer, the first control bit of the first information input of the microprogram control unit is connected to the first input of the first NAND element, the second and third control bits of the first information input of the microprogram control unit are connected to the first and the second information inputs of the first switch, the quarter and five control bits of the first information input of the block micro. software control is connected respectively to the first and second information inputs of the second switch, the second information input of the firmware control module is connected to the first information input of the address switch, the output of which is connected to the information input of the address register, the third information and the first control inputs of the firmware control module are connected respectively to the second multi-information input. of the logical conditions plexor and the first input of the OR-NOT element, the second control input of the firmware control block is connected to the inverse input of the second IS-NOT element whose output is connected to the first input of the first AND element, the first synchronization input of the firmware control block is connected to the first inputs of the second and The third element I. the second synchronization input of the firmware control block is connected to the second input of the first element I, whose output is connected to the synchronization input of the address register, the third input b The synchronization of the firmware control block is connected to the first inputs of the fourth, fifth and sixth elements AND, the fourth synchronization input

the microprogram control unit is connected to the first inputs of the seventh fourteenth AND elements, with the second input of the first NAND element and the micro-operation register synchronization input, the first, second and third outputs of which are connected respectively to the first, second control outputs and the first group of micro-operation outputs of the microprocess control unit , the fourth output of the register of micro-operations is connected to the direct and inverse control inputs of the address switch, the first group of outputs of micro-operations of the microprogram block control unit and the HE element whose output is connected to the second group of micro-operations outputs of the microprocessor control unit, the fifth output of the micro-operations register is connected to the second input of the IPI-NEO element, the output of which is connected to the second input of the eighth And element, the sixth - ninth outputs of the micro-operations register are connected with the second group of micro-operations outputs of the microprogram control unit, the tenth output of the micro-operations register is connected with the second group of micro-operations outputs of the microprogram control unit and the second input the house of the sixth element And, the eleventh - the fifteenth outputs of the register of micro-operations are connected respectively to the second inputs of the second, seventh, ninth, tenth and third elements And, the sixteenth output of the register of micro-operations is connected to the third input of the eighth element And , the first output of the group of outputs of the register of micro-operations is connected to the second inputs of the fourth and fifth elements I, the second - the fifth outputs of the group of outputs of the register of the micro-operations are connected to Respectively with the second inputs of the eleventh - fourteenth elements And, the sixth and

the seventh outputs of the group of outputs of the register of micro-operations are connected respectively to the direct input of the second element AND-NOT and the third input of the first element AND-NOT, the eighth output of the group of outputs of the register of micro-operations is connected to the first and the control inputs of the first and second switches, the ninth output of the group of outputs of the register micro-operations are connected to the second control inputs of the first and second switches, the output of the register of the address is connected to the input of the microcommand memory block, the first and second outputs of which are connected to the first group of outputs microoperations of the microprocessor control unit, the second output of the microinstructions memory block is also connected to the first input of the microoperations register, the third to the sixth outputs of the microinstructions memory block are connected respectively to the second to fifth inputs of the microoperations register, the seventh and eighth outputs of the microcommands memory are connected respectively to the control and third information inputs of the logical conditions multiplexer, the output of the modified address bit of which is connected to the input of the modified address of the second address the second information input of the address switch; the ninth output of the microcommand memory block is connected to the input of the unmodifiable address bits of the second information input of the address switch; the fourth information input of the microprogram control unit is connected to the inverse and forward inputs of the fourth, fifth elements And, respectively, the seventeenth to twenty the fourth outputs of the register of micro-operations, the outputs of the second - the fourteenth elements Hj, the output of the first NAND element, the outputs of the first and second switches are connected to the third Rupp micro firmware control block outputs.

one

The invention relates to computing and can be used in the construction of peripheral

hierarchical computing system processors as control and communication devices.

A firmware interface device is known that contains a control unit, registers, a synchronization unit, a switch, a counter lj.

The disadvantage of this device is the limited functionality due to the fact that the device allows the exchange of information with only one source.

The closest to the proposed technical essence and the achieved result is a device for interfacing a digital computer with peripheral devices, containing a block of communication signal amplifiers with a digital computer, the input-output group of which is connected to the first group of input-output devices signals of communication with peripheral devices, a group of input-output of which is connected to the second group of input-output devices of the device, the decoder, the first and second outputs of which are Finished respectively with the first inputs of the exchange control unit and the shift register, the first and second switches, the interrupt unit, the even-ti forming unit, the first and second triggers, the first decoder input connected to the first output of the communication signal amplifier unit with the digital computer, the first the input and the second, third and fourth outputs of which are connected respectively to the first output and the second input of the exchange control unit 11 and the first inputs of the first and second triggers, the third input of the control unit about The first inputs of the first switch and interrupt issuing unit are connected to the first output of the communication signal amplifier unit with peripheral devices, the second output of which is connected to the second input of the first switch and the fourth input of the exchange control unit, the second output connected to the second input of the shift register, the first output of which is connected to the first input of a parity shaping unit, the output of which is connected to the first input of a block of communication signal amplifiers with peripheral devices, the third output of which is connected to the second input of the parity shaping unit and the fifth input of the block

exchange control, the second and third inputs - respectively with the third and fourth outputs of the exchange control block, the fourth output - with the third inputs of the parity shaping unit and the shift register, the fourth input, the fifth and sixth rows - with the output of the second trigger, the fourth input, respectively the shift register and the third input of the first switch, the fourth input of which is connected to the third output of the decoder, the fourth output connected to the second inputs of the first and second flip-flops, the output of the first flip-flop is connected to the second input of the interrupt issuer and the fifth input of the first switch, the output and the first and second inputs of the second switch are connected respectively to the second input of the decoder and the fifth input of the shift register, the second output of the shift register and the fifth decoder code, and the input-output with the outputs the first switch and interrupt block and the third input of the signal amplifier block with the digital computer 2

The disadvantages of this device are the low speed of data exchange and the narrow field of application of the device.

Low data exchange rate due to the following.

The actual exchange of data is preceded by the preparation phase of the exchange, i.e. Before each piece of data there is a control word defining the time of entry into the exchange (Tg,). After the end of the actual exchange, carried out during the time T, the initial state of the device is restored, which corresponds to the exit time of the exchange. formula

 T

Repeatedly implementing data exchange cycles for each data word requires additional overhead time associated with entering and exchanging exchange. Obviously, this significantly reduces the rate of exchange, especially when exchanging large amounts of data.

The narrow field of application of the device is due to the fact that it can only carry out the functions of direct data exchange between the central and peripheral processors. To implement the data processing control function, special technical means must be introduced into the device, but they are absent. This does not allow for the flexible redistribution of funds and resources of the system as a whole. The impossibility of realization with the help of a known device of complex control functions does not allow initiating a check of the functioning of the device, as well as performing the processing of distortions of various classes. The purpose of the invention is to increase the speed of data exchange and expand the field of application of the device by buffering the broadcast data and implementing the exchange algorithms using hardware-micro software. , The goal is achieved by the fact that the firmware for controlling and exchanging data contains a command switch, an address switch, an exchange control block, an interrupt unit, a register, a buffer register, addresses, a data bus, and the information input of the output register, a group of inputs the interrupt code and the mask code of the interrupt block via the data bus are connected to the input by the output of the peripheral device, and the first group of information inputs of the address switch forms the input of the sign of the device exchange direction, group The paired information inputs of the interrupt unit form the input of the interrupt and exchange request, the device; the second group of information inputs of the address switch is connected to the information output group of the interrupt unit; the first output of the exchange control unit is connected to the input of the attribute of the fixed address of the interrupt block and to the enable inputs of command switches and addresses whose output groups are connected to the corresponding group via the bus,. the inputs of the lower bits of the buffer register, the inputs of the high bits of which are connected to the group of outputs of the masking bits of the interrupt unit, the group of address inputs of which are connected via the address bus to the group of corresponding outputs of the COM 01 address mutators and commands, the output of the interrupt of the interrupt unit is connected to the input interrupt control unit of the exchange control, the input of which is included in the group of inputs of the interrupt request and device exchange, the second output of the exchange control control unit is connected to the sample input of the switch addresses, the third output of the exchange control block is the output of the resolution of the device exchange, a persistent command storage unit, an operational storage unit, a central operational storage unit, a firmware control unit, a synchronization unit, a control signal switch, an information switch, a command counter, a counter are entered addresses, a sample counter, a cycle counter, three blocks of trunk elements, a central address bus, and a central data bus, with the first information input of the microprogram unit pack This information forms the input of the logical conditions of the device, the group of information outputs of the information switch, the permanent memory block of commands, the information inputs / outputs of the operational memory block, the information inputs of command counters, addresses ,. samples and cycles, the second group of information inputs and the third information input of the microprogram control unit are connected to the peripheral device via the data bus; the first group of outputs of the microprogram block control forms the output of the device's external microoperations, the first and second group of information inputs and outputs of the central operational storage unit , the first group of information inputs of the information switch and the group of outputs of the first block of trunk elements connected to it The second group of information inputs of the information switch and the group of codes of the second block of trunk elements connected with it are connected via the central data bus through the central data processor through the central data bus, the group of address inputs of the central operational memory block is connected via a digital bus of the trunk of the trunk elements and with a group of address outputs of the central processor, the first input of the synchronization block is the start input of the device, the first - fourth outputs of the sync block connected to the first or fourth synchronization inputs of the microprogram control unit, the first and fourth outputs of the synchronization block are connected respectively to the first and second synchronization inputs of the exchange control unit, the third and fourth outputs of the synchronization unit 1 and connected to the first and second synchronization inputs of the interrupt unit, the first and second groups of micro-operations of the microprocessor control unit are connected respectively to the group of micro-operations inputs of the control unit about The first and sixth outputs of the third group of micro-operations outputs of the microprocess control unit are connected to the control inputs of the register register, address counter, command counter, buffer register, sample counter, cycle counter, seventh-tenth outputs of the third group of microprogram output microprocessor outputs, respectively. Controls are connected respectively to the counting inputs of the address counter, command counter, sample counter and cycle counter, the eleventh twentieth outputs of the third group. The outputs of the micro-operations of the microprogram control unit are connected respectively to the second input of the synchronization unit, the sample input of the command switch, the control input of the permanent memory block of commands, the first, second control inputs of the random access memory, the first, second control inputs of the information switch, the control the inputs of the first, second and third blocks of trunk elements, the twenty-first to the twenty-fifth outputs of the third group of outputs of micro-operations of the microprogram block The connectors are connected respectively to the first to fourth inputs of the switch of control signals and the output of the device’s direct access requirement, the outputs of the command counter and the address counter are connected to the first and second command inputs, the first output of the exchange control block is connected to the first the control input of the firmware control block, the second control output of the firmware control block is connected to the first control input of the exchange control block and the output the end of the exchange device. Va, address inputs of a persistent memory block of commands and operative memory of the block are connected to the outputs of the command and address switches, the group of outputs of the buffer register is connected to the third group of information inputs of the information switch, the output of the cycle counter is connected to the second control input of the microprogram control block , the register register code is connected to the information inputs of the first and second block of main elements; the access and record inputs of the device are connected according to but with the fifth and sixth inputs of the control signal switch, the first output of which is connected to the first control input of the central storage unit, the second control input of which is connected to the second and third outputs of the control switch signal, the output of the sample counter, except for the lower bit, connected to the input of the third block of trunk elements, the low order bit of the address bus is connected to the fourth information input of the firmware control block and to the third control block. common input switch information. The exchange control block contains the first and second elements AND, the OR element, the register, the first - the fourth AND-NOT elements, the enable trigger and the inhibit trigger; the first synchronization input of the exchange control block is connected to the first inputs of the first, second and third AND-NOT elements, the second synchronization input of the exchange control unit is connected to the first input of the fourth NAND element and the register synchronization input, the first input of the group of micro-operations inputs of the exchange control unit is connected to the first input of the OR element, the second input of the groups The inputs of the microoperations of the exchange control unit C (shared with the first inputs of the first and second elements AND, the third and fourth inputs of the group of inputs of the microoperations of the exchange control unit are connected respectively with the second inputs of the first and second elements of AND-NOT, the first and second control inputs of the unit exchange control is connected respectively to the second inputs of the fourth element AND-NOT and the first element AND, the output of which is connected to the second input of the OR element, the information input of the exchange control unit is connected to the second input v And, the output of which is connected to the third input of the OR element and the first information input of the register, the output of the OR element is connected to the second information input of the register, the first output of which is the first output of the exchange control block, the second output of the register is connected to the second input The third NAND element and the second output of the exchange control block, the third and fourth NAND elements, are connected to inverse one and zero inputs of the resolution trigger, the output of which is the third output, respectively. the exchange control locus, the outputs of the first and second elements AND-NOT are connected to the inverse unit one and zero inputs of the inhibit trigger, the output of which is connected to the third input of the second element AND, In addition, the microprogram control block contains the microinstructions memory block, register addresses, first {1 switch, second switch, address switch, logical conditions multiplexer, fourteen AND elements, two AND-NOT elements, CLI-NOT elements, NOT elements and micro-operations register, the first information input of the mic the program control is connected to the first information input of the logic multiplexer; the first control bit of the first information input of the microprogram control unit is connected to the first input of the first NAND element, the second and third control bits of the first information input of the microprogram control unit are connected to the first one and the second information inputs of the first switch, the fourth and fifth control 110 bits of the first information input of the microprogram control unit They are connected respectively to the first and second information inputs of the second switch, the second information input of the microprogram control unit is connected to the first information input of the address switch, the output of which is connected to the information input of the address register, the third information and first control inputs of the microprogram control unit are connected respectively to the second information the input of the multiplexer logical conditions and the first input of the element OR NOT, the second control input of the microprobe unit frame control is connected to the inverse input of the second element IS-NOT, the output of which is connected to the first input of the first element AND, the first synchronization input of the microprogram control unit is connected to the first inputs of the second and third elements And the second synchronization input of the microprogram control unit is connected to the second input of the first element And, the output of which is connected to the synchronization input of the address register, the third synchronization input of the firmware control block is connected to the first inputs of the fourth, fifth and sixth th element, and a fourth clock input microprogram control unit connected to the first vhoda-. mi of the seventh - fourteenth elements AND, with the second input of the first element AND-NOT and the synchronization input of the register of micro-operations, the first, second and third outputs of which are connected respectively with the first, second control outputs and the first group of outputs of the micro-operations of the microprogram control unit, the fourth output of the register micro-operations are connected to the direct and inverse control inputs of the address switch, the first group of micro-operations outputs of the firmware control block and the input of the HE element whose output is connected with the second group of micro-operation outputs of the microprogram control unit, the fifth output of the micro-operations register is connected to the second input of the OR-NOT element, the output of which is connected to the second input of the eighth And element, the sixth and ninth outputs of the micro-operations register are connected to the second group of micro-operations output of the microprogram unit, many controls, the tenth output of the register of micro-operations is connected to the second group of outputs of micro-operations of the microprocessor control unit and the second input of the sixth element I, the eleventh - the fifteenth output The register of micro-operations is connected to the second inputs of the second, seventh, 1, eu, tenth, and third elements And, the sixteenth output of the register of micro-operations is connected to the third input of the eighth element And and the third group of outputs of the micro-operation unit of the micro-operation register connected to the second inputs of the fourth and fifth elements, And, the second - fifth outputs of the group of outputs of the register of micro-operations are connected respectively to the second inputs of the eleventh to fourteen And the sixth and seventh outputs of the micro-operations register output group are connected respectively to the direct input of the second AND-NOT element and the third input of the first AND-NE element, the eighth output of the micro-operations register output group is connected to the first control inputs of the first and second switches, the ninth output of the group of outputs of the register of micro operations is connected to the second control inputs of the first and second switches, the code of the address register is connected to the input of the microcommand memory block, the first and second outputs of which are connected They are connected to the first input of the register of microoperations, and the third to the sixth outputs of the microinstruction memory are connected to the second to fifth inputs of the register of microoperations, the seventh and the eighth the outputs of the microcommand memory block are connected respectively to the control and the third information inputs of the multiplex logical conditions, the output of the modified address bit of which is connected to the mod the address bit of the second information input of the address switch, the ninth 112th output of the microcommand memory block is connected to the input of the unmodifiable address bits of the second information input of the address switch, the fourth information input of the firmware control block is connected to the inverse and direct inputs of the fourth, fifth elements And, respectively, the seventeenth - twenty-fourth outputs of the register of micro-operations, the outputs of the second - fourteenth elements AND, the output of the first AND-NOT element, the outputs of the first and second terminals mutators connected to the third group of micro firmware control block outputs. The essence of the invention is to control the speed of data exchange and expand the field of application of the device based on the buffering of broadcast information in the RAM, the implementation of processing algorithms for heavy (slow) and fast interruptions using special hardware-firmware means, the ability to initialize direct group communication and organization checks the operation of both the peripheral and the central processor. The invention is implemented by introducing the following new elements and SBN3 to it. The introduction of a permanent memory block (FBB) of commands, a counter of commands and the relations caused by them allows you to store commands and constants of the main program, as well as addressing the memory blocks of the PZB when implementing the main program. The introduction of the central data bus, the central operational storage unit, the sample counter and the cycle counter and their associated communications allows the central processor data to be stored and directly access the data stored in the central operational storage unit, followed by recording to the operational storage unit. block. The introduction of an on-line storage unit (OZB), an address counter, and the relations resulting from them allows data to be stored during operation of the operation unit, as well as

to address the memory cells OZB.

The introduction of the firmware control unit and the relations determined by it allows the data processing control functions to be implemented by the operation unit.

The introduction of the synchronization unit, the control signal switch, the information switch, the first, second, and third block of trunk elements and the connections resulting from them allows the device to be controlled and synchronized with four clock sequences.

FIG. 1 is a functional diagram of the proposed Firmware device for control and data exchange; FIG. 2 is a functional block diagram of a firmware control unit (MCU); in fig. 3 - functional interrupt block circuit; in fig. 4 - functional block diagram of the exchange control unit (BOO); in fig. 5 - functional block diagram; in fig. 6 is a functional diagram of a control signal switch; in fig. 7 - functional command switch; in fig. 8 is a functional diagram of the address switch; in fig. 9 - functional information switch diagram.

The firmware for controlling and exchanging data14I contains the FBT 1, the FFB 2, the central operative storage unit (CSC) 3, the BMU 4, the interrupt block 5, the CPUU 6, the synchronization block 7, the control switch 8, the command switch 9, the address switch 10 , information switch 11, command counter 12, address counter 13, sampling counter 14, cycle counter 15, output register 16, buffer register 17 first block 18 of trunk elements, second block 19 of trunk elements, third block 20 of trunk elements, data bus 21, , bus 22 addresses, prices -sectoral data bus 23, a central bus 24, address input 25 of the starter, the inlet 26 guiding feature exchange apparatus input 27 of logical conditions devices, input device 28, address inputs 29, the group interrupt requirements and sharing device.

input 30 requests exchanges group 29 inputs requests interrupt and exchange, device access input 31, device record input 32, device input output 33, device input output group 34, device output 35 external output, device exchange output output 36, exchange resolution output 37 device output 38 requires direct access to the device.

FIG. 1 also shows the output of 39.1 of the first half-word of TSOZB 3, the input-output 39.2 of the second half-word

5 CSCB 3, the first group of 40 outputs of microoperations of BMU 4, the second group of 41 outputs of microoperations of BMU 4, the third group of 42 outputs of microoperations of BMU 4, containing output 42.1

0 end operation microoperations, output 42.2 of microoperations of recording information management in issuance register 16, output 42.3 of microoperations of permitting counter code 12 commands, output 42.4 of microoperations promoting content of counter 13. of advancing the contents of the counter 12 commands, output 42.7 of the micro-operation of managing the recording of information of the counter 12 commands, output 42.8 of the micro-operation of referring to the PZB 1, output 5 progress 42.9 of the micro-operation of the recording sign in OZB 2 , output 42.10 of the microoperation of accessing OZB 2, output 42.11

information management micro-operations in the buffer register 17,

0. output 42.12 of a three-bit micro-operation control of information switch 11, output 42.13 of micro-operation of access to data bus 21, output 42.14 of micro-operation of control of first trunk unit 18 of main elements, output 42.15 of micro-operation of control of second block 19 of main elements, output of 42.16 micro-operations of CBS .3, output 42.17 microoperation of the sign of recording the first half-word in CSCB 3, output 42.18 of the micro-operation of control of the switch 8 control signals, output 42.19 of the micro-operation of the characteristic

3 records of the second half-word in POSE 3, output 42.20 of the micro operation of advancing the contents of the counter 14 sample, output 42.21 of the micro operation of recording information of the counter 14 of the sample, output 42.22 of the micro operation of advancing the contents of the counter 15 cycles, exit 42.23 of the micro operation of recording the information of the counter of 15 cycles , the output 42.24 of the microcontrol management of the third block 20 of trunk elements, the output 43 of the presence of interruptions of the block 5 interrupts, the output 44 of the code of the fixed addresses of the block 5 interrupts, the output 45 of the masking bits of the block 5 interrupts first, the second output 46 of the CPU 6, the first output 47 of the CPU 6, the first fourth outputs 48.1 - 48.4 of the synchronization unit 7, the first 49, the second 50, the third 51 outputs of the control switch 8, the output 52 of the command counter 12, the output 53 of the address counter 13 , the output 54 of the counter 15 cycles, the output 55 of the buffer register 17, the output 56 of the first block 18 of main elements, the output 57 of the second block 19 of main elements, the second information input 58 of the BMU 4, the third information input 59 of the BMU 4, the input 60 of the interrupt code and the input 61 mask code block 5 interrupt, the second control input 62 block 5 interrupts, junior bit 63 bus 22 addresses. The device start input 25 is the first input of the synchronization unit 7, the first to fourth 48.1 48.4 outputs of which are connected respectively to the first to fourth synchronization inputs of the BMU 4, the first 48. and the fourth 48.4 outputs of the synchronization unit 7 are connected to the first 48.1 and second 48.4 inputs respectively sync CID 6, third 48.3 and fourth 48.4 outputs of synchronization unit 7 are connected respectively to the first 48.3 and second 48.4 synchronization inputs of interrupt block 5, the input 26 of the device exchange direction feature is the first information input the home of the address switch 10, the input 27 of the logical conditions of the device is the first information input of the BMU 4, the first control output of which is the output 35 of the external microoperations of the device, the first 40 and the second 41 groups of the outputs of the microoperations of the BMU 4 are connected respectively to the group of inputs of the microoperations of the CCU 6 and block 5 interruptions, the first - the sixth outputs of the third group of 42 outputs of microoperations of the BMU 4 are connected respectively: output 42.2 to the control input of the output register 16, output 42.5 to the input of the address 13, output 42.7 to the input counter 12 commands, code 42.11 - with input of buffer register 17, output 42.21 - with sample counter 14, output 42.23 - with 15 counter cycles, seventh - tenth outputs of the third group 42 outputs of microoperations of the BMU 4 are connected respectively: output 42.4 - with counting inputs of the counter 13 addresses, output 42.6 - with the input of the counter 12 commands, output 42.20 - with the input of the counter 14 of the sample and output 42.22 - with the input of the counter 15 cycles, the eleventh - twentieth outputs of the third group 42 and codes of micro-operations of the BMU 4 are connected respectively: output 42.1 - with the second input of block 7 sync onization, output 42.3 — with the control input of the switch 9 commands, output 42.8 — with the control input of the PZB 1, outputs 42.9, 42.10 — with the first and second control inputs of OZE 2, outputs 42.12 and 42.13 — with the first and second control inputs switch 11 of information, output 42.14 with control input of the first 18, output 42.15 with the control input of the second 19 and output 42.24 with the control input of the third 20 blocks of trunk elements, twenty-first and twenty-fifth outputs 42 .. 16 42 .19 the third group of 42 outputs of microoperations BMU 4 are connected respectively with the first - fourth input The control signal switch 8 and the output 38 of the device direct access demand, the outputs 52 and 53 of the command counter 12 and the address counter 13 are connected to the first and second information inputs of the command switch 9, the first output 47 of the CPU 6, respectively. interrupts, the enable input of the address switch 10, the first control input of the BMU 4 and the enable input of the command switch 9, the second control output of the BMU 4 is connected to the first control input of the CPUU 6 and the output 36 of the exchange end device, a group of inputs 29 interrupt requests and device exchange is connected to the first information input block L of interrupts, the first information output 44 of which is connected to the second information input of the address switch 10, input 30 exchanges requirements of a group of inputs 29 interrupt requests and device exchange are connected to the information input of the CPU 6, the second 46 and third outputs of which are connected respectively to the sample input of the Switch 10 address and the output 37 of the device exchange, the address bus 22 is connected to the address input MF 1 and OZB 2, whose input-output with the data bus 21, the output of FB 1 is connected to the data bus 21, the pin 22 of the address is connected to the address inputs 62 of the interrupt block 5 and to the lower bits of the information input of the buffer register 17, output 55 of which connected to the third information input of the information switch 11, the upper bits of the information input of the buffer register 17 are connected to the output group 43 of the masking bits of the interrupt block 5, the output 43 of whose presence is connected to the input, the interrupt of the CPU 21, the data bus 21 is connected to inf The input inputs of the command counter 12, the address counter 13, the output register 16, the sample counter 14 and the 15 cycle counter, the output 54 of which is connected to the second control input .EMU 4, the 21 dunng bus 21 are connected to the second 58 and the third 59 ITU 4 information inputs, input 60 of the interrupt code and input 61 of the mask code of the interrupt block 5, the output of register 16 of the input is connected to the information inputs of the first 18 and second 19 blocks of trunk elements, the outputs 56 and 57 of which are connected respectively to the first and second information inputs of the switch 11 Formations and the central data bus 23, the first 39.1 and the second 39.2 inputs-outputs of the DSP 3 are connected to the central data bus 23, the inversion inputs 31 and the device records 32 are connected to the fifth and sixth inputs respectively: the control signal switch 8, the first output 49 which is connected to the first control input of CSCB 3, the second control input of which is connected to the second 50 and third 51 outputs of the switch 8 of control signals, the output of the counter 118 118 of the sample, except for the lower bit, through the third block 20 of main elements and the central bus The 24 addresses are connected to the address input of the central operational storage unit 3, the output of the information switch 11 is connected to the data bus 21, the device address input 28 is connected to the address central bus 24, the low-rank 63 of the address bus 22 is connected to the fourth information input of the BMU 4 and the third control input of information switch 11. BMU 4 (Fig. 2) contains a block of 64 memory of micro-commands, address register 65, micro-operation register 66, address switch 67, first 68 and second 69 switches, multiplexer 70 logical conditions, fourth 71, fifth five, eleventh 73, twelfth 74 , - the thirteenth 75, fourteenth 76, second 77, sixth 78, seventh 79, eighth 80, ninth 81, tenth 82, third 83 and first .84 elements AND, second 85 and first 86 elements. AND-NOT, element OR NO 87, item NO 88. FIG. 2 also marked the first exit of micro-operation 89, the third 90, the fourth 91 ,. the second 92, fifth 93 and sixth 94 outputs, the seventh output 95 of the logic conditions code, the eighth output 96 of the modifiable address bit, the ninth output 97 of the unmodifiable digit of the address of the microcommand memory 64, the output 98.1 of the HE 88 element, the sixth - ten inputs 98.2 - 98.6 register 66 micro-operations, respectively, the third 99.1 and fourth 99.2 outputs of register 66 micro-operations, output 100.1 (42.11) of the micro-operation of recording information management of the buffer register 17, output 100.2 (42.9) of the micro-operation of recording information in OZB 2 , output 100.3 (42.7) control microoperations Apis information counter 12 commands output 100.4 (42.3) 66 microoperation register microoperation resolution micro advance content code counter 12 vschachi, yield 100.5 (42.6) of the program counter 12 instruction code, yield 100.6 (42.5) a control information recording micro-operation to the counter. 13 address, output 100.7 (42.4) of the microoption promotion of the contents of the counter code 13 address, output 100.8 (42.2) of the register management write 16 operations, output 100. (42.1) end operation microoperations, output 100.10 (42.8) of the access operation microprocessor 1, exit 100.11 (42.10) of the microoperation of accessing HSE 2, output 100.12 (42.17) of the micro operation of the record of the first half word in CSRP 3, output 100.13 (42.19) of the microoperation of the sign of the second half word in CSFR 3, output 100.14 (42.20) Micro operations of promoting the contents of the counter 14 samples, output 100.15 (42.21) micro control operations for writing information of the sample counter 14, output 100. (42.22) microoperations promoting the contents of the counter 15 cycles, output 100.17 (42.23) microoperations to manage information recording of the counter 15 cycles, output 101.1 microoperations of the register 66 microoperations controlling the first block 18 of the main elements (output 42.14 of the BMU 4 ), the output 101.2 of the micro-operation of the register 66 of the micro-operations of control of the second block 19 of main elements (output 42.15 of the BMU 4), the output of the 101.3 micro-operations of the register, 66 micro-operations of the control of the third block of the main elements 20 (output of 42.24 of the BMU 4), micro-operation output 101.4 of micro-operation register 66 for accessing CSRB 3 (output 42. BMU 4), micro-operation output 101.5 of micro-operation register 66 of micro-operations of control switch 8 control signals (output 4.18 of BMU 4), output 101.6 of micro-operation of micro-register register 66 of direct access (output 38 devices), output 101.7 of the micro-operation of the register 66 of the micro-operations with information by the information switch 11 (output 42.13 of the BMU 4), output 101.8 of the three-bit micro-operation of the control of the information switch J1 (you, move 42.12 of the BMU 4), group 102 of the micro-operations of the regis Micro operation trap 66, containing first first and fifth control bits, 103.1–103.5 of input 27 of the BMU 4, respectively. The first information input 27 of the BMU 4 is connected to the first information input of the logical conditions multiplexer, the first control bit 103-1 of the first information input 27 of the BMU 4 is connected to the first input of the first element AND-HE 86, the second 103.2 and the third 103.3 control bits the first information input 27 of the BMU 4 are connected respectively to the first and second information inputs of the first switch 6B, the fourth 103.4 and the fifth 103.5 control bits of the first information input 27 of the BMU 4 are connected respectively to the first and second information data inputs of the second switch 69, the second information input 58 of the BMU 4 is connected to the first information input of the address switch 67. the output of which is connected to the information input of the address register 65, the third information 59 and the first control 47 inputs of the BMU 4 are connected respectively to the second information input of the logical conditions multiplexer 70 and the first input of the ILINE 87 element, the second control input 54 of the BMU 4 is connected to the inverse input of the second element YN-HE 85, the output of which is connected to the first input of the first element I 84, the first input 48.1 of the synchronization of the BMU 4 is connected to the first inputs of the second 77 and the third 83 of the element I, the second input 48.2 of the synchronization of the BMU 4 is connected to the second input of the first element And 84, the output of which is connected to the synchronization input of the register of the address 65, the third synchronization input 48.3 of the BMU 4 is connected to the first inputs of the fourth 71, the second 72 and the sixth 78 And elements, the fourth synchronization input 48.4 of the BMU 4 is connected to the first inputs of the seventh - the four-element elements 79-82, 73-76, with the second input of the first element AND-HE 86 and the synchronization input of the register 66 micro-operations, the first, second and third 99.1 outputs of which are connected respectively to the first 35 and second 36 control outputs and the first group of 4 About the outputs of microoperations BMU 4, the fourth output 99.2 of micro-operations register 66 is connected to the direct and inverse control inputs of address switch 67, the first group 40 of codes of microoperations BMU 4 and the input element HE 88, output 98.1 of which is connected to the second group 41 outputs of microoperations BMU 4 , the fifth output of the register of micro-operations is connected to the second input of the element OR-NE 87, the output of which is connected to the second input of the eighth element I 80, the sixth-ninth outputs 98.2 - 98.5 of the micro-operations register 66 are connected to the second group A1 of the outputs of micro-operations E At 4, the tenth output 98.6 of the register 66 of the micro-operations is connected to the second group of 41 outputs of the microoperations BMU 4 and the second input of the sixth element I 78, the eleventh - the fifteenth outputs of the register 66 of the micro-operations are connected respectively to the second inputs of the second 77, seventh 79, ninth 81, the tenth 82 and the third 83 And elements, the sixteenth output 100.4 of the micro-operation register 66 is connected to the third input of the eighth element I 80 and the third group of 42 micro-operations of the BMU 4 micro-operations, the first output of the group 102 of the micro-operations register 66 is connected to the second inputs the fourth 71 and fifth 72 elements And, the second - the fifth outputs 1-02.4-102.7 of the group 102 of the outputs of the register 66 micro-operations are connected respectively with the second inputs of the eleventh - fourteenth elements And 73-76, the sixth 102.8 and the seventh 102.3 outputs of the group 102 outputs micro-operation register 66 is connected respectively to the direct input of the second element AND-NE 85 and the third input of the first element AND-NE 86, the eighth output 102.2 of the group 102 of the outputs of the micro-operation register 66 is connected to the first control inputs of the first 68 and second 69 switches, the ninth output 102.1 groups 1 02 outputs of micro-operation register 66 are connected to the second control inputs of the first 68 and second 69 switches, register address 65 is connected to the input of microcommand memory 64, the first 89 and second 92 outputs of which are connected to the first group 40 of micro-operations BMU 4, the second output 92 of micro-command memory block 64 is also connected to the first input of register 66 micro-operations, the third and sixth subdirectores 90, 91, 93, 94 of micro-command memory block 64 are connected to the second-fifth input of micro-register register 66, the seventh 95 and eighth 96 output microcommand memory block 64 is connected to the control and third information inputs of the multiplexer 70 logical conditions, respectively, the output of the modified address bit of which is connected to the input of the modified address bit of the second information input of the switch 67 address, the ninth output 97 of the memory 64 block 64 with the input of the non-modifiable bits of the address of the second information input of the switch 67 of the address, the fourth information input 63 of the BMU 4 is connected to the inverse and direct inputs of the fourth 71 and the fifth 72 And, respectively, the seventeenth 101.1 twenty-fourth 101.8 outputs of the register of 66 micro-operations, outputs 5, respectively 100.1, 100 „8, 100.12, 100.13, 100.2, 100.3, 100.5-100.7, 100.14-100.17 of the second - the fourteenth elements And 77,83,71,72, 78-82, 73-76, output 100.9 of the first element of the AND-HE 86, outputs 100.10 and 100.11 of the first 68 and second 69 switches are connected to the third group of 42 outputs of the microoperations of the BMU 4.

Interrupt block 5 (Fig. 3) contains interrupt register 104, mask register 105, fixed address register 106, decoder 107, first switch 108, second switch 109, first element 110, second element 1111, third element 112 the fourth element is AND 113, the fifth element is AND 114, the first is 115, the second is 116, the sixth is 117, the fifth is 118, the fourth is 119, the third is 120 NAND, the element is NOT 121.

FIG. 3 also shows the first 122, the second 123, the third 124 outputs of the mask register 105, the first 125, the second 126, the third 127, the fourth 128 0, the outputs of the fixed address register 1P6, the outputs 129 and 130 of the fourth 113 and the fifth 114 respectively And, input 131.1 of microoperation of group 41 of inputs of microoperations, 5 corresponding to output 98.1 (Fig. 2), input 131.2 of microoperation of group 41 of inputs of microoperations, corresponding to output 98.6 (Fig. 2), inputs 131.3 - 131.6 of microoperations of group 41 of inputs of microoperations, corresponding to outputs 98 -. 2 - 98.5 (Fig. 2). The interrupt request inputs of a group of 29 interrupt request inputs and exchange of interrupt block 5 are connected to the inverse inputs of the unit into the triggers register register 104, the first output of the interrupt register 104 is connected to the input terminal HE 121, the output of which is connected to the first inputs of the first 115, the second 116 , the third 120 elements AND-NOT and the first element AND 110, the second output of the register 104 interruption is connected to the second input of the first element AND-NOT 115, the output of which is connected to the second input of the first element AND 110, the second input of the second element That AND-NOT 116, the second input of the third element AND-NOT 120 and with the first input of the fourth element AND-NOT 119, the third output of the interrupt register 104 is connected to the third input of the second element AND-NE 116, the output of which is connected to the first inputs of the fifth 118 and the sixth 117 AND-NOT cells and with the third input is rubbing its element AND-NO 120, the output of the first element AND 110 is connected to the second input of the sixth element AND-NE 117, the output of which is connected to the fourth input of the third element AND-NOT 120, the second input of the fourth element AND-NOT 119, the second input of the fifth element AND-NOT 118, the fourth output The interrupt register 104 is connected to the third input of the NAND 117 element, the input 47 of the fixed address block attribute 5 of the interrupts is connected to the first input of the second And element 1 whose output is connected to the first input of the fixed address register 106, the outputs of the fifth, fourth and third And- elements NOT 118-120 are connected respectively to the second Fourth inputs of the register 106 of the fixed address, the output 125 of the register 106 of the fixed address is connected to the first input of the third element I T12, the output of which is connected to the synchronization input of the decoder 107, The first synchronization input 48.3 of the interrupt block 5 is connected to the second input of the third element 112, the first and second inputs of the first 108 and second 109 switches, the outputs of which are connected respectively to the synchronization inputs of the interrupt register 104 and the mask register 105 unit 5 interrupts are connected to the synchronization input of the register 106 of a fixed address, the foreign outputs of the decoder 107 are connected to the inverse inputs of zeroing triggers of the interrupt register 104, the second output 126 of the register 1 1 of a fixed address connected to the first input of the decoder 107 and the first input of the fourth And 113 element, the third output 127 of the fixed address register 106 is connected to the second input of the decoder 107 and the first input of the first And 114 element, the fourth output 128 of the fixed address register 106 is connected to the interrupt 43 outputs and 44 codes of fixed interrupted addresses of the block 5. interruptions, inputs -131.3 and 131.4 of micro-operations for recording information into register 104 of group 41 of the inputs of micro-operations are connected respectively with the third and fourth inputs of the first switch 108, inputs 1 31.5 and 131.6 micro-operations for recording information into the mask register 105 of a group of 41 inputs of micro-operations are connected respectively to the third and fourth inputs of the second switch 109, the corresponding bits of the group of address inputs 62 of the interrupt block 5 are connected to the fifth inputs of the first 108 and second 109 switches, an input 61 of the mask code of the interrupt unit 5 is connected to the information input of the register 105 of the mask, the first output 122 of which is connected to the third input of the first AND-115 element 115, the second 123 and the third 124 outputs of the mask register 105 are connected respectively with the fourth inputs of the second element INE 116 and the sixth element AND-NOT 117, besides the outputs 122-124 of the mask register 105 form the output 45 of the masking bits of the interrupt block 5, the input 131.2 of the micro-operation sign of recording information in the OZB 2 of the group 41 of the inputs of the micro-operations are connected to the second input of the second element I 111 and connected to the output 44 of the code of the fixed address of block 5. The input 131.1 of the inverse value of the microoperation of the end of the command of the group of 41 inputs of the microoperations is connected to the second inputs of the fourth 113 and the first 114 elements And, the outputs 129 and 130 of which x is connected to the 44 kbda output of a fixed address, the interrupt code input 60, the interrupt block 5 is connected to the information input of the interrupt register 104. The CPUBU 6 (FIG. 4) contains the register 132, the resolution trigger 133 and the inhibit trigger 134, the second element AND 135 and the first element AND 136, the third 137, the fourth 138, the second 13 and the first 140 AND elements, NOT the element OR U1. FIG. 4 also denotes the first 142-1, the second 142.2, the fourth 142.3, and the third 142.4 inputs of a group of 40 inputs of micro-operations BOOS 6. The first input 48.1 of synchronization BOO 6 is connected to the first inputs of the first 140, the second 139 and the third 137 NAND elements, the second input 48.4 synchronization of the CPUU 6 is connected to the first input of the fourth element of the INE 138 and the synchronization input of the register is ipa 132, the first input 142.1 of the group TO the inputs of microoperations of the CPUU 6 is connected to the first input of the element OR 141, the second input 142.2 of the group 40 of the inputs of microoperations of the CPUU 6 is connected to the first inputs the first 136 and the second 135 elements And the third 142.4 and the fourth 142.3 inputs of a group of 40 inputs of microoperations BOO 6 are connected respectively to the second inputs of the first 140 and second 139 elements AND-NOT, the first 36 and second 43 control inputs of the BOO 6 are connected respectively to the second inputs of the fourth element AND -NE 138 and the first element AND 136, the output of which is connected to the second input of the element OR 141, information input 30 of the CPU 6 is connected to the second input of the second element AND 135, the output of which is connected to the third input of the element OR 141 and the first input of the register 132, the output of the element OR 141 is connected to T. The red input of the register 132, the first output of which is the first output 47 of the CPUU 6, the second output of the register 132 is connected to the second input of the third element AND-HE 137 and the BTO-output 46 of the CPUU 6, the outputs of the third and fourth 138 elements AND-NOT are connected respectively, with the inverse unit and zero inputs of the trigger 133, the output of which is connected to the third output 37 of the CPU 7. The outputs of the first 140 and second 139 I-NOT elements are connected respectively to the inverse unit and zero inputs of the inhibit trigger 134, the output of which is connected to the third input of the second th AND gate 135. The synchronization unit 7 (Figure 5) comprises a clock generator 143 and the trigger 144 is started. Flepsbrft input 25 of the synchronization unit 7 is connected to the single input of the trigger 144, the single output of which is connected to the control input of the generator 143 clock pulses. The second input 42.1 of the 7 cpronization unit 7 is connected to the zero input of the trigger 144. The first fourth outputs of the generator 143 clock pulses are connected respectively to the first and fourth outputs 48.1-48.4 of the synchronization unit 7. The switchboard 8 of the control signals (FIG. B) contains the first 145, the second 146 and the third 147 main elements, the resistor 148, the first 149, the second 150 and the third 151 bus. B; 1od 42.16 of the call to the CSCB 3 of the switch 8, the control signal is connected to the information input of the first trunk element 145, the output of which is connected via a resistor 148 to the power supply and the first bus 149, the input 42.17 of the write attribute of the first half-word and the input 42.19 of the write attribute of the second half-word 1b The CSCB 3 of the switch 8 of control signals is connected to the information inputs of the second 146 and the third 147 main elements, respectively, the outputs of which are connected respectively to the second 150 and the third 151 buses, the input 42.18 of the comm control The control signal terminal 8 is connected to the control inputs of the first 145, second 146 and third 147 main elements, the input 31 of the switch of the control switch 8 is connected to the first bus 149, the output of which is the first output 49 of the switch 8 of the control signals, input 32 the control switch records 8 are connected to the second 150 and third 151 buses, the outputs of which are the second 50 and third 31 outputs of the control signals switch B, respectively. The switch 9 commands (Fig. 7) contains the switch 152, block 153 trunk elements and the element 154. The first 52 and second 53 information inputs of the switch 9 commands are connected respectively with the first and second information inputs of the switch 152, the output of which is connected to the information input of the block 153 trunk elements, the control input 42.3 of the cog-mutator 9 commands connected to the direct and inverse inputs of the switch 152, the input 47 resolution of the switch 9 commands connected to the input element HE 154, the output of which is connected to the control input block 153 trunk elements, the output of which is the output of the switch 9 commands. The switch 10 addresses (Fig. 8) contains the Switch 155, block 156 of the main elements, the generator 157 zero. The resolution input 47 of the address switch 10 is connected to the control input of the main elements block 156, the output of which is the output of the address switch 10, the first 26 and second 44 information inputs of the address switch 10 are connected to the low-order bits of the first and second information inputs of the switch 155 , the output of the generator 157 zero is connected to the inputs of the higher bits of the first and second information inputs of the switch 155, the input 46 of the selection of the switch 10 of the address is connected to the direct and inverse inputs of the switch 155, you the course of which is connected to the information input of the block 156 main elements. The information switch 11 (FIG. 9) contains a multiplexer 158, a block 159 of trunk elements and a switch 160. The first 56, second 57 and third 55 information inputs of the information switch 11 are connected to the first, second and third information multiplex 158, respectively. First bit the first three bit control input 42.12 of information switch 11 is connected to the first control input of multiplexer 158, the output of which is connected to the information input of the main elements block 1, the output of which is tator 1 information. The second bit of the first three-bit control input 42.12 of information switch 11 is connected to the first information input of switch 160, which is connected to the second control input of multiplexer 158. The third bit of the first three-row control information input 42.12 of information switch 11 is connected direct and inverse control inputs of the switch 160. The second control 1 128 input 42.13 of the information switch 11 is connected to the control input of the main elements block 159, and the third control input of the information switch 11 connected to the second information input of the switch 160. Consider the purpose of the blocks and elements of this firmware device to control and exchange data. PBG 1 is intended for storing the operation codes of commands, addresses and constants. OZB 2 is designed for storing data, constant, addresses and commands during testing. The BMU 4 is designed for storing and issuing micro-commands for controlling external devices, for example, operating units, for issuing external microoperations to the device output 35, and also for controlling the microprogram device itself in various operation modes (device microoperations for output 36 of the device, groups 40-42 exits BMU 4). Interrupt block 5 is designed to provide an exit to an interrupt by issuing a fixed address to fetch the firmware depending on the incoming interrupt request and the mask code that masks certain interrupt code bits. The CPU 6 serves to control the exchange of data in various modes of operation of the device. The synchronization unit 7 is designed to synchronize the operation of the device. The command switch 9 is designed to control the passage of addresses from the outputs of the counter 12 commands and the counter 13 addresses to the bus 22 addresses when retrieving information from the PZB 1 and OZB 2 or recording information in the OZB 2 depending on the mode of operation of the device, as well as when storing addresses in the buffer register 17. The address switch 10 is designed to transmit a fixed address to the address bus 22 for reading (writing) a new (old) program state word when interrupting or reading commands at fixed addresses when communicating with the central by construction.

29

The information switch 11 is designed to control the passage of information to the data bus 21 from the output 55 of the buffer register 17, from the central data bus 23 depending on the control signals or from the outputs 56 and 57 of the blocks 18 and 19 of the bus elements.

Counter 12 of the commands is designed to set the address code when picking information from the OGS 1 and organizing the sequential course of the program.

The address counter 13 is designed to form an address code when retrieving information from AZB 2 and modifying this address to increment it by one if necessary.

The sample counter 14 is designed to form an address code when retrieving information from CSCB 3 and modifying this address by increasing it by one if necessary.

The counter 15 cycles is designed to control the retrieval of information from DSP 3, i.e. organizes the exchange of a given number of words.

The issuance register 16 is intended for storing information when transmitted to its central device.

The buffer register 17 is intended to 1dl temporarily store the code of the old program state word when processing an interrupt, and also to store the information of the address counter 13 when receiving information from the central device.

The first 18 and 19 blocks of trunk elements are designed to connect the output of the register 16 into the central data bus 23.

The third block 20 of trunk elements is designed to connect the sample counter 14 to the central address bus 24.

Start input 25 is designed to give a signal that starts operation (switching on) of this device.

The input 26 is intended to receive a code defining the direction of the direction with the central device and the address for reading (writing) information from the PSA 2 ,.

Logical conditions input 27 is intended to fix logical conditions, for example, from the processor's operating unit, a. also control 9601 0

signals on the organization of the device.

The address input 28 is for receiving the address code of the DSPC 3 from 5 of the central device, for example from the operation unit of the central processor.

Input 29 is designed to receive interrupt and request requests (input 30) for the exchange of information with the central unit.

Inputs 31 and 32 are intended for the arrival of the signals of the sign of access and writing in CSCB 3, respectively

5 Output 35 is designed to detect micro-operations signals for controlling external devices, such as an operating unit.

The output 36 is intended for transmitting the signal of the end of the exchange of information with the central device.

The output 37 is for transmitting a signal for allowing communication with a central device.

5 The output 38 is intended for transmitting a signal of the requirement of direct access to the DSP 3.

Consider the functional purpose of the elements and the work of BMU 4 (figure 2),

0 Block 64 of the microinstructions memory is designed for storing microprograms.

The address register 65 is intended to record the code of the address to which the micro-command is sampled.

5 of memory block 64.

I The micro-operation register 66 is intended for storing the operating part of a micro-command read from memory block 64.

0, the address switch 67 is intended for switching the operation code (the starting address of the microgram) and the address code of the next microcommand during the execution of the microprogram.

The first switch 68 is designed to form a micro-operation for accessing the FGP 1, depending on the control signals from the inputs 103.2.

0 and 103.3 and signals from outputs 102.1 and 102.2 of group 102 of outputs of register 66.

The second switch 69 is designed to form a micro-operation for accessing AZB 2 depending on the control signals at the inputs 4 and 103.5 and the signals from the outputs 102 and 1 and 102.2. 311129 Logic multiplexer 70 is used to generate the modifiable bit value of the address of the next microcommand coming from the output 96 of memory block 64 and implement the logic function Z Yoa + y b-t-y b2 + ... + Ucc, where Z signal is multiplexed output: 70; code from output 95 of memory block 64, allowing the address bit to pass from output 96 of memory block 64 to output of multiplexer 70 without changes; codes from output 95 of the microinstructions memory block, which predetermine the passage to the output of multiplexer 70 of one of the logical conditions signal b (, ..., input 27 and 59 of the BMU 4. The first AND-NOT 86 element is intended to form the microoperation of the end of the proposed device when signals are received from inputs 103.1, 102.3 and 48.4 of microprogram control unit 4. The second element IS-NE 85 is intended to form a micro-operation for enabling the write of the micro-command address code to the address register 65. The first element I 84 forms an information control control The second element And 77 forms a micro-operation for controlling the recording of information in the buffer register 17 with an input to 48.1 of the BMU; 4 clock pulses fi. The third element And 83 forms a micro, control operation for recording information into the register 16 With a stroke of the input 48.1 of the BMU, 4 clock pulses f. The fourth element I 71 forms a microoperation of the recording attribute of the first half-word in CSFB 3 with the arrival of the clock pulse tj. Fifth element I 72 is intended to form a microoperation of the sign of recording the second half-word in SSR 3 with arrival at input 48.3 of the BMU 4 clock pulse fj. The sixth element And 78 forms a micro-operation of recording in OZB 2 with an input to the input 48.3 of the BMU 4 clock pulse. The seventh element And 79 forms a micro-operation for controlling the recording of 12 commands with arrival at input 48.4 of the BMU 4 clock pulse. The eighth element And 80 forms a micro-operation for promoting the contents of counter 12 commands with arrival at input 48.4 for BMU 4 clock pulse f and a single signal from the output of the element OR NOT HE 87. The ninth element AND 81 forms a micro-operation to control the recording of the information of the address 13 counter with the arrival at the input 48.4 of the BMU 4 clock pulse V. The tenth element And 82 forms a micro-operation promoting the contents of the address 13 counter with the arrival at the input 48.4 of the BMU 4 clock t. The eleventh element And 73 forms a micro-operation promoting the contents of the sample counter 14 with the arrival at input 48.4 of the BMU 4 clocks T4. The twelfth element AND 74 forms a micro-operation of writing to the sample counter 14 with the arrival at input 48.4 of the BMU 4 clock pulse 4 and a signal at the input 102.5 of the group 102 of the outputs of the register 66. The thirteenth element And 75 forms a micro-operation promoting the counter content 15 cycles with the arrival at input 48.4 of the BMU 4 clock pulse t and the signal at the input 102.6 of the group 102 of the outputs. The fourteenth element And 76 forms the micro-operation of controlling the recording of the counter 15 cycles with the arrival at input 48.4 of the BMU 4 clock pulse 4 and the signal at input 102.7 of the group 102 of the outputs. The element 1-SHI-HE 8 / is intended for forming a micro-operation for blocking the advance of the counter of 12 commands. The HE element 88 forms a micro-operation prohibiting the issuance of two bits of a fixed address from block 5 interruptions in the development of micro-operations. The end of the command at the end of the last microprogram of the microprogram, after which the jamming occurs to form the only address of the microprogram of the interrupt exit microprogram, The BMU 4 works as follows. The operation begins with the arrival of the operation code (the initial address of the micro program) at the input 58 of the BMU 4, and takda 48.1-48.1 of the BMU 4, respectively. In the initial state, the BNU 4 triggers are in the zero state with the exception of the micro-operations register 66 triggers, which provide the formation of signals. End of the command at output 99.2, access to the ПЗБ 1 at output 102.2J permission to issue a counter code 12 at the output 100.4. With prtte: ode clock pulse at the input of 48.2 BMU 4, the starting address of the microprograms IY is written to the register 65. addresses received from the input 58 of the BMU 4 via the address switch 67. The resolution signal for the passage of the clock pulse T2 through the evil element. And 84 is the single signal from the output of the element AND-HE 85 which is formed when it arrives at inputs 54 of the BMU 4 and 102.8, respectively, of single or zero signal signaling. Thus, a selection is made from memory block 64 and the operating part of the first microcommand is written to the register 66 of the microoperations. Signals from the outputs of micro-register register 66 are provided for controlling the operation of the CTBaNra devices, for example, an operating block (output 35 of the BMA 4) 5 and also for controlling the operation of this firmware, for controlling and exchanging data (output 36, first 40, second 41 42 groups of exits of BMU 4). When executing the microprogram, in all cycles, up to the last one, the End of Team attribute will be absent and the next microcommand address will be completely determined by the information of the logical conditions code from output 95 of memory block 64, output 96 of modified address bit and output 97 of unmodified address bits of the memory block 64, as well as the logical conditions received at the input 27 4. When the last microcommand of the Vietnamese program arrives, micr 01 operation is complete. The end of the command for output 99.2 of the BMU 4, which allows the ation next program instruction to the input register 65 via the switch 67 addresses BMU 4. The address part read from the memory unit 64 from the microinstruction output 96 and 97 respectively is supplied to the multiplexer 70 and the switch 67 addresses. If the next micro-command is a linear-sequence micro-command, then the modification of the modifiable address bit by the logical conditions code on multiplexer 70 does not occur and the unmodified bit (output 96 of memory block 64) of the address from the output of multiplexer 70 together with unmodified bits (output 97 of block 64 memory) forms the code of the microcommand address, which, having passed through the address switch 67, arrives at the information input of the address register 65, followed by a lean BMU 4 operation cycle with the arrival of clock pulses Cj and f roiskhodit sample next microinstruction from the memory unit 64 and writes it into register operating portion 66 microoperations. If the next microinstruction is a microcommand of branching, then when the checked logical condition is fulfilled, the modified modifiable bit of the multiplexer 70 is modified. The modified address of the address c. The output of multiplexer 70 enters the low-order bit of the information input of the address 67 switch and changes its value if there is an appropriate logical condition. Consider the functional purpose of the elements of the interrupt block 5 (Fig. 3). Interrupt register 104 is for storing an interrupt code. The mask register 105 is for storing the mask code. The fixed address register 106 is intended to store a fixed address formed depending on the source requiring the interrupt and the mask code. It stores the interrupt codes listed in Table. one.

351129601

"

Table 1

About 1

36

At the output of 125 register 106 form

Oh oh

ABOUT

o The presence of an interrupt 1 in the discharge de O means the presence of an interrupt from the 0th source; 1 in the i-th (, 3) bit corresponds to the interrupt requirement from the 3rd (2nd, 1st) source permitted by the corresponding mask register bit, i.e. 1 i-ro bit 1 i-ro oazr yes i-bit. The first switch 108 is designed to control the recording of the code of the chip in the interrupt register 104. The second switch 109 is designed to control the writing of the mask code to the mask register 105. The second AND 111 and the third 112 elements And are designed to control the resetting of interrupt sources after their exit to service. The decoder 107 converts the request code from which the interrupt request was received into signals to exclude it. The fourth 113 and fifth 114 elements And are intended to emit signals representing two bits of the fixed address always, except for the moment of micro-operation of the end of the command and the end of the microprogram, after which the program is interrupted (i in this case the fixed address 100 at outputs 128, 129 and 130, respectively) “Consider the designation of the elements of the CPUU 6 (FIG. 4). Register 132 is a two-bit register and is designed to control the commatator of 9 commands and the address switch 10, interrupt unit 5, command counter 12 via the BMU 4 and the resolution trigger 133 in various modes of operation of the device. The first 136 and the second 135 elements AND, together with the OR 141 element, are designed to generate signals that provide information to the register 132 o The first 140 and the second 139 H – NE elements are intended to control the inhibitor trigger 134. The third 137 and fourth 138 AND-NOT elements are intended to control the trigger 133. The enable trigger 133 is intended to form a signal for the information exchange resolution (permission to output information to the device input group 34 in the mode when the exchange is initiated by an external device by applying a signal to input 30). Consider the functional purpose of the elements of the switch 8 control signals (Fig. 6). The first trunk element 145 is designed to issue a call to CSC of 3 from the BMU 4 on the first bus 149. The second trunk element 146 is designed to issue a recording signal of the first half-word in CSC of 3 on the second bus 150, the Third trunk element 147 is designed to issue a recording sign signal the second half-word in the SSRT 3 on the third bus 151. Consider the functional purpose of the elements of the synchronization unit 7 (Fig. 5). The generator 143 is designed to form four sequences of clock pulses shifted relative to each other at the outputs 48.1-48.4 of the synchronization unit 7, respectively. The trigger 144 is designed to generate a start signal for the generator 143. The purpose of the elements of the command switch 9 (Fig. 7) is as follows. The switch 152 is designed to switch the codes of the command counter 12 and the address counter 13 depending on the control signal at the input 42.3 of the switch 9 commands. Block 153 of the main elements is intended for an output; switch 152 from exit to: mmutator 155 (Fig. 8). The element NOT 154 generates a signal to block the release of information from the output of the switch 9 commands. Consider the assignment of the elements of the address switch 10 (FIG. 8). The switch 155 is designed to switch codes from the sign 26 of the direction of the device exchange and the output 44 of the code of fixed addresses of the interrupt unit 5. The purpose of the block 156 trunk elements is similar to the assignment of the block 153 trunk elements of the switch 9 commands. 39 1 The generator 157 zero is designed for operating a constant zero signal level with its subsequent addition of higher bits of fixed addresses from the inputs 26 and 44 of the switch 10 address. Consider the purpose of the elements of the switch 11 information (Fig. 9). Multiplexer 158 is designed to switch the code from buffer register 17 (input 55 of switch 11), first half-word code (input 56 of switch 11) and second half-word code (switch input 57) and implement the logical function UJ x t / H -fx H / fif V f 158 42.12 “0 55- 42.12 ISO 5i 42.12 160V multiplex output code H, litter 158; code of the buffer register 17 code of the first half-word; code of the second half-word; the first bit of the control signal arriving at input 42.12; the output signal of the switch 160, which is equal to the signal value of the second time input 42.12 when the signal is zero at the third bit of input 42.12 and the signal value at input 63 of switch 11 with a single signal value at the third bit of input 42 ;12. Block 159 of trunk elements is designed to drive the output code of multiplexer 158 into the data bus 21. The firmware for control and data exchange operates in four modes: execution of the main program; slow interrupt handling; fast interrupt handling; direct access mode. In the execution mode of the main program, the firmware for control and data exchange controls the operation device (operation block) by signals from external micro-operations outputted on the output 35 of the device. In the course of program execution, interruptions and exchanges of data with the central operational unit can occur, as well as data recording in the safety zone 2 from its operation unit from input output 33 via the bus 21 danh, and direct access to the data center 1 in direct access mode. In the initial state, all counters, triggers, and device registers are in the initial (zero) state. An exception is the triggers of the register of micro-operations of EMU 4, which are in one state and provide the formation of signals. The end of the command at output 99.2, the access to the IZS 1 at output 102.2, the resolution of issuing the counter code 12 commands at output 100.4 (FIG. 2). The operation of the device begins after the start signal is applied to the input 25 of the device. The Start signal, arriving at the first input of the synchronization unit 7 and setting the trigger 144 (FIG. 5) into one state, turns on the clock generator 143, which begins to form four series of clock t, -C shifted relative to each other. The zero code of the command counter 12 passes through the switch 9 commands (Fig. 7) and the bus 22 addresses, by the enable signal of the counter code from the output 42.3 of the BMU 4 and by the zero signal from the output 47 of the WCD 6 (register 132 is in the zero state ) arrives at the FZB 1. The zero code of the counter of 12 commands corresponds to a sample of the zero cell of FGW 1, which contains the operation code of the first program command, which is read from the FGW 1 by the signal for accessing FGW 1 by the program, which is read from the FGW 1 at the output 42.8 BMU 4 and enters the tire 21 Dan s. The operation code of the first command of the program from the bus line 21 is received at input 58 of the BMU 4. Signals from output 36 and three groups of 40-42 outputs of the BMU 4 are used to control the operation of this device. The signals are issued by the BMU 4 in accordance with the algorithm of the commands executed by the device, with a fourth / clock pulse 4, the block of the BMU 4 emits a micro-operation signal from outputs 42.6, which allows an increase in command counter 12 by one. This forms the address of the cell OZ 15 in which the operation code of the next command is stored and which, after the end of the firmware of the previous command, arrives at input 58 of the ITU 4. At the same time, the device continues to function in the same way. When the last microcommand of the program is issued, a microoperation of the end of operation is output from output 42 of 1 VMD 4 to the second input of synchronization unit 7. The trigger 144 of block 7 (Fig. 5) goes to the zero state, and the device stops operating in the operation mode. In the slow interrupt mode, during the execution of the main operation mode, there can be requests for interrupting the course of the main program .I at input 2. Output for execution as a program; Interrupt processing using the described mode is carried out in the end of the next command. The mode of exit to the interrupt processing subroutine is carried out by the microprogram for five cycles of operation of the device. One cycle work device}; corresponds to the period of operation of the synchronization unit 7, issuing a series of U. -L: four clock pulses., cruiHHyTbK is one relative of N. O drugopt. All devices of this mode are fucked;) The device is divided into four sources: O, 1, O, 1 ii-j Request for interrupts on:: stupid from the input. 29 requests for interruptions and device exchange are written asynchronously into interrupt register 104 of interrupt unit 5 (FIG. 3). Mask register 105 has three bits to populate interrupt requirements from sources I, 2 and 3 No. 1 interrupt exit program zero and first - third sources, taking into account the expansion of the mask from 105, is performed with the help of this method, in accordance with the requirements of breaks, fixed in the interrupt register 104 (FIG. 3) arriving at its asynchronous S-inputs set to units from entry 29 prera requirements the device and in accordance with the state of the register 105 of the mask at the output of the element IS-NOT 120, an interrupt signal is generated, and at the outputs of the elements IS-HE 118 and 119 the code of the source number of the interrupt is generated. The NO element 121, the AND element 110 and the IS-NE 115-120 elements constitute the priority encoder, which, taking into account the priority of the allowed interrupt requirement (the high priority has a source with a lower number) at the outputs, the IS-NE elements 118 and 119 generate the code the number of the interrupt source (in the presence of an allowed interrupt requirement, the output of the INE element 120 always produces a signal). At the end of each clock cycle f of the second synchronization input 48.4 of the test run 5, the specified code is written to the fixed address register 106, and at the output 128 of the fixed address register 106 a signal appears that after 43 interruptions arrives at the second control input of the CPUU 6 ( Fig. 4). .Before the last execution cycle of the previous command (the command that is currently being executed) output 92 of the end of command 64 of the memory of HIM 4 produces a signal that triggered the AND 136 element of the CCR 6 and the signal from its output goes through the OR 141 element to the second input of the control register 132 (in this case, it is assumed that the exchange request signal at the input 30 of the exchange requirement of the interrupt and exchange request input 29 is absent, otherwise the signals go to both inputs of the control register 132 and first of the exchange modes with higher priority) "Upon termination of the T signal from the output 48.4 of the synchronization unit 7, the device proceeds to execute the last cycle of the previous command, in which, besides the signals required by the corresponding algorithm of the given command, as well as the signals of the output command 99.2 in BMU 4, permitting the issuance of a counter code of 12 commands at output 42.3 of BMU 4 and circulation of FAL 1 at output 42.8 of BMU 4, inherent in the last execution cycle of any command required to select the next control word, The same 431 same signal at the output of the A7 block 6 control exchange. Thus, at the end of the previous command, a single signal from the output 47 of the CPU 6 blocks (via NOT 154 switch 9) you give the address of the next command from the output of the counter 12 commands via the switch 9 commands to the address bus 22 and allows the fixed address to be output from 44 of the interrupt block 5 (FIG. 3) via the address switch 10. In this cycle, for any code of the source number, the fixed address will have the value 0 ... 01000. At the least significant bit of a given fixed address of an interrupt, determined by the signal of a sign of writing in rZB 2 from output 98.6 of the BMU 4 (input 131-2 of block 5) is zero followed by the precedence of the discharge, determined by the state of the outputs of the And 113 and 114 elements ( Fig. 3) are zero, since And 113 and 114 elements are closed by the absence of a signal at input 131.1 of interrupt block 5 (the command end signal is present at the input of HE 88 BMU 4), the next most significant bit of a fixed address determined by a single output state 128 register 105 fixed adr sa - a unit, and all more significant bit rows fixed address defined by the zero-state output generator 157 Niemi zero (Figo 8) - zeros. Thus, in the absence of a signal or output 46 of the CPU 6 and the presence of a signal at the output 47 of the CPU 6, the address switch 10 (FIG. 8) provides the address bus 22 with the address 0 ... 01000, with which 3 FBG 1 records the operation code of the output firmware for an interrupt, which is selected instead of the operation code of the next program command, and in the follow up cycle, the program starts executing not the next program command, but the microprograms for entering the interrupt processing subroutine. In a .t2 clock pulse, the initial address of the firmware code for the interrupt is written to the address register 65, and according to the Y, its first microcommand is written to the register 66. Since there are no single signals at the inputs 142.1 and 142.2, the second input of the register 132 (Fig. 4) with the arrival of a clock pulse in the register records a zero signal, i.e. output 47 BUO 6 - zero signal, which allows the passage of information from the output of the counter 12 commands through the switch 9 commands. In addition, the BMU 4 with f forms a micro-operation for allowing the issuance of the counter code 12 commands, at output 42.3. Next, the first cycle of the interrupt exit firmware starts, the start of which is determined by the falling edge of the clock pulse f. In the first cycle of the interrupt exit firmware, the contents of command counter 12 are memorized (from the address bus 22, the contents of command counter 12 are fed to the lower bits the information input of the buffer register 17), which is one part of the old program state word (SSP), and the contents of the register 105 of the mask from the output 45 of block 5 of the interrupt NII, it is fed to the higher dy data input register 17), which is another part of the old yuschegos MTP in the buffer register 17. The old BSC recorded in the buffer register 17 with the arrival of the output control 42.11 uop recording buffer register 17 by a clock pulse J,. In the same cycle, the output 89 of the memory block 64 of the BMU 4 generates a single signal (recording the initial address of the microprogram to the address register 65 on the falling edge of the clock pulse 2) which through the OR element 141 of the CPU 9 goes to the second input of the register 132. The first cycle ends on a given front of the clock pulse t by the formation at the output 47 of the ACU 6 of a single signal, as well as the micro-operation of the control of the switch 11 information at the outputs 42.12 and D2.13 and the micro-operation of the reversal OZB 2 at the output 42.10. In the second cycle, the execution of the interrupt-exit microprogram is generated by a clock pulse f, the microoperation of the write attribute in OZB 2 at the output of 42.9 BMU 4. The OZB 2 records the old MTP at an odd fixed address (oddness is determined by the presence of the microoperation sign of the OZB 2 record, at the output 98.6 BMU 4), at 45 P, a single signal from the output 47 of the ACU 6 blocks the contents of the counter of 12 commands and permits the issuance of a fixed address from the block 5 via a commutator 4 address 10 In addition, if there are signals to Output 47 BOO 6 and output 98.6 of EMU 4 (input 131.2 of the block 5 of the jamming) produces a signal at the output, element I 111, which, at the end of the clock pulse C, is stored in the register 106 of the block 5 interrupt, B the third cycle of the output microprogram on interrupt production-15 on

Sampling and installation of a new SSP from an OZB 2 cell with an even fixed address is carried out, for which purpose in this cycle the microoperation of the record 3 OZB 2 at the output of 98.6 BMU 4 is missing, that is, there is no signal at input 131.2 of unit 5 that participates in the formation of the lower bit fixed address. In the third cycle, a single signal on v) at course 47 of the CPU 7 is formed in the same way as it was formed in the second ij.iiKic. This signal provides the supply of a fixed address to the 22-address address and, respectively, to a; T; the common input of the OZB 2, which receives a micro-operation from the entrance of 42,10 BMU 4. The new SSP of the cell with an even fixed ri; inecoM 035 2 through 21 days. (It enters the informadiol inputs of the touch terminal 12 ko.chand and mask register 105. At the corresponding output of the group 41 of the outputs 4 (input. 131.5 of the interrupt unit 5), a microoperation is generated, from which a new state of the clock and iply tj for register 105, the mask is entered into it, and then microoperations from the output 42.7 BMU 4 impulse ir into the counter of command 12 in the same cycle. In the same cycle, the output from the register 125 register 106 impulses the pulse Lj, the element 112 generates a signal strobe the decoder 107. At the inverted output of the fray 107 corresponding to the interrupt source For a processing, a zero signal is detected which is matched by that register bit. 104 interrupts whose source is being processed. Therefore, only at the end of the third cycle from the register 104 bud (5t the source of prema is excluded to eliminate the rotary capture of the interrupt source

In the fifth cycle of the described microprocessing, which is used to access the interrupt processing subroutine. Bearing in mind that the signal of the end of a command at the output 92 of the memory block 64 of EMU 4 is generated before the cycle of the cycle corresponding to the end of the command, the fourth cycle of this firmware is not the end of execution of this firmware, but is idle. in the fourth cycle, no micro-operations are generated. Delay of the last cycle of execution of the exit microprogram for one cycle Necessary programs are generated by the micro-operations End of command at code 99.2 of register 66 of the BMU 4, resolution of the contents of counter 12 commands at output 42.3 of the BMU 4 and access At the exit 42.8 of the BMU 4, which are used to select the first instruction of the interrupt processing subroutine from the FB1 1, the actions of the device when executed correspond to the first of the described modes, and at the end under programs Partial occurs not stop the device, and return to the interrupted program; Xn of the respective teams reduced old BSC, i.e. from the corresponding cell of the SSP 2, whose width corresponds to an odd fixed address, the old SCF is selected and entered into the command counter 12 and the mask register 105. Distribution (Fixed addresses of SSP 2 for storing old SSPs (used to restore them when exiting the interruption processing subroutine - storing new SSPs) is given in Table 3, T a b e and 3 471 Continuation of the table. In fast interrupt mode during operation device, it is possible to interrupt the main program for receiving or transmitting information from other devices, for example, from the central processor of peripheral processors, from a group of 34 input-output devices of the device without referring to the processing subroutine of such Interlacing. The implementation of such a mode of operation allows reducing the time to solve a problem by quickly microprogramming the processing of interrupts for individual classes of sources and reducing the amount of program memory by eliminating the subroutines for processing these classes of sources. the exchange comes from the input 29 of the requirement of interruptions and exchanges along the circuit of the input 30 of the requirement of the exchange to the input of the element 1355 BOO 6. The transition to this mode of operation cannot It is implemented only at the end of the execution of the previous command of the program, i.e. the enable signal is a sign of the end of the command at input 142.2 of the CPUU 6, i.e. on the course 92 of block 64 of the EMU 4 memory before the last execution cycle of the previous command, the zero status of the inhibit trigger 134 allows the I 135 element to be triggered. As a result, the signal to exchange from the input 30 through the element 135 goes to the first information input of the register 132 and through the OR element 141 - to the second information input of the register 132. Thus, the incoming command at outputs 46 and 47 of the CPU 6 contains single signals that prohibit the issuance of 1 code contents of the counter 12 commands via the switch 9 commands and allow edachu fixed address from the input device 26. The mode of receiving information is carried out for several cycles of operation of the device by a special command (firmware) stored in the FB1 1, at the address determined by the code at the input 25 of the device and by zeroes in the remaining address bits, we specify -. mi from the output of the generator 157 zeros (Fig. 8). By the clock pulse f, the signal from Vick 46 of register 132 through the IS-NE element 137 is fed to the inverse single input of the enable trigger 133 and translates it into a single state. As a result, the CPU 6 from output 37 signals the possibility of receiving information. From the output of the address switch 10, the address bus 22 receives a fixed address that defines the storage address in the FB1 of the information receiving command from external devices. At this fixed address, the initial address of the special firmware from the FBT 1 is sampled through the data bus 21 to the input 58 of the BMU 4, since at the end of the execution of any command, a signal is generated that the FB1 1 is accessed to select the next command. In addition, in the last cycle of the previous command, microoperations are developed, which are necessary for working according to its algorithm, after which a transition to the execution of the information reception implementation microprogram occurs. The contents of the counter 12 commands in this cycle is not promoted, since the signal from the output 47 of the BUO 6, passed through the element OR NOT 87 -in the BMU 4 (FIG. 2), prohibits the operation of the element 80 and the microoperation at the output 42.6 of the BMU 4 is absent . In the first cycle of operation of the device, when exchanging the exchange program by receiving information, the contents of the counter 13 address are output from the output 53 via the switch Y to the address bus 22 and are written to the buffer register 17 for recording management microoperations from output 42.11 of the BMU 4 to save the interrupted program . A control word is received from one of the I / O groups of the I / O group 34, which determines the sign of the information recording (in the PSA 2 or in the interrupt block 5) and the address, according to KOTOpoh4y, it is necessary to record the information. This control word (address and sign) through the information switch 11 on the corresponding microoperations from outputs 42.12 and 42.13 of the BMU 4 enters the data bus 21, and the address is recorded in the address counter 13 (therefore, in the second cycle of this mode the address determines the address of the SSP 2 or the corresponding register from the group 62 of the address inputs of the interrupt block 5). The sign of recording information (one or zero of the most significant bit of the control word) from the data bus 21 is fed to the input 59 of the BMU 4 and determines the choice of the next microcommand to perform or write information to the registers 104, 10

block 5 interrupts or OZB 2, was dried branch of the firmware MJJ; by modifying its address on the pultiplexer 70 in the BMU .4 according to the corresponding code of logical conditions 30 Gera

From the code 95 of the memory block 64 in the BMU 4, in order to exclude the possibility of re-servicing the incoming request for receiving information, a micro-operation is formed at output 99.1 around 40 outputs of the BMU 4 which, using a clock pulse, sets the trigger ban 134 of the CPU 6 to one. In this cycle, the work of the micro-operation of accessing the IZP 1 and AZB 2 is not formed. After the first cycle of the firmware is executed, the transition X is executed to the execution of one of the microcoms of the second cycle.

In the second cycle of operation of the devices, information is recorded either in registers 104, 105 of block 5, interrupts on one chip or in OZB 2 - on the other.

In the case of recording information in the registers of the interrupt block 5, for example from the central processor in debugging programs from the bus 22 addresses to the group 62 of the address inputs of the interrupt block 5 (FIG. 3), the register number code (interrupt register 104) is output from the address counter 13

properties. In addition, this signal is fed to the input of the element H-NE 138 BUO bis. By the arrival of such an impulse T4, three g

The supply of information to external devices on a group of 34 inputs / outputs of the device is growing.

 When another micro-command is executed (depending on the firmware), in the second cycle of operation, information is recorded in OZB 2, In this case, the contents

the counter 13 of the address through the CT-9 arrives at the bar 22 of the address and from it to the address input of OZET 2. From outputs 42.9 and 42.10 of the BMU 4, micro-operations are performed for recording and reversing ARP 2, respectively. Information from the group 34 of the device inputs and outputs enters the input-output of the OZB 2 through co-m1 and ipu 21 data. At exit 36, as when performing

the second cycle is issued, the microoperation of the end of the exchange is issued and with the arrival of the pulse T, the trigger 133 of the CPU BOO 6 is set to the zero state, after which the external information devices to the device input / output group 34 are discontinued and the request signal is removed from the device device input 29 105 masks). For example, if it is necessary to write information to the interrupt register 104, the address code can be ... 10. If necessary, the address code can be written to the mask register 105. The address code can be ... 01. When it is necessary to write information in both registers, the code has the form .. .eleven. From the group 34 of the device inputs and outputs, the information is fed through the switch 11 to the data bus 21 and from it to the information inputs of the interrupt register 104 and the mask register 105 of the interrupt block 5, and corresponding write operations to the registers 104 and 105 are formed on the group 41 of the BMU 4 outputs recording information into which is produced by a clock pulse G, depending on the codes at the input 62 of the interrupt block 5. The output of the interchange signal is applied to the output 36 of the device to eliminate the exchange request from the input 29 of the resolution device, after which the device switches to the third cycle of operation in the mode in question. In the third cycle, from the outputs 42 .1 2 and 42.13 of the BMU 4, the corresponding micro-operations are output, according to which the contents of the buffer register 17 (the locked state of the address counter 13 for the time of fast program code interruption) is transmitted through the switch 11 to the data bus 21. According to the clock pulse t4, output 42.5 forms a micro-operation, according to which the address counter is restored, after which the transition to the execution of the latter occurs; Fourth cycle. Execution of this mode. In the fourth cycle of operation of the device, microoperations are formed. The end of the command at output 99.2 of group 40 of the outputs of the VMU 4, advancing the contents of the counter 12 commands at the output of 42.6 BMU 4 and appealing to the IZB 1 at the output, 42.8 BMU, 4, which transfers the contents of the counter of 12 commands via the switch 9 to the bus 22, the addresses, fetching the next interrupt operation code of the program from the output of the PZB. 1 through the data bus 21 and entering it into the register 65 of the address of the BMU 4. By micro-operation, the end of the command with the arrival of the clock pulse TT through the IS-NOT 140 element is brought to the initial (zero) state of the inhibit trigger 13A. Further, the firmware device for controlling and exchanging data 1 also functions in the same way as in the mode of executing the main program. In the considered exchange mode, when information from this device is transferred to another device, work as follows. The output to the mode of executing information transfer commands is carried out similarly to the exit to the execution of an information receiving command. However, the code at input 26 of the device identifies a sample of the operation code by processing the corresponding fixed address at which the given operation code, which determines the initial address of the information transfer firmware, is stored in the TZB 1. Execute command transfer info

The procedure takes place in five cycles, while the release of information can be made from both the AZB 2 and the IZP 1.

in the register 16 of the output to you :: ode 42.2 VMU D, as a result of which the register of the issuance register 16 is recorded. The first execution cycle, the commands for issuing information are carried out similarly to that described when executing this mode, the following signals (microoperations) are issued: output 99.1 of group 40 of the BMU .4 outputs, which activates the inhibition trigger 134, blocking the perception of a repeated request for an exchange request for the entire execution of this mode (the new exchange requirement from input 30 is perceived only after neither this command); signals at the outputs 46 and 47 of the CPU 6, which allow the output of the contents of the address 13 to be sent through the commutator 9 and the address bus 22 to the information input of the buffer register 1 7 and write information to it on the microoperation at output 42.11 of the BMU 4; microoperations at the outputs 42.12 and 42.13 of the VMD 4, through which the control word is transmitted via the switch 11 to the data bus 21 from the corresponding input of the group 3-4 inputs / outputs of the device; micro operation management of recording information into the counter 13 of the address at the output 42.5 of the BMU 4 for recording the address of the cell OZB 2 and the FBW 1 into the counter 13 of the address coming from the data bus 21; In this case, the logical condition code from output 95 of memory unit 64 of VMD 4 (Fig. 2) analyzes the sign indicating the type of memory — AZB 2 11li or PZB 1, from which information is calculated and (this sign is in the highest order of the control depending on the sign of the modification by the signal from the input 59) of the address by the multiplexer 70 of the BMU 40, the calling address of the microcommand to execute the second cycle of this firmware. In the second cycle of the execution of this mode, for example, when reading a given cell of the fire alarm system 1, the following control signals are generated: a zero signal at the output 47 of the CPU 6, which allows the contents of the address 13 to pass through the switch 9 to the address inputs of the safety warning 2 and the safety barrier 1; PZB 1 micro-operations at exit 42.8 of the BMU-4 and information management information micro-operation: and the required recipe; PBT 1; micro-operation. The end of the exchange at the output 36 of the device, the PS of which with the passage of the clock pulse is set to the initial (zero) state trigger of the resolution 133 of the CPU, and at the output 37 of the device, a signal is output, according to which the external device cuts off the control apov to the group 34 input-output device. The End of exchange signal from the device output 36 eliminates the requirement of the exchange, which enters the input 30 of the device input group 29. Execution of the second cycle while reading the contents of the required cell of the OZB 2 is different in that, instead of the microoperation of the ZBP, the output of the 42.8 HEU 4 is generated by the microprocessor reverse OZB 2 at course 42.10 HEU 4, which is used to sample the contents of the target OZB cell 2. Then the transition occurs to execute the third cycle of microprogram execution of information output to an external device. This is formed by a micro-operation at output 42.1 A of EMU 4, according to which the contents of register 16 through the first block 18 of the main elements and the central: main data bus 23 enters a group of 34 input-output devices of the device. Next, a transition to the execution of - {Fifth to the fifth cycle of the given micron: CROPRO1-S. The fourth and fifth cycles are similar to the third and fourth cycles of the microprogram of receiving information from external devices, e, in the fourth cycle, microoperations are generated at outputs 2.12 and the BMU 4, through which the contents of the buffer-register 17 through the switch 11, The data bus 2 is fed to the information input of the address 13 to which it (the old contents of the address 13 is recorded) is recorded at 42 .. 5 BMU 4. In the fifth cycle of operations. The development of micro-operations at output 99.2 of group 40 of outputs of BMU 4, output 42.6 of BMU 4 and output -42.8 of BMU 4, according to which the inhibit trigger 134 is reset, the next program-1b command is selected: from PZE 1 and implemented There is a promotion counter 12 teams per unit. Next comes the execution of the interrupted program. In the direct access mode,; - switches to i.e of the execution mode of the main program tt., When, during the execution of the main program, the output from the OZB 1 direct access command (ND) occurs. At the command of ND, the device signals to the outside device — the center of the al1-gu-processor at its output 38 that it requires data exchange in direct access mode between DOSE 3 and OZB 2 or PZB 1, and direct access to POSE 3 is possible as when transferring data from P035 3 to OZB 2, and when they are transferred from OZE 2 and PZE to POSB, the microprogramming device for control and exchange is required to exit 38 of the device of the sat-nal demanding direct access from CSFB 3 ;. Od.codit to ozh; adany arrival mode. logical condition from input 27 of the device that resolves the actual directly .tool Comm.While the main program is preceded by the following commands for loading (setting) counters of the device for sampling and writing data into blocks pam p :; command download counter Uiv; Gg-rki; download command "etchik. 15 Ts1: k.pos; download counter command 13 address.a. About the tributes to the teams, it is possible to produce meter loads of information from both OTG 1 and OZE 2. In Tab. 4 and 5 show the wild-type versions-1A com.and load the proposed device from the FPB 1 and OZB 2, respectively.

Name of information

Numbers of cells PZB 1 PZB 1

i + 1

KOP i + 2 The initial address of CSCB 3

COP 2

The addition code of the contents of the counter 15 to the number of half-layers

KOP

The start address of the CRA is 2 CPC.

The initial ad-COP,

1 pec TSOZB 3

2j + 1

Code additions KOP counter contents 15 cycles to the number of exchanged half words

3

j 2

Head ad - ViOU pec OZB 2

j 3

four

It doesn't matter CPC for this subroutine.

TableD

KOP team name

Download counter sample 14

Download counter 15 cycles

Download counter 13 addresses

Direct

access

Table5

Download counter sample 14

Download counter 15 cycles

Download counter 13 addresses

Direct access Consider the execution of the command to download the sample counter 1A in accordance with the table. 4. At the end of the execution of the previous command, the operation code of the load command of the sample counter 14 is fed to the register 65 of the address HEMU A (FIG. 2). According to clock pulse B, register 66 records the first microcommand and begins the first cycle of executing the command for loading the sample counter 1A in which the following microoperations are formed: advancing the contents of the counter 12 commands at output 42.6 of the BMU 4; enable the counter code 12. commands at the output of 42.3 BMU 4; Appeal to PHB 1 at exit 42.8 BMU 4; control the recording of the information of the sampling counter 14 at the output 42.21 of the BMU 4, according to which - information is recorded which has been stepped on the information input of the sampling counter 14. According to the microoperations, the command counter 12 generates the address of one of the FBG 1, which contains the necessary information to load the counter 14 of the sample, while the information / read from the FBG 1 is fed through the bus / 1 data to the information input 14 of the sample and stored in him. The second cycle of executing this command is the last one; therefore, it develops the strategies for the last cycle of executing any command, ensuring that the next command word is typed. The execution of commands for loading the counter 15 cycles and the counter 13 of the address is similarly performed by the command to load the counter 14 of the sample according to the corresponding micro-operations at the outputs of the BMU 4. Consider executing the command to download the counter 15 cycles with information stored in OZB 2, in accordance with the table 5. The execution of this command is similar to the execution of the 15-cycle counter load command information stored in the FB1, but in the first cycle, a micro-operation is generated, which calls the FP2 2 on the code 42,10 BMU 4 instead of FBB 1 and the output 42.8 BMU 4, micro-ops at the output 42.3 BMU 4 of Collateral in

It sends the code of the switch 9 commands to the contents of the counter 13 of the address, and not the counter of 12 commands. Instead of 1

access from the proposed device. The micro-command address is modified and in the address register 65 it is recorded 158 micro-operations 42.6 advancing counter 12 of the command of the BMU 4 E-mail. It develops the micro-operation 42.4 advancing counter 13 of the address. Similarly, the sample counter 14 and the address counter 13 are loaded. When implementing the subprogram in accordance with table. 5, it is necessary to load the address counter 13 only after loading the sample counters 14 and cycles 1 5. Thus, after the counters are loaded, the direct access command is executed. The ND MijryT commands should be of the following type: ID — data transfer from the IZS 1 to POSB 3; ND2 - data transfer from HSS 2 to HSE 3; NDZ - transfer of data from CSCP 3 to RZB 2. Each ND command corresponds to a certain micrograph, which is implemented by the microprogram control unit. Consider the execution of the ND2 command that transmits data from HSS 2 to HFSP 3. The format of the data word of HFB 3 is two words of HF 2, KOTopbie can be called half words, and one half word is stored in the cell of HF 2. In the cell of DOSB 3 there are two half-words of the data format of AZB 2. The operation code (the initial address of the firmware ND2) is written into the register .65 of the address of the BMU 4 (Fig. 2). With the arrival of the synchronization register 66 of the microoperations of the clock impulse t, the first microcommand of the NL2 microprogram is recorded in the register 66. At the output 101.6 of the register 66, the microoperation of the direct access is generated, which enters the code 38 of the device. After that, the device goes to transfer data from OZB 2 to 110315 3. The address register 65 records the address of this w €: the first mi of the plXKomandy that is counted from the memory block 64. The address register 65 records the address of the first microcommand until the device receives the sig1 from the input 27; the logical condition indicating that the external device provides CSCB 3 for the direct address of the next second microcommand. As a result of recording the second microcommand into register 66, the following microoperations are formed by transmitting data from CAS 2 to CSC 3: access to CSP 2 at output of a BMD output 42.10; control the recording of information in the register 16 issuance at the output 47.2 BMU 4; control of the blocks of trunk elements 18, 19 and 20 at the outputs 42.14, 42.15 and 42.24 of the BMU 4, respectively; control switch 8 at output 42.18; microoperation at the first output of the group 102 outputs of the register 66 of the micro-operations of the BMU 4; promoting the contents of the account Ikov 1 14 and 15 at the outputs 42.4, 42.20 and 42.22 Bf-ty 4, respectively; micro operations at output 102.8 of group 102 of outputs of micro-register register 66; Appeal to CSRB 3 at the output of 42.16 BMU 4; alternately micro-operations of recording the senior and junior half words in TSOSB 3 at outputs 42.17 and 42.19 of the BMU 4, respectively. As a result of the arrival of a single signal to the direct input of the NAND 85 element and the zero signal (the overflow output 54 of the 15 cycle counter is in the zero state), the inverse input of the AND-85 element 85 generates a zero signal at the output of the latter that blocks the clock slip of the clock. pulses of Chapter 1 through element 84. Therefore, the address of the next microcommand is not recorded in register 65. The address of the next microcoma is recorded in register 65 after the end of the data transmission on the overflow signal of the counter 15 cycles. The microoperations formed on group 42 of outputs controls the recording of half-words from HZB 2 into DSCR 3. The addressing of HZB 2 cells is performed by sequentially increasing the content of the counter 13 of the address. The value of the lower digit of the counter 13 address code through the switch 9 and the bus 22 (output 63) is fed to the input 63 of the BMU 4. The signal from the input 63 of the BMU 4 goes to the direct and inverse inputs of the And 71 and 72 elements, respectively. If the odd-numbered cell address (the value of the lower-order bit is one) is recorded in the address counter 13, then with the arrival of the pulse tj to the input of the element AND 72 at the output of 100.13 group 1 160 py 42 outputs of the BMU 4 (output 42.19) a single signal is generated through the switch 8 to the output 51 of the switch. As a result, a half-word from a cell with an odd address is written by pulse g to register 16 of the output, and by a clock pulse through input code 39.2, to DSCR 3. The address of cell DSCR 3 is determined by sample counter 14. The bit size of sample counter 14 is determined in such a way that the least significant bit of it is not fed to the address of DSPC 3. This allows you to save the address of DSP3 in counter 14 of the sample for two cycles of operation, i.e. write half-words from HZB 2 at one address - even or odd, depending on which initial address was loaded into sample counter 14. For example, the original address recorded in counter 14 is 00000. Increasing the contents of the counter does not change the address of the DSP 3 cell, since the code is 00001. The first bit is 1, the remaining bits of the bit retain the O value. Thus, address 0000 is written in two words. In the following, counter code 14 is 00-010 and half-words are written in the cell with address 0001. Promotion of the counters 13, 14 and 15 is carried out sequentially J3 each cycle. Due to this, the data is read from OZB 2 cells with even and odd numbers and by sig, terminals from outputs 100.12 and 100.13 of elements 71 and 72 of the BMU 4 (outputs 42.17 and 42.19 of the BMU 4) are recorded sequentially in the older and junior parts of CEZB 3 Two half-words of data from even and odd cells of HSE 2 are recorded in each cell of CSVS 3. After the data is transmitted (recorded in CSVS 3) with a counter for 15 cycles, an overflow signal is generated, which enters input 54 of the BMU 4 and unblocks the passage of clock pulses tj lepes element I 84 at the register synchronization input 65 sa As a result, the address of the next microcommand is recorded in the address register 65, the microoperations of which are inherent in the end of execution of any command at which the NT program proceeded to the next program command, i.e. Exit from ND2 command execution mode. Data transfer from the ZZP 1 to the DSCP by the command ND1 is carried out similarly to the transfer of the DZB 2 3 DSPD 3, Addressing the cells of the PZB 1 is performed by the address counter 13 according to the same principle, not in this case instead of a micro-operation to access OZB 2 on the code 42.10 BMU 4 is generated by a micro-operation of accessing the 1 BHZ at exit 42.8 of the BMA 4. Data transfer to the CEP of 3 in the CRO by the NDZ command is performed in the analogous manner, however, at the same time, the microoperation to write half-words in COSB 3 at the outputs 42.17 and 42.19 of the BMU 4 n - not produced; micro-operations, opening groups 18 and 19 of the main elements, at outputs 42.14 and 42.15, the BMU 4 are not developed; microoperations at outputs 42.12 and 42.13 of the BMU 4 are developed in such a way that the output of the information mutator 11 is r; Ordpcha information from the outputs 39.1 to 39.2 DOZK 3 and, respectively, from the pikodo} central bus 23 data}: parity or odd ness addresses OZB 2, specified by the output 63 of the lower bit bus 22 addresses. At the same time, if the address of the HFB 2 is odd (the unit value of the output is 63 youngest: 1 is its address bus of the 22 address), the output of the switch 11 is information from its input 7g: 1 5 (m-; the next half-word of HFR 3), and for an even address of the SSP 2, information from its input 56 is transmitted to the output of the com-1utator 1 1; the micro-operation of the recording in DSS 2 is generated at output L 2.9 BMU D The central processor with DSP 3 is operated using access signals (input 31 of block 8 zalis -: (input 32 of block 8), addresses given at input 28 of the address, and yes • 5 - 1-F, 1X to the central bus: 23 data through a group of 34 inputs of outputs.The resolution of the ND to CSCM 3 from the side of the central processor, which is supplied to one of the inputs of group 27 of the inputs, is preceded by a transfer of inputs 31, 32 , 28, and groups of 34 entries into the passive, so-called third state, under which they are not The implementation of the ND regimes is realized. The structure of the device to be sent is ensured by the flexibility and the organization of a complete check of the operation of its components separately and of the device as a whole during the execution of the self-checks rekim. In the self-checks mode, the device works as follows. All commands of the command system, realizable on this device, should occupy a significant amount of memory of the memory and memory protection 1,. comparable with the memory capacity for the main program, and in some cases superior to jfx. In addition, it is often necessary to have a stand-alone check of the device’s equipment without the fate of many external devices setting all modes of the device operation. Reliable verification of the entire volume of the 1 1 SZB program can, as a rule, be carried out only with the performance of these programs themselves, and this is not always possible. To implement the check of all equipment, including the full equipment of the TZB 1, the latency modes for fast program interruptions (such as Data exchange with the suspension of its program) and slow games) interrupts in the BMU 4, the commutators 68 and 69 are introduced, which, under the control of external signals from Inputs 27, the same memory access signals at the outputs of micro-operation register 66 are interpreted as a search signal of the precinct 1 or OZB 2. This allows the control program to write monitoring programs; we are any exchange, since they are executed in part check device when working on all commands included in the system. In this case, the FBB 1 can be processed not by commands, but by AaHHbEvm. Thus, the check of the entire FBB 1 is ensured. J Implementing the output to the interrupt, exchange and direct access modes can be carried out without working out the corresponding: external signals of the interrupt, exchange requirements and direct access, but according to the program, in the body of which commands are written that are adequate to the data of the mode. For this purpose, a regular output to the firmware for processing fast interrupts with suspending a program or for microprograms for accessing subroutines for processing slow interrupts or direct access microprograms is not implemented by interfering with the addressing of block 64 of the microprogram memory, as in known devices, but through addressing the OTL with the introduction of commands to the command system using a fixed address machine, necessary to implement the storage of the old and the selection of the new MTP. This also makes it possible to organize cooking, for example, interrupt-exit modes by expanding the equipment being tested, i.e. First the interrupt exit firmware is checked, then it is included in the check and equipment of interrupt unit 5. In addition, organizing a program recording not only in the mask register 105, but also in the interrupt register 104 allows, with disconnected sources causing interrupts (and connected sources, but in the passive mode - turned off), to check the correctness of the device’s response to interrupt requests. The correct response to the interrupt requirements is performed according to the following algorithm: checking without interrupting for all possible combinations of signals at the outputs of registers 104 and 105 (for example, the contents of register 104 are zero, the contents of register 105 are ones in all bits, or the organization is running units, excluding the bit for the zero source, in the register 104 and the running zero for the corresponding bits of the mask register 105); validation of priorities when exiting interrupts in turn, starting with the highest priority (the contents of register 104 is 1111, the contents of register 105–111) to the youngest (the contents of register 104 is equal to LLG. Thus, the structure of the proposed device, its blocks and communications allow complete checks of its equipment without including test checks in the software test systems, which further increases the reliability of its operation.

29 3

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m.2

m.z

m.

8.1

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thirty

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(Rig.

71

; RB / g.

Claims (2)

1. A firmware for controlling and exchanging data, comprising a command switch, an address switch, an exchange control unit, an interrupt unit, an output register, a buffer register, an address bus, a data bus, an information input of the output register, groups of inputs of the interrupt code and mask code the interrupt unit via the data bus is connected to the input-output of the peripheral device, and the first group of information inputs of the address switch * forms the input of the sign of the direction of exchange of the device, the group of information inputs of the block interruption forms the input of the interruption and device exchange requirement, the second group of information inputs of the address switch is connected to the group of information outputs of the interrupt unit, the first output of the exchange control unit is connected to the input of the sign of a fixed address of the interrupt unit and with the permissible inputs of the command switches and addresses, the group of outputs of which via the bus the addresses are connected to the corresponding group of inputs of the lower digits of the buffer register, the inputs of the senior digits of which are connected to the group of outputs of the masking bits of the interrupt block, the group of address inputs of which is connected via the address bus to the group of corresponding outputs of the address and command switches, the output of the interrupt block interrupt is connected to the interrupt input of the exchange control unit, the exchange request input of which is included in the group of interrupt request and device exchange inputs, the second output the exchange control unit is connected to the sample input of the address switch, the third output of the exchange control unit is the output of the device’s exchange resolution, characterized in that, in order to increase the speed of data exchange and expand the scope by means of buffering. To transmit the transmitted data and implement exchange algorithms using hardware and software, a permanent memory instruction block, random access memory unit, central online memory unit, firmware control unit, synchronization unit, control signal switch, information switch, command counter, counter are introduced into the device addresses, sample counter, cycle counter, three blocks of trunk elements, a central address bus and a central data bus, the first information input of the block microprograms— 1096 ^ 1 Γ'Τϊδ a lot of control forms an input to the logical conditions of the device, a group of information outputs of the information switch, a permanent memory instruction block, information inputs and outputs of an operational memory block, information inputs of instruction counters, addresses, samples and cycles, the second group of information inputs and the third the information input of the microprogram control unit via the data bus is connected to the inputs and outputs of the peripheral device, the first group of outputs of the microprogram control unit is formed the external microoperation output of the device, the first and second groups of information inputs / outputs of the central random access memory unit, the first group of information inputs of the information switch and the group of outputs of the first block of trunk elements connected to it, the second group of information inputs of the information switch and the group of outputs of the second block of mains connected to it elements through the central data bus are connected to the input-output of the central processor, a group of address inputs of the central operative of the memory block through the central address bus is connected to the group of outputs of the third block of trunk elements and to the group of address outputs of the central processor, the first input of the synchronization block is the start input of the device, the first and fourth outputs of the synchronization block are connected respectively to the first or fourth synchronization inputs of the microprogram control unit, the first and fourth _t outputs of the synchronization unit are connected respectively to the first and second synchronization inputs of the exchange control unit, the third and the fourth outputs of the synchronization unit are connected respectively to the first and second inputs. the synchronization of the interrupt unit, the first and second groups of outputs of the microoperations of the microprogram control unit are connected respectively to the group of inputs of the microoperations of the exchange control unit and the interrupt unit, the first sixth outputs of the third group of outputs of the microoperations of the microprogram control unit are connected, respectively but with the inputs for controlling the recording of the output register, address counter, instruction counter, buffer register, select counter the counter, cycle counter, seventh to tenth outputs of the third group of microoperation outputs of the microprogram control unit are connected respectively to the counting inputs of the address counter, command counter, sample counter and cycle counter, the eleventh to twentieth outputs of the third group of microoperation outputs of the microprogram control block are connected respectively to the second input of the block synchronization, an input of a sample of a command switch, a control input of a read-only memory command block, the first, second control inputs of an opera of the primary memory block, the first, second control inputs of the information switch, the control inputs of the first, second and third blocks of trunk elements, the twenty-first and twenty-fifth outputs of the third group of microoperation outputs of the microprogram control unit are connected respectively to the first and fourth inputs of the control signal switch and the direct demand output access devices, the outputs of the command counter and the address counter are connected respectively to the first and second information inputs command switch, the first output of the exchange control unit is connected to the first control input of the microprogram control unit, the second control output is bloc, as the firmware control is connected to the first control input of the exchange control unit and the output of the device’s end of exchange, address inputs of the permanent memory instruction block and random access memory block the address bus is connected to the outputs of the command and address switches, the group of outputs of the buffer register is connected to the third group of information inputs information mutator, the output of the counter is connected cyclically to the second control input of the microprogram control unit, the output of the output register is connected to the information inputs of the first and second block of trunk elements, the access and recording inputs of the device are connected respectively to the fifth and sixth inputs of the control signal switch, the first output of which is connected to the first control input of the Central storage unit, the second control input of which is connected to the second and third outputs of the control signal switch the output of the sampling counter, except for the least significant bit, is connected to the input of the third block of trunk elements, the least significant bit of the address bus is connected to the fourth information input of the microprogram control unit and to the third control input of the information switch, and the exchange control unit contains AND elements, an OR element, a register , enable trigger and prohibition trigger, NAND elements, the first input of the block synchronization is connected to the first inputs of the first, second and third NAND elements, the second synchronization input of the block is connected with the first input of the fourth AND-NOT element and the register synchronization input, the first input of the group of inputs of the microoperations of the block is connected to the first input of the OR element, the second input is with the first inputs of the first and second elements AND, the third and fourth inputs are with the second inputs of the first and second elements AND-NOT, the first and second control inputs of the unit are connected respectively to the second inputs of the fourth AND-element and the first AND element, the output of which is connected to the second input of the OR element, the information input of the unit is connected to the second input of the second AND element, the output of which is connected to the third input of the OR element and the first information input of the register, the output of the OR element is connected to the second information input of the register, the first input of which is the first output of the block, the second output of the register is connected to the second input of the third AND-NOT element and the second output exchange control unit, the outputs of the third and fourth elements AND are NOT connected respectively to the inverse of the single and zero inputs of the resolution trip. the output of which is the third output of the block, the outputs of the first and second elements AND are NOT connected respectively to the inverse single and zero inputs of the inhibit trigger, the output of which is connected to the third input of the second element I. 2. The device according to π. 1, characterized in that the micro-program control unit contains a micro-memory memory block, an address register, a first switch, a second switch, an address switch, a logic condition multiplexer, fourteen AND elements, two AND-NOT elements, an OR-NOT element, a NOT element and a register microoperations, and the first information input of the block. the firmware control is connected to the first information input of the logic condition multiplexer, the first control bit of the first information input of the firmware control unit is connected to the first input of the first NAND element, the second and third control bits of the first information input of the firmware control unit are connected to the first and second information inputs of the first switch, the fourth and fifth control bits of the first information input of the unit micro. software control are connected respectively to the first and second information inputs of the second switch, the second information input of the firmware control unit is connected to the first information input of the address switch, the output of which is connected to the information input of the address register, the third information and first control inputs of the firmware control unit are connected respectively to the second information multi input. the logic condition plexor and the first input of the OR-NOT element, the second control input of the firmware control unit is connected to the inverse input of the second AND-NOT element, the output of which is connected to the first input of the first AND element, the first synchronization input of the firmware control unit is connected to the first inputs of the second and third elements I. the second synchronization input of the microprogram control unit is connected to the second input of the first AND element, the output of which is connected to the synchronization input of the address register, the third input is sync the microprogram control unit is connected to the first inputs of the fourth, fifth and sixth AND elements, the fourth synchronization input of the microprogram control unit is connected to the first inputs of the seventh fourteenth AND, with the second input of the first AND element and the synchronization register input of microoperations, the first, second and third the outputs of which are connected respectively to the first, second control outputs and the first group of microoperation outputs of the microprogram control unit, the fourth output of the mic register operations is connected to the direct and inverse control inputs of the address switch, the first group of microoperation outputs of the microprogram control unit and the element HE, the output of which is connected to the second group of microoperations outputs of the microprogram control unit, the fifth output of the microoperation register is connected to the second input of the IPI-Нё element, the output of which is connected with the second input of the eighth element And, the sixth - ninth outputs of the microoperation register are connected to the second group of microoperation outputs of the microprogram control unit , the tenth output of the microoperation register ^ is connected to the second group of microoperation outputs of the microprogram control unit and the second input of the sixth element And, the eleventh - fifteenth outputs of the microoperation register are connected respectively to the second inputs of the second, seventh, ninth, ninth and third elements And, the sixteenth output of the microoperation register connected to the third input of the eighth element And and the third group of outputs of microoperations of the microprogram control unit, the first output of the group of outputs of the register of microoperations with it is single with the second inputs of the fourth and fifth elements of And, the second and fifth outputs of the group of outputs of the microoperation register are connected respectively to the second inputs of the eleventh to fourteenth elements of And, the sixth and seventh outputs of the group of outputs of the register of microoperations are connected respectively with the direct input of the second element AND NOT and the third input of the first AND-NOT element, the eighth output of the group of outputs of the micro-operation register is connected to the first control inputs of the first and second switches, the ninth output of the group of outputs of the micro-register operations is connected to the second control inputs of the first and second switches, the output of the address register is connected to the input of the micro-command memory block, the first and second outputs of which are connected to the first group of micro-operation outputs of the microprogram control unit, the second output of the micro-command memory block is also connected to the first input of the register microoperations, the third - sixth outputs of the micro-command memory block are connected respectively to the second - fifth inputs of the micro-operation register, the seventh and eighth outputs of the micro-command memory block are connected inens, respectively, with the control and third information inputs of the logical condition multiplexer, the output of the modifiable bit of the address of which is connected to the input of the modifiable bit of the address of the second information input of the address switch, the ninth output of the memory block of microcommands is connected to the input of the non-modifiable bits of the address of the second information input of the address switch, fourth information input The firmware control unit is connected to inverse and direct inputs. the fourth, fifth elements And, accordingly, the seventeenth - twenty-fourth outputs of the micro-operation register, the outputs of the second - fourteenth And elements, the output of the first AND-NOT element, the outputs of the first and second switches are connected to the third group of micro-operation outputs of the microprogram control unit.