SU1336017A1 - Information exchange device - Google Patents

Abstract

The invention relates to computing and can be used in computer systems for interfacing computers with external devices operating with a serial code. The purpose of the invention is to increase the speed of information exchange and expand the functionality of the device by providing the ability to change the format of the received and transmitted data. The device contains an amplifier block, a priority node, an interrupt address register, an address decoder, a switch, a command decoder, a clock generator, a transmitter, a receiver, a coder. To implement the information, the transmitter contains a linear unit, a status trigger, a mode trigger, a synchronization counter, AND elements, a NOT element, counts of transmitted pulses, a reset decoder, a shift register, a selector decoder, an encoder control trigger, a buffer register group, and data switch For inputting information, the receiver contains a linear unit, an input signal switch, AND elements, a synchronization counter, a synchronization trigger, an input pulse counter, an input state trigger, a shift register, a decryption- reset generator, a selection decoder, a group of input buffer registers, data tator. The device is based on the principle of converting a parallel code received from a computer into a parallel or serial code for transmission to an external device, as well as the reception of a serial code. yes, transmitted to an external device, and converting it to a parallel one, with the subsequent transfer of the latter to a computer, 5 Il. . -o (L with oo O5

Description

113

The invention relates to the field of computer technology and can be used in computer systems for interfacing the input-output channels of a computer with external devices (subscribers).

The purpose of the invention is to increase the speed of information exchange and expand the functionality of the device by allowing the format of the received and transmitted data to be changed.

Figure 1 presents the block diagram of the device; 2 and 3 are functional diagrams of a transmitter and a receiver; respectively; in fig. 4 and 5 are flowcharts of algorithms for servicing information input and output cycles.

The device (FIG.) Contains an amplifier unit, a priority node 2, a breakout address register 3, an address decoder 4, a switch 5, a command decoder 6, a frequency generator 7, a transmitter 8, a receiver 9 and an encoder 10,

The transmitter 8 (figure 2) contains a linear block 1I of the main transmitters, trigger 12 states of the transmitter, trigger 3 operating modes, counter 14 synchronization, the first, second elements 15 and 16, the element NOT 17, counter 18 high-low pulses, the third element And 19, reset decoder 20, shift register 21, fourth AND element 22, burst decoder 23, encoder control trigger 24, outputs 25 of the buffer registers 26 of the output group, data switch 27,

Receiver 9 contains (fng.Z) linear block 28 of main receivers switch 29 of the input signal, first element 30, synchronizing pulse counter 31, synchronization trigger 32, counter 34 of pulsed pulses, second and third elements 34 and 35 clock input 36 receivers, trigger input input 37, per: shift gistor 38, reset decoder 39, select decoder 40, select buffer registers 40, group input buffer registers 41, data switch 42.

The drawings also denote the channel 43 of the input-output of the computer and the subscriber 44 outputs 45-50 and inputs 51-54 of the transmitter 8, outputs 55 and 56, and the first information and control inputs 57

01

Q

five

0 5

about Q

0

five

72

and 58 receiver 9, lines 59-63 of the device's connections with channel 43.

Block 1 performs the matching of the signal levels of channel 43 and the device.

The priority node 2 is designed to generate a signal for breaking demand and control signals for the breaking address register 3, which is used for transmitting the address of the interrupt vector vector to the digital computer.

The decoder 6 commands determines the mode of operation of the device, depending on the address of the computing machine to the device.

4 clock frequency generator incl. It includes, for example, a quartz-stabilized oscillator and a frequency divider, implemented on integrated circuits of counters, and provides for varying the speed of information exchange through an exchange channel.

The transmitter 8 serves for the output of information, and the receiver 9 for the input of information into the device from the subscriber.

The encoder 10 may be implemented in the form of, for example, a persistent storage device and allows the transfer of coded information to one or more devices.

The transmitter line unit I1 serves to match the levels of the signals transmitted from the device to an external object.

Counter 18 serves to count the number of pulses transmitted from the device.

The decoder 20 reset serves to ensure the cyclical operation of the counter 14 and the entire transmitter 8 as a whole.

Transmitter shift register 21 is configured to convert parallel code to serial.

The control encoder trigger 24 serves to generate a control signal for block 10. If the trigger is set to one, then the permissive signal is allowed to exit 49.

Buffer registers 26 (total M registers, registers) are used to store information intended for transmission from a computer to an external device.

Line unit 28 serves to match the signals received by the device from an external device.

13

Counter 31 serves to delay the clock signal - 1l relative to the information one, counter 32 - to count the number of pulses introduced.

The trigger 37 serves to indicate the status of the buffer registers, the register 38 to convert the serial code of the input information to parallel.

The operation of the device is based on the principle of converting a parallel code received from a computer into a serial or some other parallel code, transmitting it to a device or user devices, as well as receiving a serial code transmitted by a user device and converting a serial code into a parallel code with subsequent transfer last in the computer.

The device works as follows

When the computer accesses an external object through the device. it in line 63 brings the address through block 1 to the input of the decoder 4, which allows the decoder 6 to function at the address npassfflbHOM address.

Mode yt. Solvency is determined by three lower address bits. These signals are fed to the code input of the decoder 6.

Priority node 2 and interrupt address register 3 are designed to generate a signal for interruption request and to transmit the address of the interruption vector address. As soon as the device is ready to enter data into the computer, on the forward trigger 37 a low logic level appears that is active for node 2. In response to the ready signal, the node 2 generates an interrupt request signal on line 59 the computer (VM) sends an interrupt acknowledgment signal on line 62, In response, node 2 removes a signal from line 59 and generates signals, the first of which allows information to be transferred to register 3 via lines 60 in VM, the signal from the third output of node 2 carries information about pr Chi- not prershani: willingness device to input information in VTR or vshod therefrom. A signal of readiness of the unit goes to node 2 when it arrives at

50

five

...

five

0

five

7

direct output trigger 12 low logic level.

When the trigger 12 is in the zero state, the recording signal from the output of the decoder 6 is passed through line 53 through the element 19 to the record entry of the counter 18. In this case, the state 18 of the output 1 of the block 1 is written to the counter 18. the number of one of the M buffer recorders of the output 26, in which the next piece of information intended for the output should be written. Writing to registers 26 is carried out at a corresponding value at the code input of the decoder 23 and upon receipt of a signal on the line 52c of the output of the decoder 6.

After filling the buffer registers 26 to enable the transfer of information, it is necessary to set a single logic level at the output of trigger 12. In this case, the passage of pulses from generator 7 to the input of counter 14 is permitted. As long as the number of output pulses is less, for example, seven, the output of counter 14 is a low logic level and the passage of shift pulses in register 21 is allowed. At that, as soon as the number of output pulses will be equal to 8, the decoder 20 resets the counter 14, and the decoder 23 generates an active signal to output the data from the registers 26 through the switch 27. They are written to the register 21, because a reset pulse is generated at the output of the counter 14 C in register 21. When all information from registers 26 passes through register 21, the output of decoder 20 produces an active signal that determines that the value of counter 18 is equal to the maximum number of bits that can be written to registers 26. This signal decoder 20 will reset to the zero state triggers 12 and 24, which reflects the readiness of the transmitter 8 to receive new information from the VM. Triggers 13 and 24, as well as trigger 12, are installed from the VM. The trigger 13 in the single state enables the linear block 11 and commutes data from the output of the linear block 28 through the switch 29 to the input of the register 38. The trigger 13 in the zero state prohibits the transmission of data through the block 11 and

switches data from the output of the register 21 to the input of the register 38 through the switch 29.

The trigger 24 in the single state allows the control pulse of the encoder 10 to pass, thereby allowing ei o operation. The trigger 24 in the zero state prohibits the operation of the encoder 10.

When the starting block arrives at the input (it arrives at the input of the AND 30 element with a logical zero), counter 31 starts working - synchronization20

25

thirty

35

reception torus. At the bit interval, a transmitter consisting of a trigger of the information pulse at its output appears a pulse that sets the trigger 32 and simultaneously controls the input of the information bit into the register 38 and the count of the pulses entered into the device into the counter 33.

The input data sequence from the output of the linear unit 28 through the switch 29 is written to the register 38 under the control of the shift pulses received through the counter 31 from the output of the generator 7. After receiving the next eight information bits, they are written from the shift register 38 to one of the buffer registers 41, number which is defined as a number equal to the number of transmitted pulses taken modulo 8, i.e. the information byte is written to a separate input buffer register. It is selected by the decoder 40 upon receipt of the next information byte based on the readings of the counter 33.

After the buffer registers 41 are filled with a signal from the output of the decoder 39, the flip-flop 32 is reset and the flip-flop 37 is set to O, which is a sign that the received registers are in the buffer registers 41. At the output of the trigger 37, a passive signal appears that prohibits further counting of the counter 33 and permits the recording of information into it on line 54 from the output of the amplifier unit 1, which is used as the address of the buffer register 41 when reading information from the device to the VM. After selecting the buffer register 41, the data is received through the switches 27 and 5 to the input of the amplifier unit 1. Upon termination of the received information from the buffer registers 41 signal on

40

45

50

55

Pa- rages of the status, trigger of the operation mode, synchronization counter, two AND elements, NOT element, reset decoder, group of output buffer registers, line block of main transmitters and shift register, and receiver, switching on the line block of main receivers, input switch , two AND elements, clock counter, shift register, input state trigger. A trigger trigger, a group of input buffer registers and a reset decoder, the first input and output of the amplifier unit are connected respectively to the switch output and information inputs of the address decoder, command decoder and transmitter, the second output of the amplifier block is a device output for connecting the I-channel channel information lines Computer, the second input of the amplifier unit is the device input for connecting to the information lines of the input-output channel of the computer, the first output of the priority node is the output The device for connecting with the request line for interrupting the AMI I / O channel, the second and third outputs of the priority node are connected respectively to the control and information inputs of the address address register, the control input of the priority node is the device input for connecting to the input channel interrupt enable line output of the computer, the output of the address register is the output of the device for connection to the infogmation lines of the input-output channel of the computer, the output of the address decoder is connected to the control input of the remote Rathore commands, command decoder output group coupled to the first control input of the receiver.

line 58 of the output of the decoder 6 sets the flip-flop 37 into a single state, which corresponds to the resolution of receiving information via the I / O channel line.

Claims (1)

Invention Formula A device for information exchange, comprising an amplifier unit, a switch, a priority node, an interrupt address register, an address decoder, a command decoder, a clock clock generator one transmitter consisting of a trigger Pa- rages of the status, trigger of the operation mode, synchronization counter, two AND elements, NOT element, reset decoder, group of output buffer registers, line block of main transmitters and shift register, and receiver, switching on the line block of main receivers, input switch , two AND elements, clock counter, shift register, input state trigger. A trigger trigger, a group of input buffer registers and a reset decoder, the first input and output of the amplifier unit are connected respectively to the switch output and information inputs of the address decoder, command decoder and transmitter, the second output of the amplifier block is a device output for connecting the I-channel channel information lines Computer, the second input of the amplifier unit is the device input for connecting to the information lines of the input-output channel of the computer, the first output of the priority node is the output The device for connecting with the request line for interrupting the AMI I / O channel, the second and third outputs of the priority node are connected respectively to the control and information inputs of the address address register, the control input of the priority node is the device input for connecting to the input channel interrupt enable line output of the computer, the output of the address register is the output of the device for connection to the infogmation lines of the input-output channel of the computer, the output of the address decoder is connected to the control input of the remote Rathore commands, command decoder output group coupled to the first control input of the receiver. 713 with the first and second control inputs of the transmitter and with the group of address inputs of the switch, generator output clock frequencies connected to clock the transmitter and receiver inputs, the first transmitter output is the output of the device for connecting to the subscriber's input information line, the second transmitter output is connected to the first information inputs of the priority node and the switch, the third transmitter output is connected to the second information input of the switch, and to the second control input of the receiver, the fourth output of the transmitter is connected to the first information input of the receiver, the first output of the receiver is connected to the third: - the information is the input of the switch, the second output is The terminal is connected to the fourth information input of the switch and the second information input of the priority node. In the transmitter, the output of the linear block of the trunk transmitters is the first output of the transmitter, the forward output of the output state trigger is connected to the first input of the first element I and is the second output of the transmitter, output the operating mode trigger is connected to the control input of the line unit and is the transmitter output, the output of the synchronization counter is connected to the input of the element NOT and to the recording input of the register The transmitter shift source, the output of the first element I is connected to the control input of the synchronization counter, the output of the second element I is connected to the syncro input of the shift register, the output of the element is NOT connected to the first input of the second element And, the first output of the reset decoder is connected to the reset input of the synchronization counter, and the second output - with the reset input of the output state trigger; the output of the shift register is connected to the information input of the linear block of the main transmitters and the fourth output of the transmitter; the second inputs of the first and second AND elements are connected to the clock input of the transmitter data inputs of the flip-flop output state and mode of operation a trigger connected to data input and data inputs of the transmitter buffer register group output clock terminal of flip-flops and the output state operating mode trigger connected to the first 0 five 0 01 s 25 0 7 " the control input of the transmitter, and in the receiver the first and second information inputs of the input switch are connected respectively to the output of the linear block of trunk receivers and the first information input of the receiver, the first input of the first element I is connected to the information input of the shift register and the output of the input switches, whose address input is the second control input of the receiver, the output of the first element I is connected to the reset input of the clock counter, the synchronous input of which It is a clock input of the receiver, and the output is connected to the control input of the shift register, the setup input of the synchronization trigger and the first input of the second element AND, the second input connected to the second output of the receiver and the forward input of the input trigger, the setup input of which is the first the control input of the receiver, and the reset input is connected to the reset input of the trigger of synchronization and the output of the reset flusher synchronized input connected to the output of the trigger of synchronization and the second input of the first element the format inputs of the buffer registers of the group are connected to the output of the shift register, different by that that, in order to increase the speed of information exchange, an encoder was entered into the device, two AND elements were entered into the transmitter, an output pulse counter, a selector decoder, an encoder control trigger and a data switch, and a data switch, an input element counter and a third element AND, the fifth and sixth outputs of the transmitter are connected respectively to the synchronization and information inputs of the encoder, the output of which is the output of the device for connection to the address input of the subscriber, the second information The receiver input is the device input for connecting the subscriber's information output, the third receiver and transmitter control inputs are connected to the additional output of the command decoder, the third receiver information input is connected to the first output of the amplifier unit, the first and second inputs in the transmitter the third element. And connected according 9133 with the inverted output of the trigger state of the output and the third controlling input of the transmitter, and the output with the write input of the output pulse counter, the synchronous input and information inputs of which are connected respectively to the output of the second And element and the information input of the transmitter, the address input of the data switch connected to the output of the output pulse counter and information inputs of the reset decoder and select decoder, the group of outputs of which is connected to the synchronous inputs of the corresponding buffer registers, output They are connected to the group of information inputs of the data switch, the output of which is connected to the sixth output of the transmitter and the information input of the shift register, the reset input of the encoder control trigger is connected to the second output of the reset decoder, and the sync input and output respectively to the first control input of the transmitter and the first input of the fourth element And, the second input and output connected respectively to one 7-10 the output of the element NOT and the fifth output of the transmitter, the synchronous input desh,) of choice is the second control input of the unit, and in the receiver the information input of the linear block of the trunk receivers is the second information input of the receiver, the first and second inputs of the third element And are connected respectively to the third the control input of the receiver and the inverted output of the trigger input state, and the output to the write input of the output pulse counter, the synchronous input and information inputs of which are connected respectively to the output in The second element And and the third information input of the receiver, and the output with information inputs of the selector decoder and reset decoder AND address input of the data switch, the output and group of information inputs of which are connected respectively to the first output of the receiver and the outputs of the buffer input registers of the group, the sync inputs of which are connected to the group outputs decoder choices Screw fneHymut number cvum / faf-noy buffer register tda (bddy} Cvuirtaatb byte uHtpopffaifuu u) Bfibri and evum on Sifcfx SP && Set (er „number SP & B pQSvt / iiO Run npozpOMMU offsai m qianagpopo g /% yg / 4w J Allow SSod HOffoa u gjopno uu SycmfloilcmKi tanodit trigger cocfnof i / Jf ffffoaa f effuMtfVHOf state Start ±. Stop decide nepeoawuMjiqp nation trigger / retima oaffomttu Vgv u / woffffarnoDOM Zadot1 peeucmpa write it down. byte, inform about oiitopOMjfb / u b fa I / poanma See N, yeffamo Hova / itHbtiJ WHep jL one - - Allow IMPORTATIONS to set the condition trigger ffu / fffffa ff effuffuwoe state Editor L.Gratillo j KoHeij I Figure 5 Compiled by V. Vertlib Tehred M.Didyk Proofreader M.Demchik Order 4813 Circulation 670 Subscription VNISHI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 start / about y., i ge / iuvumb o- fiep BftSB / (one FIG. it  ermooe (iRb} I s see n, Increase number BRV