SU1676068A1 - Universal binary cell - Google Patents

Abstract

The invention relates to a pulse technique and can be used in the construction of various devices for discrete information processing. The aim of the invention is to simplify the universal binary cell. A universal binary cell contains three two-emitter transistors, three transistors, four resistors and two diodes. The introduction of new links allows us to simplify the universal binary cell while maintaining the functions performed. 1 il.

Description

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The invention relates to a pulse technique and can be used in the construction of various devices for discrete information processing.

The aim of the invention is to simplify the universal binary cell.

The drawing shows a circuit diagram of a universal binary cell.

The universal binary cell contains three two-emitter transistors 1–3, transistors 4–6, resistors 7–10, diodes 11 and 12, first 13 and second 14 outputs, inputs 15 and 16 of the reset unit, clock input 17, and power supply 18.

The collector of the multi-emitter transistor 3 is connected to the base of the transistor 3,

the collector of which is connected to the collector of transistor 6 and the base of transistor 5, the collector of which is output 13 and connected to the emitter of transistor 3, whose base through resistor 9 is connected to power supply 18, which through resistor 10 is connected to collector of transistor 4, the emitter of transistor 3 is connected the emitter of a tozistopoa 6 and the clock input 17. The emitters of transistors 4 and 5 are connected via diode 11 to a common bus, the base of transistor 6 is connected to the collector of transistor 1 to the first terminal of resistor 7 and the base of transistor 2, connected to a first terminal of resistor 8 and the base of transistor 1, the second terminal of the resistors 7 and 8 are connected to the power bus 18. The second emitters of transistors 1 and 2 are connected via diode 12 to a clock input 17. The first emitter of transistor 1 is

ON

X8 O O O

input is set to 15, and the first input of transistor 2 is reset input 16.

When the universal cell is operating in counting mode, output 13 is connected to input 15, and output 14 is connected to input 16 of a memory trigger (shown in dotted lines in the drawing).

The universal binary cell operates as follows.

First, consider the work of the cell as an RSt trigger.

In the initial state, there is a signal at input 17 and signals acting at inputs 15 or 16, since diode 12 is constantly open and transistors 1 and 2 are open.

The inputs 15 and 16 are given a combination of signals,. With the arrival of a pulse at the input 17 (), the diode 12 closes and, since both emitters of transistor 1 operate with high level signals, this transistor 1 closes. After the clock pulse ends, the transistor 6 (at its base is high) turns on and transistor 5 closes (because the collector of transistor 6 is connected to the base of transistor 5 when the transistor 6 is opened at the collector of this transistor and accordingly at the base of transistor 5 is low). As a result, state 1 () is set at output 15. In the state O (), the cell is set by a combination of the signals at the inputs 16 and 15 R 1, S 0 after the clocking pulse expires. The combination of S R T 1 signals for this trigger device is prohibited.

To organize the counting trigger, it is necessary to connect the outputs 14 and 13 to the inputs 16 and 15, respectively.

Claims (1)

Invention Formula A universal binary cell containing two diodes, the first emitters of the first and second two-emitter transistors are connected respectively to the installation and reset inputs, the bases are connected to the collectors of the second and first two emitter transistors, respectively, and are connected via the first and second resistors to the power bus, respectively, the base of the third two-emitter transistor is connected via the third resistor to the power bus, the collector to the base of the first transistor, the emitter of which is connected to the common bus through the first diode and connected to the emitter of the second transistor, the collector of which is connected to the first emitter of the third transistor, the first output of the fourth resistor is connected to the power bus, the emitter of the third transistor is connected to the clock input, the collectors of the first and second transistors are connected respectively to the first and second outputs, characterized in that simplification, the second emitters of the first and second two-emitter transistors through the second diode are connected to the clock input and the second emitter of the third two-emitter transistor, the collector which is connected to the second output of the fourth resistor, the base of the second transistor and the collector of the third transistor, the base of which is connected to the collector of the first two-emitter transistor. 17 12