SU871332A1 - Delay device - Google Patents

Description

(54) DELAY DEVICE

Claims (2)

 The Tz invention relates to a pulse technical and can be used to delay the pulses while maintaining their polarity, as a simple and economical time relay in devices that are under voltage for a long time, provided that the current consumption is minimal (in particular, in anti-theft devices) in automation devices to provide a greater range of time delay adjustment. Delay devices are known that contain a p-rvp-type transistor with one time driving capacitor, an additional and additional rv-p-n type transistor {1b. The drawbacks of the device are its complexity, a large number of elements, and the need to use an additional control source. voltage to set the delay time. The disadvantage is the current consumption of the device in standby mode. In addition, to set the delay time, the full discharge voltage of the driving capacitor is not used, since the control voltage is transmitted to the emitter of the control transistor and thus the driving capacitor time is present in the discharge circuit, which leads to its incomplete discharge do A device containing a transistor, an operational amplifier, a timing circuit, resistors and a diode is known. The drawbacks of the device are the current consumption in standby mode, the need to use two power sources, and the use of an expensive element (onyote-amplifier amplifier). In addition, the polarity of the voltage on you-. the course of the device does not correspond to the polarity of the input. The aim of the invention is to simplify the device and reduce current consumption in standby mode. To achieve this goal, a delay device containing a key, a serial RC circuit, a voltage divider connected between the power bus and a collector of a key transistor, two transistors of different conductivity types, whose emitters are interconnected, have a transistor of p-conductivity connected to the connection point of a capacitor and a resistor of a series RC circuit The base of the transistor p p-p Conductivity is connected to the connection point of resistors of a voltage divider, and the collectors of pnp and pp-conductivity transistors connected respectively to the power supply and to the load. The drawing shows a circuit diagram of the device. The device contains a switch 1 on a transistor, a serial PC circuit consisting of a capacitor 2 and a resistor 3, a voltage divider on resistors 4 and 5, two transistors 6 and 7, and a load 8. The delay device works in a sensible way. Before the trigger pulse arrives at the input of the device, transistor 6 is open and key 1 and transistor 7 are closed and the device does not consume current (1 ((o is not taken into account)). At the time key 1 is opened, one of the terminals of capacitor 2 and resistor 4 is closed to the case. In this case, the transistor 6 is closed, and in the base of the transistor 7 a voltage is set, which is determined by the ratio of the resistors 4, 5 of the voltage divider and transmitted, respectively, to the emitters of the transistors 7, 6. The charge of the capacitor 2 starts through the resistor 3 in the closed transistor 6. At the moment when the voltage of the capacitor charge begins to exceed the voltage set in the em-ra of transistor 6, it opens and a voltage of the same polarity as the input appears at the output of the device, but with a certain delay. Thus, as can be seen from the device circuit, the delay time can be set not only by changing the elements in it - the master NS circuit, but also by setting the appropriate pattern in the base of transistor 7, since depending on the level of this voltage the transistor will open earlier or later . This feature of the device makes it possible to establish such a voltage in the base of transistor 7, in which transistor 6 opens only after the almost complete charge of capacitor 2. This means that the utilization rate of apr of charge capacitor to set a certain delay in such a device is equal to 1. The proposed device, in contrast to the known ones, is simple, economical - it does not consume current in the standby mode, it is convenient to operate, since the voltage at its output is of the same polarity as the input. This will make it possible to exclude the use of additional circuits for setting the polarity of the output voltage of the corresponding polarity of the input voltage. The device does not require additional power sources. In addition, when a certain delay time is set, the proposed device has minimal dimensions, since it allows maximum use of the charge time of the driving capacitor, which makes it possible to apply the most optimal values of the resistor and capacitor capacitance to the driving time. The device also has a large range of time delay adjustment. Claim device A delay device containing a key on a transistor, a series NF circuit, a voltage divider connected between a power line and a collector of a key transistor, characterized in that, in order to simplify the device and reduce current consumption in a standby mode, two transistors are inserted into it of a different type of conductivity, the emitters of which are interconnected, the base of the pnp-conductive transistor is connected to the junction point of the condensate and the resistor of a series RC circuit, the base of the transducer: It is connected to the connection point of the voltage divider resistors, and the collectors of the np and np conductivities of the transistors are connected to the pitsch and to the loads, respectively. . Sources of information taken into account in the examination 1. The author's certificate of the USSR M 233007, | cl. H 03 K 17/28, 09/25/67 2. USSR author's certificate N 600730, cl. H 03 K 17/28, 04.12.74 (prototype). €) fy If