SU1256183A1 - Pulse sequence-to-rectangular pulse converter - Google Patents

Abstract

The invention can be used in the construction of digital signal processing devices. The purpose of the invention is to unify the device for building on elements of any series due to the fact that a switch 2 and a resistor 5 are inserted into the converter containing a trigger 3 and a capacitor 6, and the trigger 3 is made in the form of a D-trigger. Key 2 can be performed, for example, on a bipolar transistor. 2 Il. J7 C / (L ate O5 00 SAD ig. /

Description

The invention relates to a pulse technique and can be used in the construction of digital signal processing devices.

The purpose of the invention is to unify the device for building on the elements of any series.

FIG. 1 shows the electrical functional scheme; in fig. 2 - time diagrams of work.

The device contains an input bus 1 connected to the control input of the key 2 and the clock input of the D-flip-flop 3, the output of which is connected to the output bus 4 and through a resistor 5 to the R-input of the D-flip-flop 3, the analog input of the key 2 and the first capacitor plate 6, the second plate of which is connected to the output of the key 2 and the common bus, the D-input of the D-flip-flop 3 is connected to the source of the logical unit.

A pulse train to a square pulse converter operates as follows.

In the initial state, before the input pulse sequence enters the input bus 1, the D-flip-flop 3 is in the zero state, the capacitor 6 is discharged. The first pulse of the input sequence (Fig. 2a) switches the D-flip-flop 3 to one state (Fig. 2c), the switch 2 is turned on for the duration of the pulse, which ensures full discharge of the capacitor 6 (Fig. 2b). The RC time constant is chosen so that during the time between the pulses of the input sequence, the capacitor 6 does not have time to charge to a voltage corresponding to the trigger threshold of D-flip-flop 3 at the R input. The constant time can be selected in such a way that the device reacts to the disappearance of one or several pulses of the converted sequence. Thus, by the arrival of each subsequent pulse, the voltage on the capacitor 6 does not have time to reach the trigger threshold of the D-trigger 3 at the R input and is discharged to zero through the key 2 under the influence of

input pulses, while the D-flip-flop 3 is held in the unit state all the time while the input bus 1 contains the input pulses, the duration of which is not critical for the normal operation of the device. At the end of the input pulse sequence of deviations from its nominal value or in the absence of pulses at the device input during a time interval equal to or slightly longer than the pulse period, the voltage on the capacitor 6 has time to rise to the D-trigger level 3 at the R input (Fig. 2b and D-flip-flop 3 is set to the initial zero state (Fig. 2c).

The key 2 can be performed, for example, on a bipolar transistor, the base of which is connected to the input bus through a resistor, the emitter to the common bus, and the collector 0 to the D input of the D flip-flop 3, or on chips 564 KTZ, 564 KP2, 590 KH1.

The proposed device has wider applications, since it can be implemented on a series of chips

all technology.

Claims (1)

Invention Formula A pulse train to a rectangular pulse containing an input bus, a trigger, which is connected to an output bus, a capacitor, the first output of which is connected to a common bus, characterized in that, in order to unify the device, the trigger is made in the form of a D-trigger and entered the key and the resistor, the first output of which is connected to the output bus, and the second - to the second output of the capacitor, the R-input of the D-flip-flop and the analog input of the key, the output of which is connected to the common bus, the control input to the input bus and C-input D - three ger, D-input of which is connected to a source of logic-one. 0 0