SU1673981A1 - Speed measuring device - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in process control systems for controlling the speed of movement of working bodies. The purpose of the invention is to simplify the device and increase its speed. The essence of the invention is that the range of measured frequencies is divided into sections within which a given accuracy is provided for a certain generator frequency, and the generator is a pulse generator 3 and a controlled frequency divider 4, in which, depending on the measured speed, is set automatically within one to two pulse periods from displacement transducer 1, which increases the speed of the device. The use of controlled generators 9, 10, 11 digital codes, shift register 8, code comparison circuit 12, zero state decoder 13 significantly simplify the device circuit. 4 il.

Description

with

WITH

The invention relates to automation and computer technology and can be used in process control systems for controlling the speed of movement of working bodies.

The purpose of the invention is to forgive the device and improve its speed.

Fig. 1 shows a block diagram of the device: Fig. G shows schematic diagrams of a controlled divider, a controlled code generator, and a shift register; FIG. 3 shows the dependence of the speed of movement of the movable organ on the period of the pulse following the output of the sensor; figure 4 is a timing diagram of the operation of the device in the high range.

The device (Fig. 1) contains a displacement transducer 1 with a pulse output, co-wired with a movable member 2,

the speed of movement of which measures c. The device also includes a pulse generator 3, a controlled divider 4 pulse frequency, a decimal subtractive counter 5, an indication register 6, a digital indicator 7, a shift register 8, the first 9, the second 10 and the third 11 controlled digital code generators, the circuit 12 code comparisons, the zero state decoder 13, the first 14, the second 15 and the third 16 elements OR the first 17 and the second 18 delay elements, the synchronization circuit 19 and the Start button 20 for two.

VnpaenfleMb divider 4 (Fig. 2) consists of two microcircuits 21, 22 of type K155 AND С С and an inverter 23, for example, of type К 155 ЛН1.

Controlled Code Generator 9 (to implement the initial conditions in accordance with

VI

00 O 00

Vii with fig. 3) consists of a group of elements OR 24-28 and commuting circuits.

The shift register 8 consists of a chip 29 of type 155 IR2, D-flip-flop 30, for example, type 155 MT1 and two inverters 31 and 32, for example, type 155 LN1.

The device works as follows.

The resolution of the sensor 1, as well as the register width 8, the values of the codes of the code generators 9, 10, 11 and the pulse frequency from the output of the generator 3 are determined by the purpose of the device. Suppose a device is used to measure the speed of movement of a press punch in the range of 6-120 mm / min with an accuracy of ± 10%. In this case, for example, a DDR-10 type sensor with 256 counts per shaft rotation can be used as sensor 1.

When mechanically coupling the sensor 1 with the punch, for example, using a roller with a diameter of 60.6 mm and an increase gearbox with a reduction factor of three, the resolution of sensor 1 is

tg-d

datch

Cred Pdatch

 0.25 mm

Fig. 3 shows the dependence of the speed of movement of the movable organ 2 on the period of the pulse following from the output of the sensor 1.

For convenience, the hyperbolic function is represented in two scaling areas: in the speed range 6-28 mm / min, the period axis Ta, and in the range 28 ± 120 mm / min - OST TB

The hyperbolic function is represented in the form of a tube with a predictable error (10%). Within this tube, a piecewise linear approximation was made, which allows replacing the hyperbolic function with a piecewise linear one.

In FIG. 3, it can be seen that the required accuracy is ensured by four segments of a linear function with points of inflection corresponding to the speeds of movement of the moving member: 12, 28 and 60 mm / min. The table shows the results of processing the graph of the function in FIG. In the table:

V / min is the minimum speed range,

VMBKC max speed range,

Ti is the period (s) of the sensor pulses following the VMHH;

T2 - the period corresponding Umeks.

- | 1-: 10- | V T2-; 1 MOHaracteA V | X / Max - VMHH I

the slope of the linear approximation region, dividing by ten reduces

rounding error in hardware implementation.

The calculated value of the initial velocity of the range is used as the initial value by which

subtracting the current speed value, determined by the pulse period of sensor 1, determines the true speed. Graphically (Fig. 3), VBepx is a conditional point on the continuation of the approximation segment. In the formula for Veepx 2Т2, the time interval corresponding to the higher ranges (Fig. 3), i.e. if, for example, the VDepx value is calculated for the first range,

It is necessary to take into account the time corresponding to T2 of the second, third and fourth ranges. For the fourth range

25

,

,one

f Zak - the estimated frequency of the pulse following, arriving at the counting input of the counter 5 when measuring the period, in the range

30,, 1

f:

AT / AV: 10

Hz:

KI, K2 are the multiplication factors of the cascades of the controlled divider 4 (fit 2):

f3aH is the real pulse frequency at the output of divider 4, taking into account Ki and K2.

After turning on the device, the Start button 20 is pressed (Fig. 1). C signal

the button's output sets the decimal counter 5 to zero. The decoder 13 of the zero state of counter 5 produces a signal that, through the OR 15 element, sets the controlled frequency divider 4 to the zero state and, having entered the input of the zero register of the display 6 , also sets it to the zero state, as a result of which indicator 7 will

display zero speed. The signal from the button 20 through the element OR 14 is also fed to the synchronized input of the synchronization circuit 19, but since the mobile unit 2 is in

alone, then from the output of sensor 1, the signals to the clock input of circuit 19 are not received and there is no signal at its output. When the body 2 moves due to its mechanical connection with the displacement sensor 1

the sensor begins to produce pulses, the frequency of which is determined by the speed of movement of the organ 2, and their number is the value of the distance traveled. After the organ 2 begins to move, the first pulse from the output of sensor 1 is fed to the control input of the write register of indication b, but does not change its state, since the counter 5 is in the zero state, while the pulse from the output of sensor 1 goes to the synchronizing input of the synchronization circuit 19, and the signal from its output through the OR element 15 is fed to the R input of the controlled divider 4, without changing its initial state, the pulse from the output of the synchronization circuit 19 also affects the input of the Shift Register 8, and at its output sets d 1000 corresponding to the control of the operation of the device in the fourth range (fig.Z). The pulse from the sensor output through the delay element 17 and the OR 14 element is also fed to the synchronized input of the synchronization circuit 19. The device is automatically prepared for operation in the next speed measurement cycle when each successive pulse is received from the sensor 1 output. After setting the output code of register 8 to the initial code 1000 controlled code generators respectively generate: code generator 10 binary code 00000 010011, corresponding to the value Ki 0, “2 19 according to the table;

code generator 9 - binary-decimal code 0001 1001 1000 0001, corresponding to the value of Voepx 1981 according to the table;

- code generator 11 - binary-decimal code 0110 0000, corresponding to VMMH 60 of the fourth range in the table.

After installing the codes on the outputs of the 9, 10, 11 code generators, a pulse from the output of the synchronization circuit 19 through the OR 16 element delayed by the element 18 affects the input of the counter 5, as a result of which the generator code 9 is recorded in the counter 5, the output of the decoder 13 is zero neither disappears, the controlled divider 4 begins to generate pulses with the following frequency f 6250 Hz (Fig 4), the counter 5 starts to work on the subtraction. If the speed of movement of the organ 2 is within the highest range, then the second pulse from the output of sensor 1 will be generated earlier than the comparison signal of the circuit 12, which fixes the range limit. At the same time, the pulse from the output of sensor 1, arriving at the input

replays the measured speed code into the display register 6 from counter 5, the display 7 will display the speed value, the code of which also goes to

5 output devices for use, for example, in automated control systems. Let, for example, the speed of the organ 2 be 80 mm / min. After the value VBepx 1981 is written to the counter 5, the counting input of the counter 5 will arrive at the measurement period T 0.187 s (Fig. 3).

pulses m d 7 / vT7-Tn 810, the indicator displays the value of three

15 senior bits (dividing compensation by 10), i.e. on the indicator V 81 mm / min (error 1.25%).

Consider the case when the measured speed belongs to the youngest first

20 range, for example V 7 mm / min. In this case, after the sensor 1 has generated a pulse, the first one after pressing the Start 20 button, and starting the subtraction cycle from the counter, 5 pulses with a frequency of f 6250 Hz

25, when the counter reaches 5 of the speed code corresponding to the boundary of the fourth range (V 60 mm / min, see table), the comparison circuit 12 operates. The pulse signal from its output goes to the input 30 of register 8 and shifts the 1000 code to the right (Figure 2), the output of which at the output of register 4 is set to shoe 0) 00, corresponding to the control of the device operation in

35 third range (fig.Z). As a result, the controlled divider 4 generates pulse sequences with the following frequency f 105G Hz, corresponding to the third range.

40 An output signal from the output of the comparison circuit through the OR element 16 and the delay element 18 is fed to the input of the write control of the counter b in which the record is written; t- with - od Veepx of the third range.

45If the measured speed is lower than gr, the first range, then the counter 5, when subtracted, reaches the state O, the decoder 13 of the zero state sets the zero state to the zero state

50 display register 6, and divide / g. 4 is set to zero and the zero state of the AND 15 element on the indicator 7 will be indiirovsg zero -e velocity value.

Controlled frequency splitter 4 (flash 2;

55 rnbotat in accordance with the func tioning of 1b5 and e8 chips, on which it was assembled. In this case, the chip 21 forms a division stage of the output frequency frPH of the generator 3, and the chip 22 forms a frequency division stage -f freM. entering her

B4

from output P of chip 21,

The division ratio of the chip 21 Ki 2a12. and microcircuit 22 К2 2Ы2И, where ai - values of binary bits of the control code at the inputs V1-V6 of microcircuit 21; bi is the code bit value at the V1-V6 outputs of the microcircuit 22. The output frequencies of the microcircuits 21 and 22 are summed up on the microcircuit 21 by transferring the output frequency from the output of the microcircuit 22 to the C1 input of the microcircuit 21.

Total frequency fg freH

64

f

K2

from the output of chip 21 through

4096

the inverter 23 is fed to the input-output of the divider 4 and then to the input of the counter 5 (figure 1).

The controllable code generator 10 operates as follows.

In accordance with the decimal representation of the coefficients Ki and Ka of the controlled divider 4 (see table), for each of the four segments approximating direct (Fig. 3) the binary representation of these coefficients will be: for the first section Ki O, K2 2 ° + 21 + 2. for the second section Ki 2 °, Cs 21 + 24 + for the third section Ki 21 + 22; Kg 2 ° + 22 +24; for the fourth section, Ki 23 + 25; K2 - 0.

Thus, the controlled code generator 10 is a multiplexer 4 12, where 4 is the number of input signals, determined by the number of segments of the approximating polyline (Fig. 3), and 12 is the number of inputs of the controlled divider 4, and. accordingly, the number of outputs of the controlled code generator 10. The multiplexing of input signals into output signals is carried out by switching directly by conductors or through the elements OR 24-28.

The shift register 8 (figure 2) operates in accordance with the operation of the chip 29 type 155 IR1. In this case, upon receipt of a signal, the Recording from the synchronization circuit 19 is first set to the S state by the D-flip-flop 30. By which means the chip 29 is prepared for recording the code 1000 from the inputs A1-A4. and then with a delay due to the passage of the signal through the inverter 31, the code 1000 itself is recorded. Through the inverter 32 signal, recording the negative polarity on the trailing edge transfers the trigger 30 to the R state and the signal from its output, arriving at the V input of the microcircuit 29, prepares it to shift the information when the signal is received Shift from the comparison circuit 12 to the input C1 of the chip 29.

Thus, the control signal

the logical unit will sequentially shift from output F0 (after writing) to output P3.

Claims (1)

Invention Formula A device for measuring speed, comprising a displacement sensor with a pulse output, combined with a moving object of the object, a generator pulse, controlled frequency divider, decimal subtractive counter, display register, digital indicator and start button, the pulse generator is connected to the input of a controlled frequency divider, the outputs of which are connected to the input of the decimal subtractive counter, the discharge inputs of which are connected to the corresponding the inputs of the display register, the outputs of which are connected to inputs of the digital indicator and are external outputs of the device, characterized in that, in order to simplify the device and increase its speed, it is additionally introduced first, second and third controlled digital code generators, shift register, code comparison circuit, zero state decoder, synchronization circuit, first and second delay elements, first, second and third OR elements to two inputs, the first delay element input being connected to the output of the motion sensor by the control input of the recording of the register of the indication and the synchronizing the input of the synchronization circuit, the synchronized input of which is connected to the output of the first OR element, the first input of which is connected to the output of the first delay element and the second input to the button The start-up and the installation input to a zero-decoupling counter, the bit inputs of which are connected to the outputs of the first controlled generator of digital codes, the outputs of the second controlled generator of digital codes are connected to the inputs of the controlled frequency divider, and the outputs of the third controlled digital generator codes are connected to the first inputs of the comparison circuit, the second inputs of the comparison circuit are connected to the inputs of the zero state decoder and connected to the discharge outputs of the tenth subtraction counter, and ode third generator controllably coupled to digital codes the outputs of the shift register, to which the inputs of the first and second controlled digital code generators are also connected, the control input of the record of the shift register is connected to the first input of the second OR element, the output of the synchronization circuit and the first input of the third OR element, the second input of which is connected to the output of the comparison circuit codes and input shift control 4TMV.IO Formiroramie filling frequency b, (D, D; - ", 0p the shift register, and the output of this element OR through the second delay element is connected to the control input of the record of the tenth subtraction counter; the output of the second element OR is connected to the input of setting the controlled frequency divider to zero, and the second input of the second element OR is connected to the output of the zero state decoder and the input of setting the register to zero. 40 about, 2, i