SU1672458A1 - Computer-to peripherals input-output trunk interface unit - Google Patents

Abstract

The invention relates to computing and can be used in automated control systems and data collection with an increased number of peripheral subsystems connected to a common computer bus. The purpose of the invention is to increase the throughput, which is achieved through the hardware implementation of the preparation of the exchange between computers and peripheral devices in the mode of direct access to computer memory. The device contains two gain units comprising trunk transceivers, interrupt unit, multiplexer, address register, address selector, decoder, first and second status registers, control unit, fixed memory unit, memory address counter, address register, volume counter, and address counter, zero state decoder. 2 Il.

Description

The invention relates to computing and can be used in automated control systems and information gathering — with an increased number of peripheral subsystems connected to a common computer bus.

The purpose of the invention is to increase the throughput of the device ,,

Fig. 1 is a block diagram of a device for interfacing a computer with an I / O line of peripheral devices; Fig 2 is a functional diagram of the control unit

A device for interfacing a computer with an I / O trunk of peripheral devices (FIG.) Contains a first gain unit 1 containing trunk transceivers connected via bus 2 of the first input-output device to a computer bus interface, interrupt unit 3, multiplexer 4, address register 5 , address selector 6, descrambler /, first 8 and second 9 status registers, control block 10, fixed memory block 11, memory address counter 12, main transmitter 13, volume counter 14, address counter 15, zero state decoder 16 neither s oh unit G / amplification, containing trunk transceivers and connected to the inputs-outputs of external devices 18 by buses of the second device's input-output through trunk 19, bus 20 address-data, bus 21 of addresses of external devices (VU), bus

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22 VU data, VU state bus 23, output bus 24-26 and bus 2 / and 28 inputs of interrupt unit 3, active device synchronization bus 29, bus 30-33 inputs of the decoder / bus, 34 and 35 outputs of the decoder /, bus 36 of the input of the decoder /, bus 3 / -42 outputs of the control unit 10, bus 43-46 inputs of the control unit 10, bus 4 / WU state, bus 48, WU data, bus 49 of the WU address, bus 50, Input signal, bus 51 signals Output and bus 52 synchronization of the passive device

The control unit 10 (FIG. 2) contains triggers 53-60v elements And 61-63 one-shot 64, elements NOT 65-6 /, elements OR 68- / 1, distributors / 2 and / 3 pulses and generator / 4 clocks with

A device for interfacing a computer with an I / O trunk of peripheral devices operates as follows.

Using the standard cycle Output (microcomputer formulas Electronics NMS 11100.1 3.059.051 FD) in the first register 8 of the state, a request for direct access is recorded. Further, on triggers 53 and 54, the HE element 65 implements the standard common bus acquisition cycle Upon confirmation of the selection (signal on bus 38), the one-shot 64 generates a short pulse, which, passing through the element OR 6 to the trigger 55, starts the valve / 2, loading the original data from the constant memory current into the state register 9, register 5 addresses, 14 volume counter and 1 counters The 5 addresses, the last ninth signal from the output of the distributor / 2, the passage through the element OR 69 to the synchronous input of the trigger 56, triggers the distributor / 3, and through the element NOT 66 passes to the synchronous input of the trigger 5 /, which resets the triggers 58 and 59 one cycle of the work of the distributor / the standard cycle is executed. Input or Output of information between the computer and the control unit. Upon the arrival of the synchronization signal of the passive device to input 32, the current edge of the exchange is reset by the signal edge (signal SIL, passing through the elements OR 69 and NOT 66 to the synchronous input of the trigger 5 /, resetting the triggers 58, the I / O signal, and 59, the sia signal as well

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on a decay, a new exchange cycle is started (CIP signal, passing through the OR 69 element to the synchronous input of the trigger 56, starts the distributor / 3). Thus, the exchange between the control unit and the computer is performed until the volume counter 14 goes to zero. The state of the decoder 16 generates a signal on the bus 45 The end of the call, which enters the information input of the trigger 56, blocks the start of the distributor / 3, and through the OR 68 element to the synchronous input of the third trigger 55, launches the distributor / 2

After loading the volume counter 14, the Signal End signal is cleared and the signal from the ninth output of the distributor / 2 triggers the input or output cycle. The loading process and the exchange process are performed until the next load cycle in the state register 9 is written The end of exchange flag on bus 46. The signal on bus 46 The end of exchange enters through the input element AND 63 Reset the second flip-flop 54, resetting the signal on the bus 38 confirming selection, and also enters the input of block 3 interrupt, which performs the standard interrupt procedure Ani with issuing the interrupt vector, which is a sign of completion of the exchange computer with peripheral devices

Claims (1)

1. A device for interfacing a computer with an I / O trunk of peripheral devices, comprising a first gain unit, the first input-output of which is the input-output device for connecting to a computer trunk, interrupt unit, multiplexer, address register, address selector, decoder, first state register, control unit, trunk transmitter, volume counter, address counter, zero state decoder, second gain unit, the first input-output of which is the device input-output for connecting external devices STV, the second input-output of the first gain block via the address-data bus is connected to the information input of the address selector, to the output of the main transmitter, with the multiplexer output, with the information input of the first status register, with the second input-output of the second gain block, with the input of the interrupt vector of the interrupt block, the first output of which is connected to the input of the interrupt request of the first gain block, the second output is connected to the first information input of the multiplexer, the third the output of the interrupt block is connected to the control input of the multiplexer and to the first input of the decoder; the interrupt supply provision input of the interrupt block is connected | With the first output of the first gain block, the input the interrupt unit from the external device of the interrupt unit is connected to the first output of the second gain unit, to the second information input of the multiplexer, to the input of the exchange end of the control unit, to the input End of the access that is connected to the output of the zero state decoder, the input of the block state interrupt is connected to the first output of the decoder, the first input-output of which is connected to the third input-output of the first gain unit, the second input-output of the decoder is connected to the third input output of the second gain block, with the synchronization progress of the passive device of the control unit and the first higher end of the control unit, the second output of the decoder is connected to the third information input of the multiplexer, the third output of the decoder is connected to the write input of the first state register, the output of the address selector is connected to the second input with the control input of the address selector and with the fourth input output of the first gain block the input of the direct access demand of which is connected to the third output of the control block, the input is confirmed The first device selection unit is connected to the fourth output of the control unit, the second output of the first gain unit is connected to the direct access enable input of the control unit, the output of the first state register is connected to the state input of the control unit, five sixteen the output of the control unit is connected to syn-55 the output of the second trigger is connected to the gateways of the volume counter and the counter by the one-shot input, the output of which is the address, the sixth output of the control unit is connected to the first input of the first element, connected to the input of the trunk selection OR, the second input of which is - transmitter, seventh block output 24586 control is connected to the inputs of the register register of the address, the volume counter and the address counter, the output of the address counter is connected to the information input of the main transmitter, the output of the volume counter is connected to the input de5 0 five 0 zero state encoder, the output of the address register is connected to the fourth the information input of the multiplexer and the input-output address of the external device of the second gain block; the fifth information input of the multiplexer is connected to the input-output data of the external device of the second gain block, which in order to increase the throughput, a constant block is entered into it the memory address counter, the second state register, the output of which is connected to the input of the exchange end of the control unit, the recording input of the second state register is connected to the seventh output of the control unit, the on-state input of the second status register is connected to the output of the permanent memory unit and to the information input of the address register, the address input of the permanent memory unit is connected to the output of the counter, the memory address whose input is connected to the eighth code of the control unit, the synchronous input of the counter, -address is connected to the ninth output of the block 5 controls 2 "The device according to claim 1, characterized in that the control unit contains eight triggers, three AND elements, a single vibrator, three NOT elements, four IUIH elements, two pulse distributors, a clock pulse generator, and the reset input of the first trigger is the enable entry of the direct block access and 5 is connected to the input of the first element, NOT, the output of which is connected to the sync input of the second trigger, the reset input of which is connected to the output of the first element I, the first input of which is 0 input to the end of the exchange unit, the second input of the first element I connected to the output of the third trigger , the synchronization input of the first trigger is the input of a direct block access request, and connected to the information input of the fourth trigger, the output of which is connected to the synchronous input of the fifth trigger, the reset input of which is connected to the installation input of the third trigger and to the first output of the first pulse distributor, the information input of which is connected to the output of the fifth trigger, the synchronous input of the first pulse distributor connected to the synchronous input of the second pulse distributor and with the output of the clock pulse generator, the second, third, fourth, fifth outputs of the first pulse distributor are connected to ne the second, third, and fourth inputs of the second OR element, the sixth output of the first pulse distributor is connected to the first input of the third OR element and to the reset input of the third trigger, the second input of the third OR element is the synchronization input of the passive unit device, the output of the third OR element is connected to the input of the second element is NOT and with the sync input of the fourth trigger, the output of which is connected to the information input of the second pulse distributor, the first output of which is connected to the first input of the fourth element nta OR, with sixth trigger sync input, with reset inputs 0 0 five fourth and seventh flip-flops, the second output of the second distributor pulses coupled to a second input of the fourth OR gate and a clock terminal of the eighth flip-flop clock terminal of the seventh flip-flop connected to the output of the second element HE, the seventh flip-flop output coupled to the reset input of the sixth and eighth flip-flops, the eighth latch output is connected to the first inputs of the second and third elements And, the outputs of which form the first output of the block, the second input of the second element And is connected to the output of the third element NOT, the input of which is connected to The third input of the third element is the input of the end of the exchange unit, the first, seventh, eighth and ninth outputs of the first pulse distributor form the seventh output of the block, the outputs of the first and second triggers are the third and fourth outputs of the block, the output of the sixth trigger is the second output of the block, the output of the fourth OR element is the sixth output of the block, the third output of the second pulse distributor is the fifth output of the block, the outputs of the second trigger and the second OR element are continuously eighth and ninth block outputs. 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