SU1665388A1 - Device for information processing - Google Patents

Abstract

The invention relates to computing and can be used to process two-dimensional information arrays. The aim of the invention is to enhance the functionality by providing a calculation of the histogram of the distribution of the elements of the array. The device contains a block of 1 memory of input samples, block 2 of coefficient memory, block 3 of results memory, block 4 of the formation of addresses, multiplexers 5, 6, 8, 25, adders 7, 22, 26, counters 15 of addresses of counts, counter 16 of addresses coefficients, counter 17 vertical shifts, counter 18 horizontal shifts, element OR 19, trigger 20, decoders 21, 23, multiplier 24. 1 Il.

Description

The invention relates to computing and can be used to process two-dimensional information arrays.

The aim of the invention is to expand the functionality due to the possibility of calculating the histogram of the distribution of the elements of the array.

The drawing shows the functional diagram of the device.

The information processing device comprises an input sample memory block 1, a coefficient memory block 2, a result memory block 3, an address generation unit 4, multiplexers 5 and 6, adder 7, multiplexer 8, information input 9, initial setup input 10, synchronous input 11, the calculation mode setting input 12, the write-read results setting input 13, the end of calculation indication output 14, the sample address counter 15, the coefficient address counter 16, the vertical shift counter 17, the horizontal shift counter 18, the OR element 19, a trigger p 20, decoder 21, adder 22, decoder 23, multiplier 24, multiplexer 25, adder 26, information output 27.

The device implements the calculation of two-dimensional cyclic convolution, as well as the calculation of histograms.

The formula for calculating a two-dimensional cyclic convolution is as follows:

l M - 1 N - 1

fkl Е S hi g k + i l + j, k О, К-1,

I 0 j 0

, L-1,

where fkr is the processed image count (output);

L is the number of samples in the image column;

K is the number of samples in the image row;

hi - weights;

gki — input image samples;

M - the number of elements in the column of the matrix of weights;

N is the number of elements in the row of the matrix of weights.

The device works as follows.

In the passive state, inputs 10 and 13 of the device are set to logical 1. The signal from input 10 of the device sets the trigger 20 and all the counters of block 4 to zero, thus the outputs of block 4 and the output of block 7 are in the zero state . The value of logical about the output of trigger 20, the act

to the control input of the unit 1 and the control input of the multiplexer 8, switches the block 1 to the recording mode, and the output of the multiplexer switches to its information input,

connected to input 3 of the device.

The value of logical 1 from the input 13 of the device arriving at the control input of the multiplexer 5 switches the output of the latter to its information input set to the zero state.

The device begins to function, i.e. enters the active state when the input image counts 5 are sequentially received at the input 9 of the device. At the same time, the external device switches the inputs 10 and 13 of the device to the logical O state. Thus, the information input of the block 3 begins to receive values from the output of the adder 26.

0 The value of the logical 0 at the input 10 of the device allows the counters of block 4 to be counted.

At the time of the first reference of the input image to the input 9 of the device

5, depending on which function is to be implemented: a two-dimensional cyclic convolution or histogram calculation, the external device at the device input 12 sets the value of logical O or H, respectively.

Suppose that it is necessary to realize the function of two-dimensional cyclic convolution, i.e. the input 12 of the device exposes the value of the logical O. Thereby

5, the output of the multiplexer 6 switches to its information input connected to the output of counter 15. The signal from input 12 of the device switches the output of multiplexer 25 to its information input connected to the output of multiplier 24, and enters the input transfer input of the adder 26. Thus, the function summing the value received from block 3 with the value of the result of producing the values received from block 2 and from the output of multiplexer 8.

The input image samples, which are input to the device input 9 synchronously with the clock pulses at the device input 11, are recorded in the first cycle in block 1 and simultaneously pass through multiplexer 8 to the input of the multiplier 24. In this cycle, since the contents of the counters 17 and 18 are equal to zero, the result on the output of the adder

5 7 is zero, i.e. at each time in each cycle, the value of the addresses formed for blocks 1 and 3 coincides. The input image samples from the output of multiplexer 8 are fed to the first multiplier input 24, to the other input of which from the block

2 receives the value of the weight coefficient hoo. In the multiplier 24 counts gk | multiplied by the value of the weight coefficient hoo and through the multiplexer 25 are fed to the input of the adder 26, to the other input of which the zero values are received from block 3, i.e. the products hoo Qki are passed through the adder 26 without changes and are fed through multiplexer 5 to the information input of block 3. The operation mode of the block 3 is controlled by pulses from the input 11 of the device, i.e. during one period of a clock pulse, data is first read from block 3, and then data is written to the same memory cell. The products hoo gkj are recorded from the starting address in successive cells of block 3 to the addresses generated by the counter 15.

The first cycle ends when in block 1 all KL samples of the input image are recorded and in block 3 also KL products hooQkj, k 0 are recorded. K-1.1 6.1-1-1.

At the same time, the counter 15 generates a transfer signal, which also enters the setup input into the trigger one unit 20. The logic 1 signal from the trigger output 20 transfers the block 1 to the read mode and switches the multiplexer 8. Now the multiplexer 8 will receive data from output of block 1. The transfer signal from the output of counter 15 also goes to the counting inputs of counters 16 and 18. Thus, in the next cycle, the addresses at which samples will be sampled from block 1 are, at each time, one more than the addresses, by k This is followed by reading and writing to block 3. At the same time, the address at which the value of the weighting factor in block 2 occurs is obtained. It is received from counter 16. From block 2, the value of weighting factor hoi will be selected, which will be fed to the input of the multiplier 24 .Another input to the multiplier 24 is received and samples are gk. 1 + 1.

The samples gk, and −1 in multiplier 24 are multiplied by the value of the weighting factor ho-i and the resulting products through multiplexer 25 are passed to the information input of the adder 26, where they are added to the products h0ogk | coming from block 3. The resulting partial sums h0 "gk. The i-n + hooQkl is written to block 3 on the worksite h0o9k. The second cycle ends when all the contents of block 1 of memory are read again and in all the cells of block 3 will be formed

The sums of the form hoogkf + hoigk. n-1. , K-1, IOPRG

As in the previous cycle, at this moment the counter 15 generates a transfer signal, which is fed to the counting inputs of the counters 16 and 18.

After N repetitions of such cycles in block 3 the sums will be accumulated

N -1

2 hOj 9k.i + j

After the specified N cycles, the counter 18 will take a value equal to N. This, in turn, triggers the decoder 21, the signal from the output of which through the OR 19 element enters the input of the horizontal shift 18 to the zero state of the counter and to the counting input of the counter 17 vertical shifts.

After MN cycles in block 3, the sums of the form will be formed

M -1 N -1

, „, 0 TS.,

which are tk.i image counts,. K-M-1. , L-N-1.

At the same time, the counter 15 generates a transfer signal, which is fed to the counting input of the counter 18, as a result it will take the value N. The latter causes the decoder 21 to operate, the signal from the output of which goes to the counting input of the counter 17. Thus, the counter 17 vertical shifts will take the value M, which in turn will lead to the operation of the decoder 23. The signal from the output of the latter arrives at the output 14 of the device, thereby informing the external device that the calculation of two-dimensional cyclic convolution is over. With the receipt of this signal, the external device at input 13 sets a signal of logical 1. Thus, zero values will be input to the information input of unit 3 from the output of multiplexer 5.

In the next cycle, samples of the processed image are received by the memory block 3 at the information output of the device. Zero values from the output of multiplexer 5 switched to its input connected to the potential of logic O are written to their memory block. After the external device has received all the samples of the processed image and, accordingly, the entire block 3 is reset, the external device supplies the input 10 of the device with a logical 1 signal, i.e. the image processing device is put into a passive state.

In the case when it is necessary to calculate the histogram of the original image at the time the image processing device is switched to the active state, the external device exposes the logical 1 signal at the input 12. As a result, multiplexers 6 and 25 are switched and the logical 1 value is set at the input transfer of the adder 26 As a consequence of these changes, the input input of block 3 will receive input image samples from the information input of the device through multiplexer b. Adder 26 will increment the data from block 3. It is also necessary to recall that, in the passive state of the device, block 3 contains zero values. In the histogram calculation mode, the input image samples from the information input of the device through multiplexer 6 are sent to the address input of block 3. The output of this block is the contents of that memory cell whose address is given by the current count of the input image. The number contained in the memory cell is fed to the input of the adder 26; where it increases by one. The incremented number from the output of the adder 26 is fed through multiplexer 5 to the information input of block 3, where it is written into the same cell of memory block 3.

Thus, with the arrival of each new reference of the input image, the contents of the cell of block 3, whose address is determined by the value of the reference, is increased by one. Histogram calculation ends when the last sample of the input image arrives at the information input of the device. At this moment, histogram values of the input image are recorded in block 3. These values are located starting from the zero cell of the memory block 3 and up to (2-1 -1) cells, where c is the number of bits that represent the input image samples. At the same time, the external device changes the values of the signals at the inputs 12 and 13 of the device. At input 12, the value of logical O is set.

Thus, the address input of memory block 3 through multiplexer 6 will receive the values from the output of counter 15. At this moment, the contents of the counter are zero. At the input 13 of the device, the value of the logical 1 is set, the multiplexer 5 switches and, as a result, the value zero is present at the information input of the block 3.

After the last reference of the input image arrives, the external device sequentially receives discrete histogram values from the information output of the device. In place of the readable discrete values of the histogram, zero values are recorded in the memory block 3. After all discrete histogram values are received on the information

0, the output of the device, the external device sets the value of logical 1 at the input 10 of the device. The device is put into a passive state.

Claims (1)

Invention Formula 5 An information processing device comprising an input sample memory block, a coefficient memory block, a result memory block, a multiplier, two adders and an address generation block, the information input of the device connected to the information input of the input samples memory block whose address input connected to the output of the first adder, the first and second information inputs 5 of which are connected respectively to the output address of the input samples and the output increment of the address of the address generation unit, the output of the address of the coefficients of which is connected to the address input of the block 0 coefficient memory, the output of which is connected to the first input of the multiplier, the output of the result memory block is connected to the information output of the device and to the first information input of the second 5 adders, the synchronous input of the device is connected to the synchronous input of the address generation unit, characterized in that, in order to extend the functionality by enabling the histogram of the distribution of the array elements to be calculated, four multiplexers are inserted into it, and the information input of the device is connected to the first information inputs of the first and second 5 multiplexers, the outputs of which are connected respectively to the second input of the multiplier and to the address input of the result memory, the write-read input and the information input of which are connected respectively to the synchronous input of the device and the output of the third multiplexer, the first and second information inputs and the control input which is connected respectively to the output of the second totalizer, the input of the logical zero of the device and to the output of setting the write-read mode of the results of the device, the output of the multiplier is connected to the first and formational entry fourth multiplexer, a second data input and the output of which connected to the logical zero input of the device and to the second information input of the second adder, the input of the computation mode setting is connected to the transfer input of the second adder and control inputs of the second and fourth multiplexers, the output of the input samples memory block is connected to the second information input of the first multiplexer, the control input of which is connected to the input of the write-read mode 0 the input samples memory block and to the output of setting the exchange mode of the address formation block, the output address of the input samples of which is connected to the second information input of the second multiplexer, the initial setup input and the output of the indication of the end of computations of the address generation block of the device and the display input termination of device calculations.