SU1661756A1 - Sorting device - Google Patents

Abstract

The invention relates to computing and can be used for sorting parts and assembling multi-part assemblies. The aim of the invention is to expand the scope by sorting the numbers according to three features. The device contains a converter 1 analog - code, element 2, schemes 3, 4 comparisons, upper limit registers 5 and 6 lower limits, set register 7, clock generator 8, trigger 9, element 10, counters 11, 12, register 13 residues, registers 14, 15, adders 16, 17, counter 18, indication block 19, group of registers 20, group of adders 21, group of subtractive counters 22, maximum detection circuit 23, encoder 24, adder 25, group of decoders 26 zero. The device sorts the next number A, determines the group number M, and completes this number A with numbers B and C into numbers available according to the picking equation M = N - K, where M, N, K are the number of groups of numbers A, B C. 2 Il.

Description

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borders and 6 lower bounds, register of 7 settings, generator of 8 clock pulses, trigger 9, element 10, counters 11, 12, register of residues 13, registers 14, 15, adders 16, 17, counter 18, display unit 19, group of registers 20, group of adders 21, group of subtractive counters 22, maximum detection circuit 23, encoder 24, adder 25, group 1661756

poo descramblers 26 zero. The device performs the sorting of the regular part A, determines the number of group T, and completes this part A for details B and C from the number available according to the picking equation m nk, where m, n, k is the number of groups of numbers A, B, C . Z Il.

The invention relates to computing and can be used for sorting parts and assembling multi-part assemblies.

The aim of the invention is to expand the scope by sorting the numbers according to three features.

Picking a product of a given precision of three parts can be given by the picking equation

m n - k,

where m, n, k are the numbers of the sorting groups for parts of the first, second and third types, respectively (details A, B and C in the following),

And in the device is taken

O Ј m L M-1, O & n N-1, O k K-1,

where M, N, K are the number of -groups of parts A, B and C, respectively.

The device performs the sorting of the regular part A, determines the number of group T, and completes the part A for this part A by details B and C from among those available according to the picking equation.

When picking, all permissible combinations of mn, kC are considered for a given m. Since pi k are connected, it is enough to select one of the parts to select a combination, provided that the other part included in the combination is available.

The device selects a combination by part B, and the group n is selected in which the number of parts is maximum. This choice op

It simulates the process of picking, the obstacle to the rapid emergence of the situation of the impossibility of picking due to the lack of details in these or other groups.

Figure 1 shows the block diagram of the sorting device, figure 2 shows the structure of the maximum detection circuit.

Sorting device contains

Converter 1 analog - code, element 2, schemes 3 and 4 comparisons, upper limit register 5, lower limit register 6, setting register 7, clock generator 8, trigger 9, element 10, counters 11 and 12, residue register 13 , registers 14 and 15, adders 16 and 17, counter 18, display unit 19, group of registers 20, group of adders 21, group of subtractive counters 22, maximum detection circuit 23, encoder 24, adder 25, group of decoders 26 zero.

Figure 2 shows the structure of the maximum detection circuit 23.

The maximum detection circuit contains (L + 1) circuit 27j-27c + comparison, switches 28, -28, AND logic circuits 29, key group 30, ZOSch.2, decoder 31 zero, And 32 element.

The device sorting works as follows.

Before the start of the actual sorting, group boundaries for Part A are entered into the 7 registers of settings and the registers of the upper 5 and lower 6 boundaries, a priori information about the composition of the batch of parts B into the register of 13 residuals and registers 14, 15, 20, -20U; a priori information on the composition of the batch of parts C to the subtracted counters.

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In subtractive counters 22,,. the numbers of parts are entered into O, 1, ... groups of parts C, the remaining counters are entered with zeros, limiting the range of choice for parts B. The registers 20t.-t-20 ,, 15, 14, 13, 20c are entered into quantities parts in O, 1, ... groups of parts B, while the remaining registers are filled with zeros, which are unused information.

In registers 5, 7 and 6, the sorting boundaries for part A are entered, starting with the minimum, in the remaining free positions, such values of the fictitious boundaries are entered which will not cause the device to trigger. The introduction of assigning zeros and fictitious boundaries allows the use of different K, M, and N values within the real memory of the device.

In addition to this, during the initial installation the trigger 9 is reset, the counters 11 and 18 are zeroed and the counter 12 is set to the maximum value. To simplify the initial installation circuit, not shown in Figure 1.

Converter 1 analog - a code converts the value of the measured parameter of the part A into a digital code, which is fed to the inputs of circuits 3 and 4 of the comparison. By the signal. The end of the conversion from the converter 1 analogue — the code is set to one state trigger 9, allowing. the passage of clock pulses from the generator of 8 clock pulses through AND circuit 10. Under the action of clock pulses from the output of the circuit AND 10, the information in registers 5-7 is shifted and at a certain moment in the registers of the borders the upper limit code (register 5) and the lower limit code appear (register 6). This moment is revealed by the appearance of a pulse at the output of counter 11, which has a conversion factor equal to the clock period between the codes of neighboring boundaries recorded in a sequential code in register 7 of settings and registers 5 and 6, and counter 12 counts the number of such periods corresponds to the number of the youngest (ji) of the sorting groups of part B and the number of group of parts A.

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Scheme 3 of the comparison works if the parameter code is less than the code of the upper boundary of the group, and scheme 4 of the comparison works if the code of parameter 4 is greater than the code of the lower border of the group, i.e if the parameter is within the tolerance of the given sorting group. In this case, the signal from the output of the counter 11 turns on the WIT signal at the output of the AND 2 circuit. Since registers 13–15 form an information ring, and their shift clock inputs are combined and connected to the output of the AND 10 element, then at the time of the appearance of the output signal And 2 in the register 20 contains the rest of parts B by this (ji) sorting group, in register 20 1 - the remainder of parts B by the next (ji + 1) sorting group, in the register. the rest of the details in the following (j i + 2) sorting group.

5 From the codes contained in registers 14, 15, using the maximum detection circuit 23, the group with the maximum remainder of parts B is selected under the condition of an enabling signal at the corresponding control input connected to the output of the corresponding zero decoder from the group of decoders, Ј. In this case, the signal from the output of the circuit AND 2 at the corresponding output of the maximum detection circuit 23 generates a signal. The positional code generated in this way at the output of the maximum detection circuit 23 is converted by the Shida by the fractioner 24 into a binary code corresponding to the number of the group Cr supplied for the indication and also the number of the selected group of parts B with respect to the smallest possible for the part A that ) is contained in the counter 12. The adder 25 performs the summation of the codes from the outputs of the counter 12 and the encoder 24. Obtained at the output

Q adder 25 code corresponding to the number of the selected group of parts B, enters the display unit 19 to display "

A single signal from one of the outputs of the circuit 23 you

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neither maximum, an entry is made in the corresponding register 14, 15, 20.-20 of the new balance of parts B in the group, which is less than the previous

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per unit. The subtraction of a unit is performed by adders 16, 17, and 2T21, the first group of inputs of which are supplied with logical units (r., Number -1 in the additional code), and the second groups of inputs are connected to the outputs of the corresponding registers.

By the same signal from one of the outputs of the maximum detection circuit 23, the corresponding subtraction counter from the counter group 22 |, -22i + 2. Is reduced by one unit, which stores the codes of parts C at the time of sorting Rvvki this part. In the event that when a regular unit is subtracted from the contents of any counter 22t-22cf ° er °, the content becomes equal to zero, which is the corresponding zero decoder. To1 the signal from this decoder is fed to the corresponding control ( 23 of the maximum detection, when sorting the next pieces A is excluded from the process of searching for the maximum residue, the corresponding sorting group of parts B, regardless of the size of the rest of the parts in this group, the search for the maximum residue is carried out Wed | one remaining groups of parts B.

The counter 18 serves to detect faults in the parts sorted. A. The clock input of the counter 18 is connected to the output of the counter 11, and the zero input of the counter 18 is connected to the output of the AND 2 circuit. The output of the counter 18, the conversion factor of which is set to one more than the maximum possible in the device the number of sorting groups of part A is connected to the reject indicator in the display unit 19.

Thus, if item A is mapped to all possible boundaries and is not assigned to any of the sorting groups (i.e., no signal arrives at the counter zero reset), then in the next step from the output of counter 18 to the input of the display 19 signal allowing the indication of marriage. The same signal arriving at one of the inputs of the installation in the zero state of the trigger 9 stops the arrival of clock pulses from the output of the circuit And 10.

The trigger 9 is set to the zero state also by the signal from the output of the circuit AND 2.

The maximum detection circuit 23 is similar to the circuit of the same name in the known device, with the exception of the additional keys SOj-SOj introduced for each information input. controlled by signals from the outputs of the corresponding decoders of zeros 26ts-26 g, decoder 31 zero, the input of which is connected to the output of the last key, and the output is connected to the inverse input of the circuit And 29 c + + and the first direct input of the circuit And 32, the second direct my input is connected to the general gating input of the maximum detection circuit 23, and the inverse input Q is connected to the output of the last circuit

2 144 matches

Thus, the signal at the output of the AND 32 circuit appears if in all the groups of parts B involved in the maximum search process 5, the number of parts is zero, which indicates that it is impossible to complete this part A with details B and C due to their absence . This signal 0 is applied to the fourth input of the display unit 19, permitting the indication of the absence of a picking capability.

The proposed device can also be used for two-piece units, performing information processing similar to the operation of the known device. This is achieved by setting the required number of nonzero data in the counters, which determine the range of part B selection. In this case, the assembly of components is carried out by indicating the number of part B, the indication of part number C is ignored.

Thus, the proposed device implements the functions of the known and extends them to three-part nodes.

Claims (1)

Invention Formula five 0 Sorting device containing analog converter - code, lower limit register, upper limit register, settings register, residual register, two registers, two comparison circuits, three counters, three adders maximum detection circuit, adder group, encoder, trigger, clock generator impulses, two elements AND, a group of registers, and U1 the analogue information input of the converter — the code is the information input of the device, and the information outputs are connected to the inputs of the first groups of the first and second comparison circuits, the inputs of the second groups of which are connected respectively to the outputs of the bits of the upper and lower bounds registers; with the input of the lower bit of the lower limit register, the output of the high bit of the kotorog is connected to the input of the lower bit of the register of settings, the output of the senior bit of which is connected to the input of the younger The register bit of the upper limit of the shift register inputs of the settings of the upper and lower limits registers, the register of residues, the first and second registers, the group of registers and the counting input of the first counter are connected to the output of the first element I, the first input of which is connected to the output of the clock generator, and the second the input is to the output of the trigger, the installation of which in 1 is connected to the output. The conversion end of the analog converter is a code, the overflow output of the first counter is connected to its installation input in O, with the counting inputs of the second first and third inputs of the second element, the second and third inputs of which are connected respectively to the outputs of the first and second comparison circuits, and the output is connected to the first reset input of the trigger and the third counter, the transfer output of the third counter is the output of the device’s fault sign and connected to the second reset input of the trigger, the high-end output of the register of residuals is connected to the low-order input of the first register, the high-level output of which is connected to the low-level input of the second .register The first and second registers and group registers are connected respectively to the inputs of the first groups of the first and second adders and the total 0 756 five ten The group's inputs, the inputs of the second groups of which are connected to the input of the logical unit of the device, the outputs of the first, second adders and adders of the group are connected respectively to the inputs of the corresponding bits of the first, second registers and registers of the group, the outputs of the third adder are outputs of the selected device group number, first and the second group of inputs of the third adder are connected respectively to the outputs of the bits of the second counter and the encoder, the inputs of which are connected to the output of the maximum allocation circuit, the information in Which odes are connected to the outputs of the bits, respectively, of the first, second registers and registers of the group, and the strobe input of the maximum allocation circuit is connected to the output of the second element AND, characterized in that, in order to expand the scope of application by sorting the numbers according to three features, it is entered a group of subtractive counters, a group of decoders zero, the inputs of which are connected to the outputs of the corresponding counters of the group, and the outputs are connected to the corresponding control inputs of the maximum allocation circuit, the control output which is the input of the device indication enable, the encoder outputs are the outputs of the second selected device group number, the counting inputs of the subtracting counters are connected to the corresponding outputs of the maximum allocation circuit, the high bit output of the second register is connected to the low bit input of the first group register, the high bit output yes i-ro register (i 1 (L-1), where L is the number of registers in the group) is connected to the input of the low-order bit (i + f) -ro of the group register, the output of the high-order word L-ro of the group register is connected to log in th least significant bit registers OC remnants. 0 five 0 Vui.t