SU1642585A1 - Da converter - Google Patents

Abstract

The invention relates to automation and computing and can be used in control devices of medium and high power levels. The purpose of the invention is to expand the dynamic and frequency ranges of the transform. The digital-to-analog converter contains a code driver, a code converter, a pulse-width converter, a clock, a frequency divider, N key amplifiers, an analog adder, and an output bus. The code converter, in turn, is executed on a multi-channel shift register and N logic blocks. The purpose of the invention is achieved by generating, on low-order bits, a shaper-modulated pulse signal shaper, as well as generating an additional code with the high-order bit of a shaper, based on dividing the clock signal by a frequency divider and converting the code converter of the generated signals into a number of modulated pulse sequences evenly shifted in phase. 1 hp f-ly, 5 ill., 2 tab. &

Description

The invention relates to automation and computing and can be used in devices for controlling the parameters of electrical energy of medium and high power levels.

The aim of the invention is to expand the dynamic and frequency ranges of the transform.

FIG. 1 shows a structural electrical circuit of a digital-to-analog converter; in fig. 2 is a block diagram of a code converter; FIG. 3 is a block diagram of a logic unit; figure 4 is a structural diagram of a multi-channel shift register; figure 5 - timing charts of the device.

The digital-to-analog converter (Fig. 1) contains a shaper 1 code, a generator 2 clock pulses, a pulse-width converter 3, a divider 4 frequencies, a converter 5 code, key amplifiers 6.1-6.N, an analog adder 7, an output bus 8.

The code converter 5 (FIG. 2) is executed on a multichannel register 9 and N logical blocks 10.1-10 .N.

For the case of a three-bit code, logical block 10 (FIG. 3) can be executed, for example, on three elements EXCLUSIVE OR, element OR and six elements AND, and a multi-channel shift register on three inverters and four D-triggers.

About 4 W SP 00

ate

The bit inputs of the pulse-width converter 3 receive mn low-order bits of the binary code M of the input signal from the shaper 1. In this case, the pulse-width converter 3 forms a sequence P (FIG. 5) of pulses whose duration is determined by the value of the least significant bits code

tu To (SM-Sz -2t-p) / 2tL (1)

where To is the period of the UT clock signal generated by generator 2;

5m - the value of the binary code M of the input signal,

t-1,

5m - 2 at 2f; (2)

Sz - the value of the binary code Z higher bits to / ed M;

 1Zj2i; , (3)

at. Zj - states of the 1st, J-ro bits of the M and Z codes, respectively.

Thus, a pulse width modulated pulse sequence F is generated by mn low-order bits of the input signal with a period T of clock pulses UT (FIG. 5), the temporal position of the front of which determines the binary code sample and corresponds to the edge of pulses F. By dividing the clock pulses pulses UT by a frequency divider 4 is carried out to form a binary code X, the size of which n is determined by the required multiplicity of the N 2P pulse-width modulation. The states of the bit outputs Xi, Xz, Xs of the 4 frequency divider for the case of n 3, which corresponds to 8-channel pulse-dummy modulation, are shown in Fig. 5. According to the function performed, the frequency divider 4 can be performed on a binary counter with a division factor of N.

The pulse width sequence F and the binary n-bit code X together with the higher bits of the M code of the input signal unambiguously determine the width-modulated pulse sequences YI, ... YN, evenly shifted in phase with the switching period T ToM, as functions of the time and magnitude of the m-bit binary code generated by the former 1. Function of matching the states of the pulse sequences YI, ..., YN with the states of bits Xi, X2, Xs and Zi, Z2, 2z of binary codes X " and Z, as well as with a width-modulated sequence nostyu F 5 code converter implemented in accordance with the following logical expression:

and.-/

t-i

YK Zn LHpk {V Zn-s L X (n-s) K L A F

®yX (n4) K) (Zi ® XJK) VF: (4)

where X JKW - (K - 1) T, K 1, ..., N;

Xj is the value of the j-ro bit of the X code, which varies over time t.

8 general case 5 code converter

0 can be performed on a permanent storage device (ROM) stitched in accordance with expression (4), which can be defined in the form of a truth table. For example, for the case of 8-channel

5 pulse-width modulation by sequential solution of expression (4) for YIYe depending on the values of bits ХцХ21Хз1 nZi, Z2, Z3KOflOBOBMMZ, we get the firmware program of the ROM. Discharges

0 ХЦХ21Хз1 in expression (4) correspond to the first YI modulation channel and are determined by the state of bits XL X2, Xs (figure 5) of the binary code X formed by the divider 4 frequencies. To determine the state of the 5 following modulation channels Yj (i 28)

In expression (4), bits Xc, X2I, Xs, obtained by temporal shift of bits Xi, X2, Xs, are substituted by the time interval

0-1) 0 The results of the solution of expression (4) are summarized in Table. 1 and 2.

The logic function defined by truth table 1 and 2. can also be implemented by code converter 5

5 (FIG. 2) containing a multichannel shift register 9 and N logical blocks

10.1 10.N (where N 8 for 8-channel

PWM). Functional diagrams of logic unit 10 and multichannel register 9

0 shift for the case of N 8 presented in Fig.Z and 4.

Multichannel shift register 9 is designed to form N binary codes uniformly shifted in time.

5 with respect to the source binary code X formed by divider 4 by dividing the output signal of generator 2. XL X2 bits. Xs binary code X entering the inputs of the register 9 shift,

0 changes in time according to the law of a meander with a period of 2T, 4T and 8T, respectively (Fig. 5). At the outputs of shift register 9, N binary codes Xi, 2,3 are generated (where K a 1, ..., N} with relative time shift T

XiK (t) Xii (t- (K-1) T); X2K (t) X2i (t- (K-1) T); (5)

X3K (t) X3i (t- (K-1) T). Whereas, the signals Xn (t), Xjift), Xai (t) are periodic in time,

The shift register function can be simplified. ak, for K- 1. 3. 5, 7 you can directly use Xn (t), and for K 2, 4, 6, 8 - Hzfmt.d.

The function performed by logic 5 block 10 is determined by expression (4).

Digital to analog converter works as follows.

The shaper 1 generates the m-bit binary code of the input signal at the bit-10 outputs, which is changed when the generator of the output pulses U of the generator 2 arrives at the synchronization input. pulse-width converter 3, where they are converted into pulse duration tn (1), the front of which coincides with the 20 leading edge of the clock pulses Jr. The pulse-modulated pulse sequence F from the output of the pulse-width converter 3 is fed to one input of the converter 5 of the code, the other bits of which 25 receive the code of the higher bits Z of the driver 1 and the binary code X formed by the divisor 4 by dividing the clock signal generator 2.

In accordance with the logic function 30 {4} using binary codes Z, X and the pulse signal F, the Kotz converter 5 generates N pulse sequences modulated according to the law of the input signal m-bit code, which arrive through 35

6.1 key amplifiers 6.N inputs

analog adder 7. The total impulse voltage UK (Fig. 5) of a high power level through the filtering link included in the adder 7 of the summing device enters the output bus 8 to the load, where the useful low-frequency components of the UH input are allocated signal. The maximum value of UM is equal NEo (where Ео is the amplitude of the output pulses of the key amplifiers), which is greater than the amplitude of the additional high-frequency components of the pulse voltage. By choosing the switching frequency of the total pulsed voltage 50 to 10 times the upper frequency of the input signal when using a second order filtering link, the device achieves a dynamic conversion pitch of the order D / I 4MS +.

At the same time, the switching frequency of individual key amplifiers is N times lower than the frequency of change of the total pulse voltage.

Formula

Claims (2)

1. A digital-to-analog converter containing a code driver, the low-order outputs of which are connected to the corresponding information inputs-- a sprat-mm-pulse converter, the synchronization input of which is connected to the output of the clock generator, and the first key amplifier, which is different in that and frequency ranges of the conversion, a frequency divider, a code converter, N-1, where N is the number of code converter outputs, key amplifiers, and an analog adder, are entered into The output of which is the output bus, and the inputs through the corresponding key amplifiers are connected to the outputs of the code converter, the first information inputs of which are connected to the corresponding old outputs, their bits of the code generator, the synchronization input is connected to the output of the pulse-width converter, and the second information inputs, respectively connected to the outputs of the frequency divider, the input of which is connected to the synchronization input of the code generator and connected to the output of the clock generator. 2. The converter according to claim 1, wherein the code converter is executed on a multi-channel shift register and N logic blocks, whose outputs are the outputs of the code converter, the synchronization inputs are combined and are the input synchronization of the code converter, the first information inputs are respectively combined and are the first information inputs of the code converter, the second information inputs of which are the corresponding inputs of the multi-channel shift register, the outputs of which correspond nno connected to the second information inputs of logic blocks, Table 1 Continued table. one table 2 Continued table. 2 S892V91 L Ur h Sx illli lllilll..i.-LLUJLIMIiMM J Xi h h p t Ouse 9 9s HC Y UK VH LriJTJTJTJTJTJiJTJn ii and shpl1plpl11stlsh FIG. five