SU1411960A1 - Digital device for controlling pulse-width converter - Google Patents

Abstract

The invention relates to a pulse technique and can be used in high-power DC and AC key converters with a sinusoidal output signal. The invention extends the range of variation of the minimum and maximum pulse durations of the output signal. The device contains a master generator of 1 pulses, a counter of 2 pulses, a divider 3 frequencies, triggers 4 and 5, reversible counters 6 and 7, subtractive counters 8 and 9. Introduction to the device of two subtractive counters, the second trigger and frequency divider allows you to change the minimum and maximum pulse durations of the output signal over a wide range, which allows the device to be used in voltage converters. At the same time, the amplitude of the output signal of the power converter is precisely controlled by the control of your code by changing the multiplicity of the durations of the output pulses. 1 il. And (L

Description

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The invention relates to a pulse technique and can be used in high-power key DC / AC converters with a sinusoidal output signal.

The purpose of the invention is to expand the range of variation of the maximum and maximum pulse durations of the output signal.

The drawing shows a functional diagram of a 1-PF pulse-width converter control device.

The device contains a master generator 1 pulses, a counter 2 pulses, a divider 3 frequencies, triggers 4 and 5, reversible counters 6 and 7, live counters 8 and 9, while the output of the master oscillator 1 pulses connected to the input of the counter 2 pulses, counting inputs of reversible counters 6 and 7 and the counting inputs of the subtracting counters 8 and 9, the preset control inputs of which are connected to the output of the pulse counter 2, the input of the frequency divider 3 and the first inputs of the trigger 4 and 5, the inverse output of the trigger 4 is connected to the input of the counting direction A counter 6, the information inputs of which are connected to the control signal bus, the preset control input, to the same input of the reversible counter 7 and the output of the splitter 3 frequencies, and the outlets of the old bits to the information inputs of the down counter 8, the overflow output of which is connected to the second input trigger 5, the direct output of which is connected to the d output bus and the counting direction input of the reversible counter 7, whose information inputs are connected to the zero bus, and the outputs of the higher bits from the information output GOVERNMENTAL inputs reversible counter 9, the overflow outlet of which is connected to the second input of the flip-flop 4.

The digital control unit of the pulse-width converter works as follows.

Denote the states of the reversible counters 6 and 7 by integers U, and and, equal to the number of pulses of the master oscillator 1 needed to bring the counters into this state from the initial one, i.e. -2 where K is the size of reversive counters. Pulse counter 2 generates

short pulses with the following frequency f, where f is the frequency of the master oscillator, 1 is the width of the counter 2 pulses, is equal to the size of the subtracting counters 8 and 9. Each pulse from the output of the counter 2 sets the triggers 4, and 5 to zero and presets the counters 8 and 9. Indicate the current following number.

of these pulses n, then 1 most significant digits of the number and; (n) are recorded in the counter B, and after a time interval

t (n) (n) j / (2 f) (1)

at the output of counter 8, an impulse is formed by switching the trigger 5 to the state of the unit in which it remains for a time

7 / p) 2 -U / n) J / (2 f) (2)

before the arrival of the impulse n + 1.

The change in the state of the counter 7 for the time interval between the pulses b and n + 1 is

uU2 (n) U2 (n + 1) -U2 (n), - then

& U2Cn) f) -CH (p) 2 and (p),

since the time interval t is in addition mode, and the interval is in subtraction mode.

In contrast to (3), a change in the state of counter 6 is described by the formula

. i-K + i uU (p) -2i, (p), (4)

since the counting direction is changed by the signal from the inverse trigger output

Take the first order difference from both sides of equation (3)

-K +1

g2i (n) 2 & i, (n)

and equation (4) is substituted into it,

get

l2 (n) +4

ek + 1

U2 (n) 0.

(five)

This equation is an equation for the motion of an oscillatory link in discrete form, the transition to the limit

S (t ..

A t

(6)

-K41

where and) is the angular velocity iso -2f,

Solving this equation is the law of variation of BHyTjis. H is a state of reversibility;

and jC t) As inoOt,

where A is the signal amplitude code.

Because time intervals

and 1

(7)

characterized by the state of trigger 5, depend on Q according to formulas (1 and 2), their values are modulated according to a sinusoidal law, and the signal from the output of trigger 5 after amplification can be fed to a control input of the transducer operating with two-polar PWM carrier frequency f, and output sinusoidal voltage frequency f.

In order for the error associated with truncation in performing computational operations in counters with a limited size not to accumulate, and also to control the amplitude of the output signal, a divider of 3 frequencies is inserted into the device with a division factor close to 2. The output pulses of this divider following frequency of the output sinusoidal voltage, go to the preset control inputs of the reversing counters 6 and 7 and thereby set the initial states of the counters to 1 and O, respectively, after which tion period otrabatyvaets sinusoidal oscillation at the expiration of the initial operation period setting conditions down counter is repeated, that stabilizes the output signal amplitude and the possibility of controlling the amplitude of the output signal amplitude from the source code.

g

but

ten

15

20

-t

25

thirty

35

The paddle is quite simply and precisely controlled by the control code, changing the multiplicity of the durations of the output pulses.

Claims (1)

Invention Formula A digital pulse width converter control device containing a pulse generator connected in series, a first pulse counter and a first trigger, the direct output of which is connected to a viper bus, a second pulse counter whose information inputs are connected to the control signal bus, and a third pulse counter, characterized in that, in order to expand the range of the change in the multiplicity of the pulse duration of the output signal, a frequency divider is added to it, two subtracting scores pulse and the second trigger, the first input of which is connected to the output of the first pulse counter, the input of the frequency divider and preset control inputs of both subtractive pulse counters, the counting inputs of which are connected to the output of the master pulse generator and the counting inputs of the second and third pulse counters, while the direction input the second pulse counter is connected to the inverse output of the second trigger, and the outputs of its higher bits are connected to the information inputs of the first subtractive pulse counter, in overflow output Thus, the introduction to digital Q th is connected to the second input of the first a pulse width converter control unit of two subtractive counters, a second trigger and a frequency divider allows the minimum and maximum lengths to be varied. output pulses over a wide range, including the sinusoidal law, which is beneficial when using the device 3 powerful voltage converters, while the amplitude of the output signal of the powerful transducer trigger, the direct output of which is connected to the input of the counting direction of the third pulse counter, the preset control input of which is connected to the same input of the second pulse counter and the output of the frequency divider, the information inputs are connected to the zero bus, the high-end outputs are connected to the information inputs The second subtractive counter, the overflow output of which is connected to the second input of the second trigger. . 0 trigger, the direct output of which is connected to the input of the counting direction of the third pulse counter, the preset control input of which is connected to the same input of the second pulse counter and the output of the frequency divider, the information inputs are connected to the zero code bus, the outputs of the higher bits are connected to the information inputs of the second deducting counter , the overflow output of which is connected to the second input of the second trigger.