SU1642456A2 - Dc stabilized source - Google Patents

Abstract

The invention relates to electrical engineering and can be used as a secondary source of electrical power for electronic equipment. The purpose of the invention is to expand the functionality while maintaining the quality of the output parameters and improving reliability during operation. This goal is achieved by introducing dividing diodes 7, N elements EXCLUSIVE OR SE, N voltage dividers 11, N flip-flops 12, block 13 summing the number of simultaneously arriving signals, decoders 14, 15 and block 3 of bit-wise. During one cycle, continuous and constant voltage regulators 5 are connected to the load 9. In the event of individual stabilizers 5 failing, the output parameters of the output voltage of the device are preserved and the number of faulty stabilizers 5 is determined. 3 il. (L

Description

The invention relates to electrical engineering and can be used as a secondary source of electrical power for electronic equipment.

The aim of the invention is to expand the functionality while maintaining the quality of the output parameters, improving reliability during operation.

Fig. 1 shows a functional diagram of a stabilized constant voltage source; figure 2 - diagram of his work; FIG. 3 is a functional implementation scheme of the summation unit for the number of simultaneously incoming signals. The stabilized DC voltage source contains a generator of 1 pulses, the output of which is connected to the counting input of counter 2, made with the installation input in O, the M outputs of which are connected separately to one M inputs of the unit 3 of a variable summation, the M outputs of which are connected to the M inputs of the first a decoder-4, N outputs of which are connected to control inputs of parallel-connected constant-voltage regulators 5.1-5.N, the inputs of which are combined and connected to

OE

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OE

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the output for connecting the source 6 of the supply voltage, and the outputs through the separation diodes 7; 1-7.N

load 9 through the filter 8 stabilize 5.2, the remaining outputs of the first encoder 4 - level O (figv,

combined and connected to the input filter, 2c), locking the stabilizers 5.1

8, the output of which is connected to the output for connecting the load 9, each output of the decoder 4 is connected to one input of the corresponding element 10.1-10.N EXCLUSIVE OR, whose other input through a voltage divider 11.1-11. stabilizer 5.1 - 5.N DC voltage, and the output - to the installation input to 1 of the corresponding trigger 12.1-12.N, the output of which is connected to the corresponding input of the block 13 summing the number of simultaneously incoming signals, the outputs of which simultaneously 20 are connected to friend the inputs of block 3 of the bit summation and to the inputs of the second decoder 14, the inputs of the installation in the O flip-flops 12.1-12.N are connected to the input of the installation in the O of the 25-second 2 and the output of the third decoder 15. Figure 1 also denotes the outputs 16.1-1 b.N triggers 12.1 - 12.N and outputs 17 of the second decoder 14.30

A stabilized constant voltage source, for example, with N 3, i.e. N way.

4-2 works as follows 5.3. The falling edge of the second pulse of the generator 1 sets the counter 2 to the state 0-1, at the third end of the first decoder 4, level 1 is set, connecting to load 9 via filter 8, the stabilizer 5.3, at the other outputs of the first decoder 4 - levels O ( figv, 2b), locking stabilizers - 5.1 and 5.2. The falling edge of the third pulse of the generator 1 (Fig. 2a) mirrors the control signal through the third decoder 15, which sets the counter 2 to the initial state 0-0, the next series connection to the load 9 starts through the filter 8, which stabilizes the jams 5.1 -5.3, which give something for one period of the pulses of the generator 1 pulses.

When any stabilizer 5.1–5.3, for example, 5.2, for example, 5.2 fails, the output of the EXCLUSIVE OR 10 element will be present at the time of the interrogation at the same time signals of different Aases, which signal a malfunction of the stabilizer 5.1 5.3, and when signals of one phase arrive, they are malfunctioning. The output of the element 10.2 EXCLUSIVE And at the same time, level 1 appears, which takes the trigger 12.2 to the state 1, which is fed to the corresponding input of the unit 13 summing the number of simultaneously receiving signals. Block 13 operates in such a way that, when a signal appears — at any of its inputs, respectively, a 0–01 signal appears at the outputs, with 1 being written to the low-order bit, while the signals at any two inputs appear simultaneously, accordingly, at outputs O - 10, with simultaneous occurrence of signals at any three inputs at its output, respectively,

At the moment of connection of the constant voltage after the end of the transients, the counter 2 is established in one of four possible states. In this case, on both outputs of the counter 2 zeros, i.e. 0-0 state (fig 26, 262). Considering that these signals are transmitted directly to the first decoder 4, i.e. At the second inputs of block 3, the levels O are present. At the first output of the first decoder 4, level 1 is set (FIG. 2B), which allows the stabilizer 5.1 to work on load 9 through filter 8, and the remaining outputs of the first decoder 4 levels O (figvg, 2c), locking stabilizers 5.2 and 5.3. The falling edge of the first pulse of the generator 1 (Fig. 2a) transfers the counter 2 to the state 1-0, at the second output - the first decoder 4 (Fig. 2b) a level 1 is set, which connects to

16424564

load 9 through the filter 8 stabilizer 5.2, on the remaining outputs of the first decoder 4 - level O (figv ,, | |

ьт-, 2в), locking stabilizers 5.1

-, 2c), locking stabilizers 5.1

u - 15 20 25 30

35

40

45

50

55

and 5.3. The falling edge of the second pulse of the generator 1 sets the counter 2 to the state 0-1, the third output of the first decoder 4 sets the level 1, which connects the stabilizer 5.3 to the load 9 through the filter 8, the O outputs of the first decoder 4 (fig.2b, 2vЈ), locking stabilizers - 5.1 and 5.2. The falling edge of the third pulse of the generator 1 (Fig. 2a) generates a control signal through the third decoder 15, which sets the counter 2 to the initial state 0-0, starts the next cycle of series connection to the load 9 through the filter 8 of stabilizers 5.1-5.3, which return current during one period of the pulses of the generator 1 pulses.

When any stabilizer 5.1-5.3, for example 5.2 fails, the output of the EXCLUSIVE OR 10.2 element will be present at a certain time of the survey simultaneously signals of different Aase, which signal a malfunction of the stabilizer 5.1 - 5.3, and when signals of the same phase arrive, they are malfunctioning. At the output of element 10.2, EXCLUSIVE OR, a level 1 appears, which translates the trigger 12.2 into state 1, which is fed to the corresponding input of the block 13 of the summation of the number of simultaneously incoming signals. Block 13 operates in such a way that when a signal appears — on any of its inputs, respectively, a 0–01 signal appears on the outputs, with 1 being written to the low-order bit, while signals are appearing on any two inputs, respectively, on the outputs O - 10, with the simultaneous appearance of signals on any three inputs on it, respectively - O 1, etc.

I

An example of the implementation of such a block 13 can serve as a functional diagram (Fig. 3), built on half-adders 18 and full adders 19. The above-mentioned functional diagram is executed on eight inputs, but by analogy

You can design an electrical circuit for the required number of inputs.

The signal O - O 1 from block 13 is fed to the inputs of block 3 of bitwise summation, in which it is added to the signal coming from counter 2. As a result of summing up at the output of block 3, the signal will be one more unit and, accordingly, the control signal will be transferred to the next output bus of the first decoder 4. Consequently, the control signal to the faulty stabilizer 5.2 will not be received, but will be transferred to the operational stabilizer 5.3, which will work for load 9 through the filter 8.

Thus, in the event of a malfunction of the stabilizer 5.2 to the load 9 through the filter 8, the in-service stabilizers 5.1 and 5.3 will be connected in series, the faulty stabilizer 5.2 will pass. Similarly, work is organized in the event of a defective stabilizer 5.1 or 5.3. Moreover, the signals at the outputs 16.1-16.N inform about the faulty stabilizers 5.1-5. H of a constant voltage, and at the outputs 17 of the second decoder 14 about the number of faulty stabilizers that allows . a certain number of faulty stabilizers 5.1-5.N form a signal to the actuator to disconnect the power supply source.

Compared with the prototype, this device expands the functionality when creating secondary power sources.

five

five

0

five

0

on the basis of unified voltage regulators of low power.

Claims (1)

Claims of the invention. Stabilized source of constant voltage by auth.St. P 1361525, characterized in that, in order to expand functionality while preserving the quality of output parameters and increasing reliability during operation, N dividing diodes, N EXCLUSIVE W, N voltage dividers, N flip-flops, a unit of summing simultaneously received signals are introduced , the second and third decoders, block of summation, the M inputs of which are connected to the M outputs of the counter, and the M outputs to the M inputs of the first decoder, the N outputs of which are connected to the same inputs of the element EXCLUSIVE OR, the other inputs of which are connected via parallel voltage dividers in parallel N N constant voltage regulators, these outputs are interconnected via separation diols, the outputs of the EXCLUSIVE OR elements are connected to the installation input of 1 flip-flops, the outputs of which are connected to the inputs of the sum totaling unit simultaneously arriving signals, the outputs of which are simultaneously connected to the inputs of the second decoder and other inputs of the block of one-bit summation, the installation inputs to O trig ger connected and connected to the installation of the counter and the output of the third decoder, the inputs of which are connected to the M inputs of the first decoder. 1, at at, 6g "M AT / g / xtt xs ( M ( X5 (/ G5 " I (X8 G l FIG. Z