SU1714603A1 - Controllable adder - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is to increase the completeness of the control. The adder contains the switch 1, the delay elements 2, 3. the element is NOT 4, the modulo adders are two 5, 6, the elements AND 7, 8. 9, control input 10, information inputs 11, outputs 12, 13 of the sum and transfer. 1 dw., 26 tab.

Description

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The invention relates to a computing technique and can be used for the construction of various adders with a built-in control.

The purpose of the invention is to increase the amount of control.

The drawing shows a structural hema controlled adder.

The monitored / adder contains switch 1, delay elements 2 and 3, NOT 4 element, modulo va adders 5 and 6, AND elements 7–7, control input 10, information inputs 11, output 12 sums and transfer output 13.

Controlled adder has two modes of operation - working and control.

In the operating mode, the control input 10 is given a logical O signal, the switch 1 switches the inputs of the first group to its outputs, and the adder implements the truth table of the full adder.

In the control mode, the control input 10 is given a logical 1 signal, the switch 1 connects to its outputs the inputs of the second group. Thus, in a controlled adder, a feedback is formed, defined by the relations XI (T + 1) S (T-1), X2 O + 1) P (T), X3 (T + 1) P (T),

VfleXiCT). H2SG), Xs (T), SCO. PfO-signal values. fishing at inputs 11 of the adder 5 modulo two and outputs 12 and 13 of the sum and transfer of the controlled adder. The first equation shows that the signal at the first input is delayed per cycle.

Table 1 shows the possible malfunctions and the corresponding signals at the outputs 12 and 13. Tables 2-26 are truth tables for various states of the controlled adder.

With a good adder, possible truth tables 12-18 are implemented. This number is due to the uncertainty of the initial state of inputs XI, X2 and X. However, all tables have the same periodic part, which contains four different input sets. At outputs 12 and 13, a frequency f is generated. If there are constant faults such as wire wiring to the power bus XI 1, X2 1, XZ 1, wire break XI O, X2 O, XZ O, circuit XI X2, X1 X3, X2 X3, XI X2 XZ, the monitored adder starts to implement tables respectively truths 2-11. All of them differ in their periodic part from that already obtained with an intact adder.

Fault in most cases is detected by the presence on one (or both) of the outputs 12 and 13 of the monitored controlled constant logic level

O or 1. In individual cases, a fault can be detected, for example, by comparing the oscillation frequency at the outputs 12 and 13 of the monitored totalizer with the control one. It is also possible

the difference between faults among themselves, as can be seen from the table.1 ...,

The uncertainty of the initial state also has no effect on the functioning of the faulty monitored adder, as can be seen from Tables 20–25, where, for different initial states, a fault type X2 0 was simulated.

The delay element 2 serves to delay the signal per clock (defined as m + V 2 g + 2 7 where r, g, g, t are the delay times, respectively, on the switch, modulo two, the element I, the element NOT) the generation frequency, and

delay element 3 — to equalize the signal arrival time at the input of the switch, which is determined by the delay of the HE element 4.

Claims (1)

Invention Formula Controlled adder containing the first and second modulo two, the first, second and third elements And, with the first input of the first modulo two adder connected to the first inputs The first and second elements And the second input of the first modulo two adder is connected to the second input of the first and first inputs of the third And elements, the third input of the first modulo two adder is connected to the second inputs of the second and third And elements, the outputs of the first, second and third And elements connected respectively to the first, second and third inputs of the second modulo two, the output of which is the transfer output of the controlled adder, the output of the sum of which is connected to the output of the first modulo-two adder, characterized in that, in order to increase the completeness of the control, it contains two delay elements, a NOT element and a switch, the first group of information inputs of which are connected to the information inputs of the monitored adder, the second group of information inputs the switch is connected to the outputs of the first and second delay elements and the NOT element, respectively, the input of which is connected to the input of the second delay element and the transfer output of the monitored adder, the output of which is connected to the input of the first delay element, and table 5  HZ g S J P50 I X2 Xi Table 2k