SU1628186A1 - Four-phase mis flip-flop - Google Patents

Abstract

The invention relates to the dust technique and microelectronics and can be used in the launching of electronic keyboard computing maigin or other digital devices. The purpose of the invention is to expand the field of application by providing a four-phase trigger when the power is turned on. The trigger contains the -or- element OR- NOT 1, plug-in NOT 2, output bus 3, input bus 4, phase buses 5-8, pini bus 14. In order to achieve this goal, MIS transceivers 0-12, capacitor 13 are inserted. and a trigger set to a particular state without an additional external signal. 2 yl.

Description

1

The invention relates to computing technology and microelectronics, but can be applied to the design of electronic keyboard computing machines (ECM). Or other digital devices,

The purpose of the invention is to expand the scope of application by providing

the potential that opens the transistor 12 and charges the parasitic capacitance of the gate of the transistor 12. Through the open transistor 12, the output of the OR-NOT element and the output bus 3 are set to state 1. At the same time, the opening potential flows to the gates of transistors 9 and 10, with the result that

self-installation of four-phase MDP-trig-yu output element NOT 2 and input bus 4

Hera when turning on the power. Connect to the phase bus 70

Fig. 1 shows the trigger-circuit. After power is turned on, it starts

Hera; in fig. 2 - timing diagram of the operation of the phase impulse phase generator.

pulses, which is a part of the four-phase MDP-trigger, contains 15 ° and microcircuits together with a trigger.

the element OR-NOT 1, the element NOT 2, the output bus 3, the input bus 4, the first 5, the second 6, the third 7 and the fourth 8-phase bus, MOS transistors 9-12, capacitor 13, bus 14 power 20 or , the charge transistor 15 of the element OR NONE, the clocked transistor 16 of the element OR NONE, the charging transistor 17 of the element NO, the clocked transistor 18 of the element NO, the logical transistors 25, 19, 20 and 21. The output of element 1W-NOT 1 is connected to the input of element NO 2 and to the output bus 3. The first input of element OR-NOT 1 is connected to s. As a result of the phase generator running on buses 5-8, phase impulses are generated in accordance with the diagram shown in FIG. These pulses arrive at the corresponding inputs of the transistors 15-18 and simultaneously the value of the signals located on the gates of the logic transistors 19, 20 and 21 is determined

trigger state.

i

i

After power up on bus 14

a series of phase pulses begins to form with oj.Horn of four potential, opening transistor 12 and charging the parasitic capacitance of the gate of transistor 12. Through the open transistor 12, the output of the OR-NOT element and the output bus 3 are set to state 1. At the same time, the phase pulse generator functions , part of the integral and the microcircuits together with the trigger.

As a result of the phase generator on the buses 5-8, phase pulses are generated in accordance with the diagram shown in Fig. 2. These pulses are fed to the corresponding inputs of the transistors 15-18 and simultaneously with the value of the signals on the gates of the logic transistors 19, 20 and 21, are determined

trigger state.

i

i

After power up on bus 14

a series of phase pulses begins to form with oj.Horn of four possible

the course of the element is NOT., and the second input is about ttyuis. The first beat is the presence

with input bus 4, source and gate of charging transistor 15 - with first phase bus 5 and gate transistor 11, gate of clocked transistor 16 - with phase bus 6, source and gate of charge transistor 17 of the HE element 2 - with phase bus 7 and c the sources of transistors 9, 10 and 11, the gate of a clocked transistor 18 of the HE 2 element - with the phase bus 8, the drains of the transistors 9 and 10 - with the first and second inputs of the OR-NO element, respectively, and their gate with the drain of the transistor 11 and with the gate of the transistor 12, the drain of which is connected to the output of the element OR NOT “

The capacitor 13 is connected between the source and the gate of the transistor 12, the source of which is connected to the supply bus 14 Element OR NONE 1 consists of transistors 15, 16, 19 and 20 o. Element NOT 2 consists of transistors 17, 18 and 21.

The trigger works as follows.

When the power is turned on on the bus 14, a constant voltage rises, as a result, through the condenser to the gate of the transistor 12 enters

one

40

but ,,

4b

1 pa bus 5; the second cycle - the presence of 1 on the bus 6 while O at the same time on nim.t 5; friction so 1 - the presence of 1 on the tire 7; the fourth pact is the presence of i on bus 8 while O is on stream 7. Gels after the supply of bus on bus 14 a series of phase impulses begin to form from the first, second or fourth cycles, t et when there is a signal O on bus 7, the element output HE 2 and the input bus 4 is set to state O. If a series of phase pulses starts to form from the third cycle,

d e. when it is present on bus 7 and

3

signal 1, then setting O at the output of the element HE 2 occurs after the phase of the phase pulse on the bus 7 terminates. When a phase pulse arrives at the bus 5 connected to the charging transistor 15 of the element OR NOT 1 and the gate of transistor 11, the latter opens and zeroes the gates of transistors 9, 10 and 12, connecting them to a phase spike 7, at which moment O is located. As a result, transistors 9, 10 and 12 are closed and do not affect the operation of the trigger signal.

Subsequently, after the initial start-up program is executed, the trigger is set to the state O by transferring bus 4 to signal at the input of the element OR NOT HE Signal 1 arriving at line 4 is formed inside the integrated circuit, and the type of clocking of the phase logic element on which this signal should correspond to the type of clocking of the element. HE 2 Resetting the trigger can only be done after turning off and on the bus 14

Claims (1)

Invention Formula A four-phase MDS trigger containing input, output, phase buses and power supply, an ILN-NE element and a NOT element, including charging, clocked and logic transistors, the output of the OR-NOT element is connected to the output bus and the input is an NOT element, the output which is connected to the first input of the element OR NOT, the second input of which is connected to the input bus, the source and the gate of the charging transistor of the element OR is NOT connected to the first phase bus and the drains of its first and second logical transistors, the gate of its clocked transistor to the second phases bus, and the drain - from the sources of its first and second logic transistors, the source and gate of the charging transistor of the element NOT ten 15 20 25 thirty 35 86 connected to the third phase bus and to the drain of its logical transistor, the gate of a clocked transistor of the NOT element to the fourth phase bus, its drain from the source of the logical transistor of the element NOT, and its source to the drain of the charging transistor of the element NO and the output of the element NO, the source of a clocked the transistor of the element OR is NOT connected to the drain of the charging transistor of the element OR — NOT and its output, the gates of the first and second logical transistors of the element OR — NO are connected respectively to the first and second inputs of the element OR — NOT, differing Due to the fact that, in order to expand the scope of use by providing self-installation of the trigger when the power is turned on, four transistors and a capacitor are inserted in it, the sources of the first, second and third transistors being connected to each other and connected to the third phase bus, the drains of the first and second transistors connected respectively to the first and second inputs of the element OR NOT, and their gates are connected to the drain of the third transistor and the gate of the fourth transistor, the drain of which is connected to the output of the element OR NOT, the gate ter its transistor connected to a first phase bus, the source of the fourth transistor through a capacitor connected to the gate chetrertogo transistor and connected to the power bus., w% w