JPH1188132A - Pulse generating circuit and image sensor using the circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pulse generating circuit that generates a pulse train where each pulse has an optional width with a simple configuration. SOLUTION: In the pulse generating circuit that employs a plurality of circuits each in which an intermediate signal Y2 that changes from a leading edge of an input signal Z1 with a prescribed time constant is produced by using a delay circuit consisting of a capacitor C2 and a resistor R2, a NAND gate 5 receiving signals Z1, Y2 provides an output of a pulse Z2 with a prescribed width and an output of the pre-stage is used for an input of a next stage as the series connection circuits, a diode D1 is connected in parallel with the resistor R2 to make an impedance of a charging path of the capacitor C2 negligibly smaller than the impedance of a discharge path. In this case, charges are rapidly charged at the time of charging and charges are discharged according to a regular time constant at the time of discharge. Thus, even when the time constant is set larger to increase the output pulse width, since the rise speed of the charging is fast, the signal Y2 is raised sufficiently faster and the output pulse width is optionally set without being limited by the pulse width of the pulse Z1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a pulse generating circuit, for example, a pulse generating circuit for generating a pulse train for driving an output differentiating circuit of an image sensor, and an image sensor device using the same.

[0002]

2. Description of the Related Art Conventional pulse generation circuits include:
For example, "Kunio Inoki" Design of Digital System "C
Q Publishing Co., Ltd. Published the 13th edition on August 20, 1986
Page 19 ". This circuit is a circuit for outputting only one pulse having a predetermined width in accordance with a rising edge of an input signal. To briefly explain the configuration, first, an input signal X is introduced into a CR delay circuit including a resistor R and a capacitance C via an inverter. The output Y of this CR delay circuit is connected to one input of a NAND gate,
An input signal X is connected to the other input of the ND gate. If the input signal X is in the "low" state, C
The output Y of the R delay circuit is "high", and therefore, the output Z of the NAND gate is "high". When the input signal X changes to "high" from that state, the electric charge accumulated in the capacitance C is discharged through the resistor R and the inverter, so that the output Y of the CR delay circuit gradually falls. And until the Y is less than the threshold value V _T of the NAND gate, the output Z of NAND gate is "low". When Y becomes smaller than the threshold value V _T , the output Z returns to “high”, and thereafter, even if the input signal X falls, the output Z remains “high”. That is, each time the input signal X changes from "low" to "high", one pulse is output in accordance with the rising edge. The pulse width of this pulse becomes a value corresponding to the time constant of the CR delay circuit. It is considered that a circuit that outputs a plurality of pulses with a phase shift for each circuit can be configured by connecting the circuits as described above in multiple stages in series.

FIG. 9 shows a circuit in which two circuits for outputting one pulse as described above are connected in series, and a pulse which is out of phase for each circuit is output. FIG. 10 shows a signal of each part in FIG. It is a waveform diagram. In FIG. 9, an input signal X (strobe pulse) is input via an inverter 1 to a delay circuit including a resistor R1 and a capacitance C1. Also, N
The two input terminals of the AND gate 2 receive the input signal X
And the output Y1 of the delay circuit. The above part is the first-stage pulse generation circuit. As described above, the inverter 4, the delay circuit including the resistor R2 and the capacitance C2, and the NAND gate 5 constitute a second-stage pulse generation circuit. The output Z1 of the first-stage NAND gate 2 is provided as an input signal of the second-stage pulse generation circuit. Reference numerals 3 and 6 denote inverters, which respectively output the outputs Z1 and Z2 of the NAND gate 2 in the first stage.
The output Z2 of the NAND gate 5 at the stage is inverted and output as the output T1 of the pulse generator at the first stage and the output T2 of the pulse generator at the second stage. With the configuration described above, two pulses having phases shifted from each other can be output as shown in T1 and T2 in FIG. 10. If the pulse is connected in multiple stages, a pulse train having the number of pulses corresponding to the number of stages can be output. It is thought that it can be obtained.

As a general method of sequentially generating pulses having different pulse widths, a method of counting clocks is used. That is, a method of generating a clock in accordance with the rising edge of the strobe, counting the clock, and outputting a pulse that continues from a certain number to a certain number.

[0005]

However, in the case of a circuit in which conventional pulse generating circuits are connected in series in multiple stages as described above, there are the following problems, which cause practical problems. Hereinafter, description will be made with reference to FIGS. 9 and 10. First stage N
While the output Z1 of the AND gate 2 is "high", the output Y2 of the second delay circuit is in the "low" state. When the output Z1 changes to "low" from this state, the output Y2 rises with a predetermined time constant, and becomes as shown by the broken line of Y2 in FIG. Thereafter, when the output Z1 returns to "high", Y2 starts to fall. From the point in time when the output Z1 returns to "high", the output Y2
There until equal to or less than the threshold value V _T, the output Z2 of the second-stage NAND gate 5 becomes "low", it outputs the pulse T2 of the second stage in correspondence with is output. As described above, the output Y2 of the second stage rises and falls in response to the “low” and “high” changes of the output Z1 of the first stage. Product R of resistance R2 and capacitance C2
2 · C2. And the second stage NAND gate 5
In order to increase the pulse width of the output Z2 (corresponding to the pulse circuit output T2 of the second stage), it is necessary to make the fall of the output Y2 of the second stage slow.
C2 must be increased. However, R2 ・ C2
Is increased, the rise of the output Y2 is naturally delayed, and the output Y2 becomes as shown by a solid line in FIG. When the output Z1 began falling is Y2 back to "high", if not exceed the value threshold V _T of Y2, the output Z2 of the second-stage NAND gate 5, as shown by the solid line "high" In this state, the output T2 of the second stage is not output.

As described above, in the circuit of FIG. 9, if the pulse width of the output T2 of the second stage is to be increased, the charging time of the delay circuit is lengthened, that is, the output Z1 of the first stage is output.
The pulse width of the subsequent stage is limited by the output pulse width of the previous stage, and each pulse cannot form a pulse train having an arbitrary pulse width.
There was a problem. For example, in a circuit for controlling the output of an image sensor, a plurality of pulses having different phase-shifted pulse widths are required, but it is difficult to obtain a plurality of pulses having different pulse widths in the multistage connection circuit as described above. there were.

Further, the conventional method of counting clocks has a problem in that a high frequency clock is required, so that much noise is generated. In addition, a counter for counting clocks is required. In particular, when the widths of the respective pulses are significantly different, the number of times of counting must be increased, and the circuit scale becomes large. Was.

The present invention has been made to solve the problems of the prior art as described above. A first object of the present invention is to form a pulse train having a simple configuration and each pulse having an arbitrary pulse width. It is an object of the present invention to provide a pulse generating circuit capable of performing the above. A second object is to provide an image sensor device that can output a differential image whose edge can be easily detected by a small-scale additional circuit using the above-described pulse generation circuit.

[0009]

Means for Solving the Problems In order to achieve the above object, the present invention is configured as described in the claims. First, according to the first aspect of the present invention, an intermediate signal that gradually changes with a predetermined time constant from a rising edge of an input signal is generated using a capacitance, and a logical operation of the input signal and the intermediate signal is performed. A pulse generating circuit that generates a pulse of a predetermined width by using a plurality of pulse generating circuits, and is connected in series so that an output of the preceding pulse generating circuit becomes an input of the next-stage pulse generating circuit. The configuration is such that the impedance of the charging path between the capacitance and the power supply is set to be negligibly small compared to the impedance of the discharging path between the capacitance and the ground.

[0010] With the above-described configuration, charging is rapidly performed when charging the capacitance, and discharging is performed with a regular time constant when discharging. Therefore, even if the time constant is set to a large value in order to increase the output pulse width, the charge rises quickly, so that the intermediate signal can be sufficiently started. Therefore, a pulse having an arbitrary pulse width can be output without being limited to the output pulse width of the preceding stage. If such a pulse generation circuit is connected in multiple stages, each pulse has an arbitrary pulse width. A pulse train can be created with a simple circuit. The above configuration corresponds to, for example, an embodiment shown in FIG. 1, FIG. 3, or FIG. The above-mentioned intermediate signal is, for example, as shown in FIG.
This corresponds to the outputs Y1 and Y2 of the delay circuit in FIG.

A second aspect of the present invention relates to a more specific configuration of the first aspect, wherein a unidirectional element (for example, a diode or a transistor) is connected in parallel with the resistance of the charging / discharging path, and the static electricity is discharged. The discharge is limited and discharged from the capacitance via a resistor, and the charge current flows rapidly without passing through the resistor during charging. The above configuration corresponds to, for example, an embodiment shown in FIG. 1 described later.

A third aspect of the present invention is a more specific configuration of the first aspect, wherein a switching element that is turned on during charging is connected between the capacitance and the power supply, and the capacitance is reduced from the capacitance during discharging. The discharge current is limited and discharged via the resistor, and the charge current flows rapidly without passing through the resistor during charging.

Next, a fourth aspect of the present invention is directed to the first aspect.
Conversely, it is a circuit that generates a pulse synchronized with the falling edge of the input signal, in which the impedance of the discharge path between the capacitance and the ground is set to be negligible compared to the impedance of the charging path. is there. With such a configuration, discharging is rapidly performed when discharging the capacitance, and charging is performed with a regular time constant when charging. Therefore, even if the time constant is set to a large value in order to increase the pulse width to be output, the intermediate signal can sufficiently fall because the fall time at the time of discharge is fast.
Therefore, without being limited to the output pulse width of the previous stage,
Since a pulse with an arbitrary pulse width can be output,
If such a pulse generation circuit is connected in multiple stages, a pulse train having an arbitrary pulse width for each pulse can be formed by a simple circuit. The above configuration corresponds to, for example, an embodiment shown in FIG.

[0014] Claims 5 and 6 show a more specific configuration of claim 4, and claim 5 corresponds to claim 2 above, and claim 6 corresponds to claim 3 above. This is a corresponding configuration. The configuration of claim 5 corresponds to, for example, the embodiment shown in FIG. 1 described later, in which the direction of the diode is reversed (detailed description follows FIG. 5). In the embodiment shown in FIG.
This corresponds to a configuration in which ET7 is deleted and an n-type MOSFET is connected in parallel with the capacitance C2 (detailed description is described next to FIG. 5).

Next, the invention according to claim 7 is based on claim 1.
An image sensor device to which the pulse generation circuit according to any one of claims 1 to 6 is applied, wherein the circuit for generating a control pulse for controlling three switches of the image sensor device is provided. In the pulse generation circuit described above, a circuit in which three stages are connected in series is used. The above configuration corresponds to, for example, an embodiment shown in FIG. 7 described later.

[0016]

According to the present invention, a pulse having an arbitrary pulse width can be output without being limited by the output pulse width of the preceding stage. If such pulse generation circuits are connected in multiple stages, a pulse train having an arbitrary pulse width for each pulse can be produced. In addition, since a high-frequency clock is not required, noise is small, and the same circuits may be arranged by the number of pulses, so that the circuit can be simplified and the scale can be reduced. Further, by applying the pulse generation circuit of the present invention as a control pulse for controlling each switch of the output differentiation circuit of the image sensor, a differential image can be obtained with a simple configuration without using a counter or the like. Is obtained.

[0017]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and FIG. 2 is a signal waveform diagram in FIG. First, the configuration will be described. X is an input signal (strobe pulse), 1 is an inverter, 2 is a NAND gate, R
Reference numeral 1 denotes a resistor, C1 denotes a capacitance, and these portions form a first-stage pulse generation circuit. Reference numeral 4 denotes an inverter, 5 denotes a NAND gate, R2 denotes a resistor, C2 denotes a capacitance, and D1 denotes a diode. These parts form a second-stage pulse generation circuit. And the first stage NAN
The output Z1 of the D gate 2 is connected as a second-stage input signal. The resistor R1 and the capacitance C1 form a delay circuit, and the output is Y1. The resistor R2, the capacitance C2, and the diode D1 also form a delay circuit, and the output is Y2. Reference numeral 3 denotes an inverter, which inverts the output Z1 of the NAND gate 2 in the first stage to generate an output pulse T1 in the first stage. Similarly, reference numeral 6 denotes an inverter, which inverts the output Z2 of the second-stage NAND gate 5 to 2
This is the output pulse T2 of the stage. In FIG. 1, the signals obtained by inverting Z1 and Z2 are output pulse T
1, T2, but Z1 and Z2 can be used as they are.

In the delay circuit of the second stage, the cathode of the diode D1 is connected to the capacitance C2 and the anode is connected to the output of the inverter 4. The capacitance C2 is charged from the power supply via the inverter 4. In this case, the diode D1 conducts to short-circuit the resistor R2. Conversely, when the capacitor C2 discharges to the ground terminal via the inverter 4, the diode D1 is cut off and the resistor R2 is inserted. It is configured to be.

The operation will now be described with reference to FIGS. First, in the first-stage pulse generation circuit, the input signal X is applied to the resistance R1 and the capacitance C via the inverter 1.
1 is introduced into the delay circuit. The output Y1 of the delay circuit is connected to one input of the NAND gate 2,
An input signal X is connected to the other input of the ND gate 2. Here, when the input signal X is in the “low” state, the output of the inverter 1 is “high”, and the capacitance C1 is equal to the resistance R.
1 and a predetermined time constant, and the output Y1 is “high”.
become. Therefore, the output Z1 of the NAND gate 2 becomes "high". When the input signal X changes from that state to “high”,
Since the charge accumulated in the capacitance C1 is discharged with a predetermined time constant via the resistor R1 and the inverter 1, the output Y1 of the delay circuit gradually falls. And the input signal X
Between but rises to "High" until the Y1 becomes equal to or smaller than the threshold V _T of NAND gate 2, the output Z1 of the NAND gate 2 becomes "low". The Y1 threshold V _T becomes smaller than the output Z1 is returned to "high", then the input signal X
Falls, the output Z1 remains "high". A signal obtained by inverting the output Z1 by the inverter 3 is set as an output pulse T1 of the first stage. That is, each time the input signal X changes from "low" to "high", one pulse T1 is output in accordance with the rising edge.

Next, in the pulse generation circuit of the second stage, the output Z1 of the first stage is connected to the resistor R2
, A capacitance C2 and a diode D1. The output Y2 of the delay circuit is the NAND gate 5
The first stage output Z1 is connected to the other input of the NAND gate 5.

Here, when the output Z1 of the first stage becomes "low", the output of the inverter 4 becomes "high" and the capacitance C2 is charged. In this case, since the diode D1 is in the forward direction, the diode D1 conducts and short-circuits the resistor R2. Therefore, the capacitance C2 is rapidly charged and the output Y
1 goes "high" in a short time. When the output Z1 of the first stage changes from this state to “high”, the output of the inverter 4 becomes “low”, and the electric charge accumulated in the capacitance C2 is discharged. However, in this case, since the diode D1 is in the opposite direction, the electric charge of the capacitance C2 is slowly discharged with a predetermined time constant via the resistor R2 and the inverter 4.
The output Y2 of the delay circuit gradually falls. Then, after the output Z1 of the first stage rises to “high”, the above Y2 becomes NA
Until the voltage _falls below the threshold value VT of the ND gate 5, the NAND
The output Z2 of gate 5 goes "low". Y2 is the threshold value V
_When it becomes smaller than _T , the output Z2 returns to "high".

As described above, in the pulse generating circuit of the second stage, the resistor R2 is short-circuited when the capacitance C2 is charged, so that the charging is rapidly performed. Discharge is performed with the time constant R2 · C2. Therefore, even if the time constant by C2 and R2 is set to a large value in order to increase the pulse width of the output Z2 of the second stage (and thus T2), the output Y2 can be sufficiently raised because the rise is fast. . Therefore, the pulse width of the output Z2 of the second stage can be arbitrarily set without being limited by the pulse width of the output Z1 of the first stage. For example, FIG. 2 shows a case where the pulse width of the output Z2 of the second stage is set to a larger value than the output Z1 of the first stage.

As described above, by adding the diode D1 to make the impedance of the charging path of the capacitance C2 negligibly small as compared with that of the discharging path, it is not limited to the output pulse width of the preceding stage. A pulse having an arbitrary pulse width can be output. If such pulse generation circuits are connected in multiple stages, a pulse train having an arbitrary pulse width for each pulse can be produced.

The circuit of this embodiment has a simple configuration including a CR delay circuit and a diode, does not require a high-frequency clock, has little noise, and does not require a counter. Can be realized.

In the circuit shown in FIG. 1, a case is shown in which a diode is not provided in the first stage pulse generating circuit, but a pulse generating circuit having a diode as in the second stage is also provided in the first stage. Of course, it may be used.

Next, FIG. 3 is a circuit diagram showing a second embodiment of the present invention. In FIG. 3, 7 is a p-type MOSF.
ET, and the same reference numerals as those in FIG. 1 denote the same components.
The p-type MOSFET 7 has a source connected to the power supply, a drain connected to a connection point between the capacitance C2 and the resistor R2, and a gate connected to the first-stage output Z1 (second-stage input).

The operation will be described below. Second stage input Z1
Changes from “high” to “low”, the p-type MOSFET 7
Turns on, and connects the capacitance C2 to the power supply. As a result, the capacitance C2 is immediately charged. On the other hand, when the input Z1 of the second stage changes from “low” to “high”, the p-type MO
Since the SFET 7 is turned off and the electric charge of the capacitance C2 is discharged via the resistor R2, it can be discharged only gradually,
The time constant at that time is R2 · C2. Other basic operations are the same as those in FIG. Therefore, FIG.
Also in the case of FIG. 1, as in FIG. 1, the impedance of the charging path of the capacitance C2 can be made negligibly smaller than that of the discharging path, so that it is not limited to the output pulse width of the preceding stage. A pulse having an arbitrary pulse width can be output.

In the circuit of this embodiment, C
Simple configuration with R delay circuit and MOSFET etc.
Since a high-frequency clock is not required, noise is small, and a counter is not required.

In the circuit shown in FIG. 3, a case where no MOSFET is provided in the first-stage pulse generation circuit is exemplified. However, a pulse generation circuit provided with a MOSFET as in the second stage is also provided in the first stage. Of course, it may be used.

When the circuits are integrated on the same substrate, there is an advantage that the use of the MOSFET as shown in FIG. 3 can be more easily realized than the use of the diode as shown in FIG. That is, since both ends of the diode D1 in the circuit of FIG. 1 are away from the power supply or the ground, when a pn junction having such a connection is formed in the substrate, a parasitic bipolar transistor is formed at the same time. In order to avoid the adverse effects of the parasitic bipolar transistor, various measures are required on the substrate configuration, and the manufacturing process becomes complicated. On the other hand, when a MOSFET is formed, the above problem does not occur, and the MOSFET can be formed by a simple process.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention. In FIG. 4, 8 and 10 are p
Type MOSFETs 9 and 11 are n-type MOSFETs, and the same reference numerals as those in FIG. In this circuit, instead of inverters 1 and 4 in FIG.
Type MOSFETs 9 and 11 are provided. In the first stage circuit, the source of the n-type MOSFET 9 is grounded,
The drain is at one end of the resistor R1, the gate is at the input signal X,
Each is connected. In the second-stage circuit, the source of the n-type MOSFET 11 is connected to the ground, the drain is connected to one end of the resistor R2, and the gate is connected to the first-stage output Z1 (the second-stage input).

The operation of the first-stage circuit will be described below. The same applies to the second stage. When the input signal X changes from “high” to “low”, the p-type MOSFET 8 turns on and connects the capacitance C1 to the power supply.
Is charged immediately. At this time, the n-type MOSFET 9 is off. On the other hand, when the input signal X changes from “low” to “high”, the p-type MOSFET 8 is turned off, and the n-type MOSFET 8 is turned off.
Since the SFET 9 is turned on, the capacitance C1 is grounded via the resistor R1, and the electric charge of the capacitance C1 is changed to the resistance R1.
Is gradually discharged. The time constant at that time is R1 ·
C1. Other basic operations are the same as those in FIG.

Therefore, in the case of FIG. 4, as in FIG. 1, the impedance of the charging path of the capacitances C1 and C2 can be made negligibly smaller than that of the discharging path. It is possible to output a pulse having an arbitrary pulse width without being limited to the above.

The inverter used in the circuit of FIG.
Generally, it is constituted by a pair of p-type and n-type MOSFETs. Therefore, if configured as shown in FIG.
The number of components can be reduced as compared with FIG. 3, and the same function can be realized with a simple circuit.

In the circuit of the present embodiment, C
Simple configuration with R delay circuit and MOSFET etc.
Since a high-frequency clock is not required, noise is small, and a counter is not required.

Although the same circuit as that of the second stage is used as the first stage pulse generating circuit in the circuit of FIG. 4, a circuit using an inverter may be used as in FIG. .

Next, FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention, and FIG. 6 is a signal waveform diagram in FIG. In the first to third embodiments described above, the circuit that generates a pulse in synchronization with the rising edge of the input signal has been described. However, the pulse is generated in synchronization with the falling edge of the input signal. The present invention can be applied to a circuit. This embodiment relates to the above configuration.

In FIG. 5, reference numerals 12 and 13 denote NOR gates, and the same reference numerals as those in FIG. 4 denote the same parts. That is, the circuit of FIG. 5 replaces the NAND gates 2 and 5 in the circuit of FIG. 4 with NOR gates 12 and 13 and connects a resistor between the drain of the p-type MOSFET and the drain of the n-type MOSFET. A capacitance is connected to a connection point between the drain of the MOSFET and the resistor, and the connection point is connected to N
It is connected to one input terminal of an OR gate.

The operation of the first-stage circuit will be described below. The same applies to the second stage. When the input signal X changes from "low" to "high", the p-type MOSFET 8 is turned off and the n-type MOSFET 9 is turned on, so that the capacitance C1 is directly grounded through the n-type MOSFET 9,
The charge is immediately discharged. On the other hand, when the input signal X changes from “high” to “low”, the p-type MOSFET 8 turns on, and the capacitance C1 is connected to the power supply via the resistor R1. At this time, the n-type MOSFET 9 is off. Therefore, the capacitance C1 is gradually charged via the resistor R1, and the time constant at that time is R1 · C1. Until the time when the output Y1 of the circuit delay from when the input signal X is changed to "low" to "high" (circuit composed of the resistor R1 and the capacitance C1) exceeds the threshold value V _T, NOR The output Z1 of the gate 12 becomes "high".

As described above, in the circuit of FIG. 5, the time constant R1 · C is synchronized with the falling edge of the input signal X.
A pulse having the pulse width set in step 1 is output. Since the impedance of the discharge path of the capacitances C1 and C2 can be made negligibly smaller than that of the charge path, a pulse having an arbitrary pulse width is output without being limited to the output pulse width of the preceding stage. I can do it.

Also, in the circuits of FIGS. 1 and 3, a pulse having a pulse width set by the time constant RC is output in synchronization with the falling edge of the input signal in the same manner as described above. Can be done. First, in the circuit of FIG. 1, the connection direction of the diode D1 is reversed.
That is, the cathode of the diode D1 is connected to the inverter 4 side, and the anode is connected to the capacitance C2 side. With this connection, the capacitance C from the power supply via the inverter 4
2 is charged, the diode D1 is cut off and the resistor R2 is inserted. Conversely, when the capacitance C2 is discharged to the ground terminal via the inverter 4, the diode D1 conducts and the resistor R2 is shorted. Therefore, the impedance of the discharge path of the capacitance C2 can be made negligibly small compared to that of the charge path. If a NOR gate is used instead of the NAND gates 2 and 5, a pulse having a pulse width set by the time constant RC can be output in synchronization with the falling edge of the input signal, as in FIG. A pulse having an arbitrary pulse width can be output without being limited to the output pulse width of the preceding stage.

Also, in the circuit of FIG.
The FET 7 is deleted, and instead an n-type MOSFET is connected in parallel with the capacitance C2, ie, an n-type MOSFET
Is connected to the connection point between the resistor R2 and the capacitance C2, the drain is connected to ground, and the gate is connected to the input signal Z1. With such a configuration, at the time of charging, the capacitor is charged through the resistor R2, and at the time of discharging, it is immediately discharged through the n-type MOSFET. Therefore, similarly to the circuit of FIG.
The impedance of the second discharge path can be made negligibly smaller than that of the charge path. And NA
If NOR gates are used instead of the ND gates 2 and 5,
As in FIG. 5, a pulse having a pulse width set by the time constant CR can be output in synchronization with the falling edge of the input signal, and any pulse can be output without being limited to the output pulse width of the preceding stage. A pulse having a pulse width can be output.

In the circuit of this embodiment, C
Simple configuration with R delay circuit and MOSFET etc.
Since a high-frequency clock is not required, noise is small, and a counter is not required.

FIG. 7 is a block diagram showing a fifth embodiment of the present invention, and FIG. 8 is a waveform diagram showing signal waveforms and switching timings of the switching circuits S1 to S3 in FIG.

In this embodiment, the pulse generation circuit described in the first to fourth embodiments is applied as a control pulse generation circuit of an image sensor. In FIG. 7, reference numeral 21 denotes an image sensor such as a CCD or MOS type,
22 is a buffer circuit, 23 is a differential amplifier, S1, S2,
S3 is a switch. Reference numeral 31 denotes a pulse generation circuit (2) of the same type as the first stage in the first to fourth embodiments.
32 and 33 are pulse generation circuits of the same type as the second stage in the first to fourth embodiments. In this way, a circuit that generates three pulses by connecting the pulse generation circuits in three stages in series is used. The first stage is a pulse T1 for S1, and the second stage is a pulse T2, 3 for S2.
The stage is used as a pulse T3 for S3.

In the apparatus shown in FIG. 7, the output of the image sensor 21 is input to a sample and hold circuit composed of a switch S2 and a buffer circuit 22, and is sampled and held. The output of the buffer circuit 22 is a switch S3,
The differential amplifier 23 is connected to the + input and the − input of the differential amplifier 23 via S1, and outputs the difference value between the two.

The operation will be described below with reference to FIG. The switch S1 is turned on in accordance with the rising edge of the strobe signal X supplied from the outside, and is turned off after a predetermined time. Next, the switch S2 turns on in synchronization with the turn-off of the switch S1, and turns off after a predetermined time. Further, the switch S3 turns on in synchronization with the turn-off of the switch S2, and turns off after a certain time. By driving in this manner, a differential output of the image sensor 21 can be obtained.

That is, each pixel of the image sensor 21 is sequentially scanned, and a voltage proportional to the input light at each pixel is sequentially output. The output is sampled when the switch S2 is turned on, and is held when the switch S2 is turned off. Next, the switch S3 is turned on and sends the current output signal to the + input of the differential amplifier 23. Then, before the next pixel is sampled by the switch S2, the switch S1 turns on and sends the output of the current pixel to the-input of the differential amplifier 23. Therefore, the next time the switch S3 is turned on, the differential amplifier 23
The input holds the output of the previous pixel, and the + input receives the output of the current pixel. as a result,
The difference between the current pixel and the previous pixel, that is, the value of the difference between the next pixel and the next pixel is the output of the differential amplifier 23. As described above, for example, by scanning the image sensor in the horizontal direction and reading it out, FIG.
The output of the differential amplifier 23 in the circuit described above is a differential image in the horizontal direction. In this way, a differential image can be obtained with a simple circuit. From the differential image, the edge of the captured image (the point at which the image changes from light to dark or dark to light: for example, indicating the end of a road or the end of a white line) can be detected relatively easily, so the original image is left as it is. Image processing is easier than using.

When controlling the opening and closing of the switches S1 to S3 in the circuit of FIG. 7, control pulses T1 to T3 having the same waveform as S1 to S3 of FIG. 8 are required. That is,
Rises in synchronization with the fall of the previous pulse, and
A pulse having an arbitrary pulse width is required. Therefore, in the pulse generation circuit described in the first to fourth embodiments, as shown in FIG.
The first stage is a pulse T1 for S1, the second stage is a pulse T2 for S2, and the third stage is S3.
Can be used as the pulse T3 for use.

As described above, by using the pulse generating circuit of the present invention as a control pulse for each switch of an image sensor, a small-sized additional circuit alone without a digital circuit such as a counter can be used for edge detection and the like in post-processing. An image sensor device that can easily obtain a differential image can be realized.

Further, in the pulse generation circuits described in the first to fourth embodiments, the high frequency clock is not required, so that the noise is small. Also, a pulse of an arbitrary pulse width can be output irrespective of the pulse width of the preceding stage, and the same circuit may be arranged by the number of pulses.
The circuit is simple and the scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform chart showing signal waveforms in FIG.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 6 is a waveform chart showing signal waveforms in FIG. 5;

FIG. 7 is a block diagram showing a fifth embodiment of the present invention.

8 is a diagram showing signal waveforms and switches S1 to S in FIG.
FIG. 3 is a waveform chart showing opening and closing timings of FIG.

FIG. 9 shows a pulse generation circuit that can be considered from the related art.

FIG. 10 is a waveform chart showing signal waveforms in FIG. 9;

[Explanation of symbols]

1. Inverter 2. NAND
Gate 3, 4 ... Inverter 5 ... NAND
Gate 6 ... Inverter 7, 8 ... P-type MOSFET 9 ... N-type MOSFET 10 ... P-type MO
SFET 11 ... n-type MOSFET 12, 13 ...
NOR gate 21 ... Image sensor 22 ... Buffer circuit 23 ... Differential amplifier 31 ... Pulse generation circuit of the same type as the first stage 32, 33 ... Pulse generation circuit of the same type as the second stage S1, S2, S3 ... Switch D1 ... Diode R1 ... Resistance R2 ... Resistance C1 ... Capacitance C2 ... Capacitance X ... Input signal (strobe pulse) Z1 ... Output of NAND gate 2 of the first stage Z2 ... Output of NAND gate 5 of the second stage Y1 ... Resistance R1 Output of delay circuit composed of capacitance C1 Y2 ... Output of delay circuit composed of resistance R2 and capacitance C2 T1 ... Output pulse of first stage T2 ... Output pulse of second stage T3 ... Output pulse of third stage

Claims (7)

[Claims] 1. An intermediate signal that gradually changes with a predetermined time constant from a rising edge of an input signal using a capacitance, and a pulse having a predetermined width is generated by a logical operation of the input signal and the intermediate signal. A plurality of pulse generation circuits, and a pulse generation circuit connected in series such that an output of the preceding pulse generation circuit is an input of the next stage pulse generation circuit, and a charging path between the capacitance and a power supply. The impedance of
A pulse generation circuit, wherein the pulse generation circuit is set to be negligibly small compared to the impedance of a discharge path between the capacitance and the ground. 2. The discharge path is discharged by limiting a discharge current from the capacitance via a resistor, and the charge path is connected in parallel with the resistor so that the charge current flows without passing through the resistor. The pulse generation circuit according to claim 1, wherein a unidirectional element is connected to the pulse generator. 3. The discharge path is discharged by limiting a discharge current from the capacitance via a resistor, and the charging path is configured such that the charge current flows without passing through the resistance. The pulse generating circuit according to claim 1, wherein a switching element is connected between the power supply and the power supply. 4. An intermediate signal which gradually changes at a predetermined time constant from a falling edge of an input signal using a capacitance, and a pulse having a predetermined width is generated by a logical operation of the input signal and the intermediate signal. A pulse generation circuit that uses a plurality of pulse generation circuits to be generated and is connected in series so that an output of a pulse generation circuit of a preceding stage becomes an input of a pulse generation circuit of a next stage, wherein discharge between the capacitance and ground is performed. The impedance of the path
A pulse generation circuit, wherein the pulse generation circuit is set to be negligibly small as compared with the impedance of a charging path between the capacitance and a power supply. 5. The charging path is charged by limiting a charging current from the capacitance via a resistance, and the discharging path is parallel to the resistance so that the discharging current flows without passing through the resistance. 5. The pulse generating circuit according to claim 4, wherein a unidirectional element is connected to the pulse generator. 6. The charging path is charged by limiting a charging current from the capacitance via a resistor, and the discharging path is connected to the capacitance so that a discharging current flows without passing through the resistance. A switching element is connected in parallel with the
The pulse generation circuit according to claim 4, wherein: 7. An output of the image sensor is connected to an input of a buffer circuit via a second switch, and an output of the buffer circuit is connected to a positive input of a differential amplifier via a third switch, and also to a first input of the differential amplifier. The first switch is turned on for a predetermined time in synchronization with a rising edge or a falling edge of a strobe input signal, and then turned off, and the second switch is connected to a negative input via a switch. Turns on for a predetermined time in synchronization with the turning off of the first switch, and then turns off. The third switch turns on for a predetermined time in synchronization with turning off of the second switch. An image sensor device controlled to be turned off, wherein opening and closing of the first, second, and third switches are controlled. 7. A circuit for generating a control pulse to be generated.
The output of the first stage is used for controlling the first switch, and the output of the second stage is used for controlling the second switch. An image sensor device, wherein the output of the image sensor is used for controlling the third switch.