JP3122343B2 - C-MOS shift register - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register using complementary MOS transistors (C-MOS). The present invention relates to a C-MOS shift register that allows unit circuits to operate at high speed.

[0002]

2. Description of the Related Art Conventional C-MOS (Complemental Metal
A shift register using Oxide Semiconductor is shown in Fig. 3.
, and its operation will be described based on the signal waveform diagram of FIG. In FIG. 3, SR ₁ and SR ₂ indicate unit circuits (unit registers) in the first and second stages of the shift register, and the unit circuits SR ₁ and SR ₂ . It has the same configuration. Q _P1 -Q _P5 are P-type field effect transistors (hereinafter referred to as FETs), Q _N1 -Q _N5
is an N-type FET. FETs _QP1 , _QP2 , _QN1 , _QN2
are connected in series to form a first inverter, and FETs _QP3 - _QP5 and FETs _QN3 - _QN5 are connected to the first inverter.
constitutes a latch circuit for latching the output level of the inverter. FETs Q _P2 , Q _P4 , Q _N1 and Q _N3 are connected to the clock signal VCLK and the inverted clock signal [VCL].
K] directly controls its conduction.

An input signal V _(STRT) is applied to the gates of inverter-connected FETs Q _P1 and Q _N2 . In this state, when the clock VCLK becomes high level, the FET _QN1 becomes conductive, and the inverted clock VCLK becomes low level, so the FET _QP2 becomes conductive. Therefore, FETQ _P2 and FETQ
A connection point C of _N1 becomes a signal obtained by inverting the input signal V _(STRT) . This signal is further inverted by an inverter consisting of FETs Q _P5 and Q _N5 and applied to the gates of FETs Q _P3 and Q _N4 . In such a state, the clock VCLK falls and becomes low level, the FET Q _P4 becomes conductive,
Since the inverted clock [VCLK] rises to a high level, the FET _QN3 becomes conductive. As a result, the FET
A signal obtained by inverting the input signal V _(STRT) is output from the connection point of Q _P4 and Q _N3 . This output is fed back to the gate of an inverter consisting of FETs Q _P5 and Q _N5 and this signal is latched.

[0004] Next, when the clock VCLK rises again, the output signal of the unit circuit SR ₁ of the first stage is read into the unit circuit SR ₂ of the second stage. The operation at this time is the same as that of the first stage unit circuit SR ₁ . Then, the clock VCLK and the inverted clock ______ [VCL
K], the input signal V _(STRT) is sequentially transferred (shifted) to the next-stage unit circuit.

[0005]

A shift register having such a structure has inverter connection points (floating connection points A and B) whose FETs are rendered non-conductive by a clock.
is in a floating state. Then, there is a problem that the capacitance floating in the floating connection points A and B slows down the transfer speed. Taking the first-stage unit circuit SR ₁ as an example to explain this point, stray capacitances C _S and C _S ' are generated at points A and B, respectively.
When the clock is in the read state, the input signal cannot be read without charging or discharging this stray capacitance. That is, the read signal is delayed during reading.

[0006] This will be further explained with reference to FIG. 4 .
When the input signal V _(STRT) is at a high level and the clock VCLK is at a read state high level, the FETs Q _P2 and Q _N1 become conductive, and the charge accumulated in the stray capacitance C _S during the non-conducting state is transferred to the FETs Q _P2 and Q N1 . Discharge through Q _N1 and Q _N2 . When this discharge ends, the voltage VC at point _C , which is the output terminal, becomes low level. That is, the change in the potential at the point C is delayed by the time Δt due to the discharge time, as indicated by the solid line. Voltage V B at point _B
In the curve of FIG. 4 showing
A portion where the potential is raised by this discharge current is shown. When the input signal is low level and reading this signal,
When the charging of the capacitor C _S ' is completed, the potential at the output terminal point C becomes high level, so the signal change is delayed by the time Δt' required for charging. Due to this delay, there is a problem that the shift register cannot operate at high speed.

[0007]

SUMMARY OF THE INVENTION In order to solve this problem, according to the present invention, a mutual open circuit is provided according to the level of the input signal.
A first C-MOS transistor that is closed and a clock signal
a second C-MOS transistor that is opened and closed by the signal
are connected in series with the input signal at the first level of the clock signal.
composed of an inverter that reads the
and the inverter at the second level of the clock signal.
a latch circuit that holds the output of the data; the inverter;
and a unit circuit configured by the latch circuit is cascaded
connected to sequentially transfer the input signal to the unit circuit of the next stage.
In the shift register, the inverter of the unit circuit is
the first C-MOS transistor constituting the
Stray capacitance generated at the connection point with the C-MOS transistor of 2
A quantity is configured to charge and discharge in accordance with the level of the input signal .

[0008] Therefore, when the level of the input signal changes,
The time required for discharging the floating connection point of the inverter or the time required for charging is shortened, and the shift register can be operated at high speed.

[0009]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention is shown in FIG. 1. FIG. 2 shows clock signals VCLK, [VCLK]
, and the voltages at points _A , _B , and _C in FIG.
shows a timing waveform diagram of In the embodiment of the present invention shown in FIG. 1, a P-type FETQ is added to the conventional circuit shown in FIG.
_P6 and N-type FET _QN6 are added, and the same parts are given the same symbols.

The operation of the circuit shown in FIG. 1 will now be described with reference to timing waveforms shown in FIG. In FIG. 1, the input signal V
After _(STRT) becomes H level, the clock VCLK rises and the inverted clock falls and becomes the first level.
FET Q _N1 and FET Q _P2 become conductive. input signal is high
Since it is level, the FET Q _N2 is conducting, and the voltage V _C at the point C tends to fall to L level. At this time, since the input signal V _(STRT) is at H level, this signal causes the FE
TQ _N6 is conducting and floating connection point A
The stray capacitance C _S at the point is connected to the clock V through this FET Q _N6
Discharge begins before CLK rises. For this reason,
The voltage V _C at point C quickly falls when the clock VCLK rises.

[0011] Next, the clock VCLK is inverted to provide a second
level, FET Q _P2 and FET Q _N1 are non-conducting.
FET Q _{P4 and} FET Q _N3 become conductive, and the output signal at point C, which is the inverted signal of the input signal V _(STRT) , is generated by the FET
Latched by an inverter consisting of Q _P5 and Q _N5 and an inverter consisting of FETs Q _P3 , Q _P4 and Q _N3 , Q _N4 , the output signal Φ ₁ of the unit circuit SR ₁ of the first stage is obtained. stop
Then , this output signal Φ ₁ is shifted to the second stage unit circuit SR ₂ .

When the input signal V _(STRT) falls to L level, the clock VCLK rises to the first
When returning to level 1, FET Q _P2 and FET Q P2
Since Q _N1 is turned on and FET Q _P1 is turned on by the input signal V _(STRT) , the voltage V _C at point C tries to go high. At this time, since the input signal V _(STRT) is L level, F
The ETQ _P6 is conducting, and the stray capacitance C _S ' at the point B, which is the floating connection point, is charged from the power supply via the FET Q _P6 . Therefore, voltage V _{C at point C} is clock VC
When LK rises, it rises quickly. Thereafter, the same operation as in the first shift register is performed in the second shift register.

In this way, the _{stray capacitances} C _S and
Since C _S ' is charged or discharged in advance according to the level of the input signal, the potential at point C of each unit circuit is applied to each unit circuit in synchronization with clock VCLK without delay.
They will be transferred sequentially .

[0014]

INDUSTRIAL APPLICABILITY As described above, the C-MO of the present invention
In the S shift register, since a transistor circuit for charging/discharging is provided at the floating connection point of the C-MOS transistor forming the inverter in each unit circuit, the input signal of each stage of the shift register can be read without delay. This has the effect of enabling the shift register to operate at high speed.

[Brief description of the drawing]

1 is a circuit diagram showing an embodiment of the present invention; FIG.

2 is a diagram showing a time chart of FIG. 1; FIG.

FIG. 3 is a circuit diagram showing a conventional example;

4 is a diagram showing a time chart of FIG. 3; FIG.

[Description of symbols]

QP1 to _{QP6 P} -type FETs QN1 to _{QN6 N -} type FETs SR1, SR2 _Unit circuits at each stage of the shift register

Claims (1)

(57) [Claims] 1. A first power supply line and a second power supply line
a pair of first C-MOS transistors , one end of which is connected to an input signal and which is opened and closed by the level of an input signal; and the first power supply , which is opened and closed by a clock signal.
the other end of the first C-MOS transistor connected to
Said as a first connection point and connected to said second power supply side
the other end of the first C-MOS transistor as a second connection point;
an inverter configured to read an input signal at a first level of a clock signal by means of a second C-MOS transistor connected as an inverter; a latch circuit for inverting and holding an output, wherein a unit circuit configured by the inverter and the latch circuit is cascade-connected to sequentially transfer an input signal to a next-stage unit circuit, the shift register comprising : between the first power supply line and the second connection point and before
connected between the second power supply line and the first connection point
A pair of third C-MOS transistors that are opened and closed to each other
and the third C-MOS transistor is controlled by the input signal.
by driving the first C-MOS transistor
connected to the connection point on the side where the register is open
configured to close the third C-MOS transistor;
A C-MOS register characterized by: