JPH0498693A - Shift register circuit - Google Patents

Abstract

PURPOSE:To shorten time for transfer and to prevent the time from being overlapped between adjacent bit output signals by forming a bit part by a transfer gate, the inverse parallel circuit of an inverter and a clocked inverter, and a NOR circuit, etc. CONSTITUTION:A shift register circuit 1A is composed of first and second bit parts A1 and A2 which are serially connected with similar circuit configuration while inverting the phase of a clock signal. An input signal SIN is inputted through a transfer gate TG of the bit part A1 to the inverse parallel circuit of an inverter INV and a clocked inverter CINV, and a latch signal SL is outputted. While inputting the signals SIN and SL, a NOR circuit NR outputs a bit output signal SO1. A NOR gate NR is provided for an output to an output terminal. Similarly, a shift output SO2 is outputted from the similar second bit part A2 in the next step at high transfer speed in the case of an inverted clock without overlapping bit output signals.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a shift register circuit.

[Conventional technology]

Shift register circuits are often used in video signal sample and hold circuits and the like.

FIG. 5 is a circuit diagram of an example of a conventional shift register circuit.

The shift register circuit IC has bit parts C1 and C with the same configuration.
2 are connected in cascade.

The bit part C1 is connected to one end of the transfer gate TG or the input terminal IN, and the other end is connected to the input terminal of the inverter ■NV and the output terminal of the clock diverter CrNV, and the output terminal of the inverter INV and the clock diverter CIN.
The input terminal of V is connected to the output terminal H1, and the latch part La has the same circuit configuration as this latch part La, and has a synchronization signal φ, T input to the transfer gate TG and the clocked inverter CINV, and which is in opposite phase to each other. Latch sections Lb that receive synchronizing signals 7-7φ are connected in cascade.

Each bit part C1, C2 is a bit output signal S01, SC2
Output.

The bit parts CI and C2 with such a circuit configuration are connected to the node M
A synchronizing signal Φ and an input signal SIN are applied to the shift register circuit IC connected in cascade through the synchronous signal Φ and the input signal SIN at the timing shown in FIG.

First, the operation of the bit section C1 of the shift register circuit IC will be explained.

From time to to tl, TG is off, and the "H" level of input signal SIN is not input to inverter IN■.

From time t1 to t2, TG of latch part La turns on,
The "H" level of the signal SIN is input to the inverter IN■, and the "L" level of the output signal SHI is output to the output terminal H1.

From time t2 to 73, TG of latch La is turned off and inverter CI NV is turned on, so that ``'' of SHI
The L'' level is maintained.

Also, since TG of latch part Lb is turned on, SHl's ゛°
The first bit output signal 5O1="H" is inputted to the L'' level level revenverter INV and outputted to the bit output terminal 0UTI.

From time t3 to t4, TG of latch part La turns on,
5IN="L" is the inverter INV4. of the latch section La.
: Input, and output signal 5H1="H" is output.

Further, TG of the latch portion Lb is turned off and CINV is turned on, so that 501-“H” is held.

From time t4 to time tl, TG of the latch section La is turned off and CINV is turned on, so that 5H1="H" is held.

Also, since the TG of the latch circuit section Lb is turned on, the latch section L
“H” is input to SH in inverter INV of b, and 5O
I-“L'' is output.

In this way, input signal 5IN=“H” from time point 10 to t2
is shifted from time t2 to t4 and output as the output signal S○1-“H” of the bit portion C1.

The bit part C2 of the shift register circuit IC is also the bit part C1.
The bit output signal 5 is output from time t4 to t8.
O2='Output "H".

As described above, the bit portion of the conventional shift register circuit is shifted to the upper bit portion of the data every cycle of the synchronization signal φ.

[Problem to be solved by the invention]

The conventional shift register circuit described above transfers data to the upper bit part in one period of the synchronization signal φ, so 1
The drawback is that it takes one cycle of the synchronizing signal φ to transfer the pulse data.

Also, the bit output signal of the shift register changes from “H” to
Since it takes the time from time t4 to t6 and from t4 to t5 in FIG. 6 to go from "L" and "L" to °゛H'', the bit output signals of adjacent bit sections go "H" at the same time. There was a time (from time t4 to time t5) when the value was intermediate between "L" and "L".

In Fig. 7, F is connected to each bit output terminal of the shift register circuit IC.
A sample and hold circuit is shown in which a video signal input terminal VIN is connected to the gate of an ET switch F, its source is connected to a video signal input terminal VIN, and a hold capacitor C is connected to its drain.

Each bit output signal S01 of shift register circuit IC
The FET switch F is turned on and off by SO2, and the voltage of the video signal SV is held in the hold capacitor C when the FET switch F is on.

Here, the output signals of adjacent bit parts C1 and C2 are SQL,
When SO2 reaches the intermediate value between “H” and “’L” at the same time, 2
The disadvantage is that the video input signal SV is not held correctly in the hold capacitor C because two adjacent FET switches F are both turned on and charge moves between the hold capacitors C connected to the drains of the FET switches. There is.

For example, when a sample-and-hold circuit is realized using a high-voltage CMOS process, the difference between the input voltage of the sample-and-hold circuit and the voltage after sample-and-hold is several tens of mV to several hundred mV.

SUMMARY OF THE INVENTION An object of the present invention is to provide a shift register circuit that has a fast data transfer time and no overlap time between adjacent bit output signals.

[Means to solve the problem]

The shift register circuit of the present invention has a first transfer gate in which an input signal is input to one end of the transfer gate, and the other end is connected to the input end of the inverter of an anti-parallel circuit of an inverter and a clocked inverter to output a latch signal. a latch section; and a NOR gate, one input end of which receives the input signal and the other input end of which receives the start signal and outputs the NOR signal as a bit output signal to a first bit output end. A first bit section, an input terminal inputting the bit output signal, has the same circuit configuration as the first latch section, and a clock signal supplied to the transfer gate and the clocked inverter is connected to the first bit section. a second latch part that corresponds to the latch part and has an opposite phase relationship; and the NO
The bit section includes a NOR gate corresponding to the R gate and a second bit output terminal corresponding to the first bit output terminal.

Further, the shift register circuit of the present invention has a first transfer gate, in which an input signal is input to one end of the transfer gate, and the other end is connected to the input end of the inverter of an anti-parallel circuit of an inverter and a clocked inverter to output a latch signal. a latch section, and a NAND gate having one input terminal receiving the input signal and the other input terminal inputting the latch signal and outputting the NAND signal as a bit output signal to a first bit output terminal. 1 bit section, an input terminal inputs the bit output signal, has the same circuit configuration as the first latch section, and a clock signal supplied to the transfer gate and the clocked inverter corresponds to the first latch section. a second latch section having an opposite phase relationship; and a bit section having a NAND gate corresponding to the NAND gate and a second bit output terminal corresponding to the first bit output terminal. has been done.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

The shift register circuits IA have the same circuit configuration and the clock signals are in opposite phases. The second bit section is composed of the second bit section Al and A2 in series.

In the first bit section A1, the input signal SIN is input to one end of the transfer gate TG, and the other end is input to the inverter IN.
A first latch section L1 is connected to the input terminal of the inverter INV of the anti-parallel circuit of the clocked inverter CINV and outputs the latch signal SL; It has a NOR gate NR which inputs the latch signal S and outputs the NOR signal as the bit output signal S○1 to the first bit output terminal.

The second bit section A2 has the same circuit configuration as the first bit section A1, and the synchronizing signals φ, 7- input to the transfer gate TG and the clocked inverter CINV are opposite to those of the first bit section A1. The phase synchronization signal 7-1φ is input.

A synchronizing signal φ and an input signal SIN are applied to the first and second bit portions AI and A2 of the shift register circuit IA at the timing shown in FIG.

From time to to tl, TG of bit part A1 turns on,
The "H" level of the input signal SIN is input to the bit portion A1, and the "L" level is input to the N○R gate NR via the inverter INV.

5IN−“H” is input to the other input terminal of the NOR gate NR, and the NR bit output signal 501=“L” is output.

At this time, the TG of the second bit portion A2 is off.

From time t1 to t2, TG of bit part A1 is turned off,
Since clocked inverter CINV turns on, IN
The pressure of V is maintained at "L", and "L" is input to NR.

SIN is input to the other input terminal of NR, but 5I
Since N="L II" is not established, the NR output signal S
○1-"L' is output.

At this time, since TG of bit part A2 is turned on, signal 5O1
- "L" is input as "H" to NR via INV.

Since 5O1-"L" is input to the other input terminal of NR, the output signal 5O2="L" of NR is output.

Since the input signal SIN becomes "L'" from time t2 to t3, the two NR input signals SIN and S of bit part A1
Both L become “L”, and the output signal 501 of NR becomes “H”.
” is output.

At this time, since TG of shift register circuit A2 is on, 501="l Hl" is sent to NR via INV at low level.
II is input.

Since SO3-"Ho" is input to the other input of NR, the output signal 5O2-"L" of NR is output.

From time t3 to t4, TG of bit part A1 is turned on,
Input signal 5IN-"L" is inputted to NR via INV.

Therefore, the output signal Sol of NR begins to change from "H" to "L".

At this time, the NR input terminal of the second bit part A2 has the first
Since the bit output signal Sol of NR is input, the NR output signal 5O1="L" is output.

From time t4 to t5, signal S○1 becomes "L", and since TG of bit part A2 is turned on and CINV is turned on, the state "L" at time 3 is maintained, and the input of NR L'' is input to both terminals, and the NR output signal 5
O2="H" is output.

As described above, the input signal SIN is shifted to the upper jit portion in half the cycle of the synchronizing signal φ.

Furthermore, since the output starts after the output signal level of one lower level becomes L'', the outputs of the adjacent bit sections will be output at the same time.
It will never be an intermediate value between Hp and "L'."

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

The difference from the first embodiment in terms of circuit configuration is that the first embodiment uses a NOR gate NR, whereas this embodiment uses a NA
This is because it has been replaced with an ND gate NA.

A synchronizing signal φ and an input signal SIN are applied to a circuit in which bit parts Bl and B2 having such a circuit configuration are connected in series at a timing as shown in FIG.

At time tl from time 10, TG of bit part B1 is turned on, input signal 5IN="L" is input to INV, and NAN
D game) The output "Ho" of INV is input to NA.

Since 5IN-"L" is input to the other input terminal of NA, the output signal 501 of NA="H" is output.

At this time, TG of bit portion B2 is off.

From time t1 to t2, TG of bit part B1 turns off,
Since CINV is turned on, the output of INV is held at "'H", and "H" is input to NA.

SIN is input to the other input terminal of NA, or 5I
Since N is not “H”, the NA output signal 5O1
="°H'' is output.

At this time, since the TG of the second bit portion B2 is turned on, the signal 5O1-'"H" is inputted to NA as "'L" via INV.

Since 5O1="H" is input to the other input terminal of NA, the output signal 5O2="H" of NA is output.

Since the input signal SIN becomes "H" from time t2 to t3, both of the two input signals of NA of bit part B1 become "H", and the NA output signal 501="L"° is output.

At this time, since TG of bit part B2 is on, SO
2-“L” is input to NA via INV.

Since 501-"'L" is input to the other input of NA, the output signal 5O2 of NR="H" is output.

From time t3 to t4, TG of bit part B1 is turned on, and input signal 5IN is set to "H" or L' is applied to NA via INV.
" is input and the other input terminal of NA is 5IN-"H'
” is input.

Therefore, the NA output signal S01 begins to change from "L" to "H".

At this time, the signal Sol is applied to the NA input terminal of bit section B2.
and the output of INV held by CINV ゛H
” is input, the NA output signal S○2=“H” is output.

Since the signal S01 becomes "H" from time t4 to t5, "H" is input to both of the NA input terminals of the bit section B2, and the NA output signal SO2 "L" is output.

As described above, the second embodiment has the same effect as the first embodiment, but both the input signal and the output signal have an opposite phase relationship between the second embodiment and the first embodiment. .

As a result, in the above-mentioned FIG. 7, when the FET switch F is in the N channel (on at "H"), it corresponds to the first embodiment, and when it is in the P channel (on at "L"), it corresponds to the second embodiment. can.

〔Effect of the invention〕

As explained above, since the present invention uses only one latch section in the bit section of the shift register circuit, the output signal of the bit section can be obtained in half the period of the synchronization signal.

Furthermore, by inputting the input and output of the latch section to the logic gate, adjacent outputs do not become intermediate values between "H" and "L" at the same time.

This has the effect that the video input signal can be held correctly when used in the shift register circuit and sample hold circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a first embodiment of the present invention.
Figure 3 is a circuit diagram of the second embodiment; Figure 4 is a timing diagram of signals of each part to explain the operation of the circuit in Figure 3. ,
Fig. 5 is a circuit diagram of an example of a conventional shift register circuit, Fig. 6 is a timing diagram of each part signal to explain the operation of the circuit of Fig. 5, and Fig. 7 is a diagram of each bit output signal of the shift register circuit. FIG. 2 is a circuit diagram of a sample and hold circuit that determines sampling timing. ■A~IB...Shift register circuit, Al, Bl...
- First bit part, A2. B2... second bit part,
Ll, L2... 1st. Second latch section, TG...transfer gate, INV...inverter, CINV
...Clocked inverter, NR...NOR gate, NA...NAND gate, IN, VIN...input terminal, 0UTI to 0UT2...1st. Second bit output terminal, φ, T... synchronization signal, SIN... input signal, Sol~S○2... bit output signal.

Claims (1)

[Claims] 1. (A) An input signal is input to one end of the transfer gate, and the other end is connected to the input end of the inverter of an anti-parallel circuit of an inverter and a clocked inverter to output a latch signal. a first latch section; and a NOR gate having one input terminal receiving the input signal and the other input terminal inputting the latch signal and outputting the NOR signal as a bit output signal to the first bit output terminal. (B) an input terminal inputting the bit output signal;
a second latch section having the same circuit configuration as the latch section and in which a clock signal supplied to the transfer gate and the clocked inverter is in an opposite phase relationship with the first latch section; A shift register circuit comprising: a bit section having a NOR gate corresponding to a NOR gate and a second bit output terminal corresponding to the first bit output terminal. 2. (A) A first latch unit, into which an input signal is input to one end of the transfer gate and whose other end is connected to the input end of the inverter of an anti-parallel circuit of an inverter and a clocked inverter to output a latch signal; , a NAND gate having one input terminal receiving the input signal and the other input terminal inputting the latch signal and outputting the NAND signal as a bit output signal to the first bit output terminal. , (B) an input terminal inputs the bit output signal, and the first
a second latch section which has the same circuit configuration as the latch section and whose clock signal supplied to the transfer gate and clocked inverter is in an opposite phase relationship with the first latch section; A shift register circuit comprising: a bit section having a corresponding NAND gate and a second bit output terminal corresponding to the first bit output terminal.