SU1614117A1 - Device for receiving relative by-pulse signal - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to reduce the time to synchronization and gating error control. The device contains triggers 1, 2 and 3, shaper 4 pulses, band-pass filter 5 with a signal conditioner, frequency divider 6 into two, inverter 7, elements EXCLUSIVE OR 8, 9, and 10 and counting trigger 11. In the device at the output of the element EXCLUSIVE OR 10, a signal is formed consisting of two non-coincident sequences, the symbols of which have a duration of half a clock interval and alternate. The first of them characterizes the information content of the transmitted digital signal (but can be distorted by errors), and the second characterizes the flow of errors that occur in the input relative bi-pulse signal. These sequences arrive at trigger 11, with one error in the bi-pulse input signal corresponding to one transition from low to high (and one transition from high to low) of the output signal of trigger 11. The goal is achieved by ensuring the formation of error signals with the representation of errors as transitions from one particular level to another. 3 il.

Description

ABOUT

 1

The invention relates to telecommunications and can be used in digital transmission systems as receivers of subprimary digital streams.

The purpose of the invention is to reduce the time to synchronization and gating error control.

FIG. 1 shows a structural electrical circuit of the device; in fig. 2 and 3 are time diagrams explaining his work.

The device contains the first 1, second 2 and third 3 triggers, shaper 4 them - i pulses, band-pass filter 5 with a signal shaper, a divider of frequency b by two,; Inverter 7, first 8, second 9 and third 10 I elements EXCLUSIVE OR. countable; trigger 11.

; The device works as follows.

At the input of the device comes relative; bi-pulse signal (Fig. 2,3a), in which at each clock interval there are two pulses of different levels with a significant transition from one level to another in the middle of the clock interval, moreover when transmitting 1 digital signal from -: is stored, and when transmitting O, the sequence of alternation of the levels of I pulses at the next clock interval I compared with the previous one changes. Thus, transitions at the boundaries of the clock intervals occur during transmission 1 and are absent during transmission I of transmission O. Under the influence of noise and distortion during transmission along the line, the signal shape changes and upon reception digital gating errors occur, leading to disturbance of the signal structure. The violation of the structure in the bi-pulse signal is schematically represented in FIG. 2,3a changes in the levels at half the clock interval and are marked with crosses. A level change at half the clock interval corresponds to one gating error.

The input signal in FIG. 2, 3a is fed to the input of the pulse former 4, which converts all transitions from one level to another in this signal to a sequence of pulses (FIG. 2.36). From this sequence, the band-pass filter 5 with the signal conditioner produces first a sinusoidal signal (Fig. 2.3a), and then a pulse signal (Fig. 2.3g) of the doubled clock frequency. With the help of the 6 frequency divider by two, the recovered clock signal is produced according to the Diagram of FIG. 2e either according to the diagram of FIG. 3 and depending on the initial conditions of its operation,

The first trigger 1 with positive fronts of the recovered clock gates the input relative bi-pulse signal, with the result that at its output a signal is formed according to the diagram or Fig. 2e or fig. Ze. At the output of the second flip-flop 2, the same signal appears, but is delayed by one clock interval (diagrams in Fig. 2.3 g, respectively). The output of the first element EXCLUSIVE OR 8, the inputs of which are affected by the output signals of the first 1 and second 2 flip-flops, produces a reconstructed information signal according to the diagram in FIG. 2h or FIG. 3, while the restoration of the information signal does not depend on the initial operating condition of the frequency divider 6 two.

Errors in the received relative bi-pulse signal (marked with crosses in Fig. 2.3a) lead to errors in the duration of the contact interval in the output signals of the first 1 and second 2 triggers and the first element EXCLUSIVE OR 8 (Figs. 2,3, f, g, s ), also marked with crosses. In this case, if the error in the bi-pulse signal is read by the positive edge of the clock signal (Fig. 2.3e) in the first trigger 1 (the first error in the diagrams of Fig. 2 and the second in Fig. 3), then in the reconstructed information signal (Fig. 2, 3z} errors also appear on two adjacent clock intervals.If the error in trigger 1 is not read (the second error in the diagrams of fig.2 and the first in fig.3), then in the information signal (fig. 2.3z) errors since the distortions in the relative biopulse signal occur equally in both the first and the second half of the clock interval (as the first and second errors, respectively, given in the signal (Fig. 2, Pro), then the average number of errors in the received information signal (Fig. 2.3h) is equal to the number of errors in the input signal (Fig. 2, for).

In the third trigger 3, the positive fronts of the clock signal inverted in inverter 7 (Fig. 2.3i) gates the relative bi-pulse signal (Fig. 2.3a) at time points shifted relative to the gates of the first trigger 1 by half of the clock interval. In the output signal of the third - trigger 3 (Fig. 2.3k), there are errors marked by crosses, caused by distortions in the signal (Fig. 2, Pro). The output signals of the first 1 and. The third 3 triggers (Fig. 2.3 e, k) are fed to the inputs of the third element EXCLUSIVE OR 10, which, summing these signals modulo two, in fact

compares in pairs the values of the neighboring halves of the clock intervals in the signal (Fig. 2,3a). As a result of comparison, a signal is formed at the input of the EXCLUSIVE OR element (Fig. 2.3 l), in which when the levels of two adjacent halves of the clock coincide, the spacing of the signal (Fig. 2.3a) is high, and when the discrepancy is low. The signals (Fig. 2l and Fig. 3l) are completely similar and equally phased with respect to the signal (Fig. 2,3a). The structure of the signal (Fig. 2.3 l) uniquely reflects the structure of the bi-pulse signal (Fig. 2, Per).

In the comparison, in the third element, the TURN-OFF OR 10 levels on either side of each border of the clock intervals of the input bi-pulse signal (Fig. 2, Over) in the signal (Fig. 2.3 l) is formed either high or low, depending on whether there was a transition on the border of these two clock intervals or not, which, in turn, depends on the transmitted information. If symbol 1 is transmitted, then a transition at the boundary of clock intervals is present in the relative bi-pulse signal, and a low level will be present in the signal (Fig. 2.3 l) and vice versa. In the next half of the clock interval element, EXCLUSIVE OR 10 compares the values of the two halves within one TaicTOBoro interval of the bi-pulse signal (Fig. 2.3a). If there was no error in the bi-pulse signal, then these two halves have necessarily different levels and in the signal (Fig. 2.3 l) a low level is necessarily formed. If an error occurred in the signal (Fig. 2,3a), then it necessarily leads to disruption of the structure of the relative bi-pulse signal, namely, the absence of a mandatory transition in the middle of the clock interval. This, in turn, causes a violation of the signal structure (Fig. 2.3 l): instead of a mandatory low level, a high level pulse appears in it, which indicates an error in the bi-pulse signal. All changes in the signal structure (Fig. 2.3 l) caused by errors in the bi-pulse signal (Fig. 2, a) are marked with crosses.

Thus, the output signal of the third element EXCLUSIVE OR 10 (Fig. 2.3l) consists of two non-coincident sequences, the symbols of which have a duration of half a clock interval and alternate: the first characterizes the information content of the transmitted digital signal (but can be distorted errors), the second characterizes the flow of errors arising in the relative bi-pulse signal.

The output of the third element EXCLUSIVE OR 10 is applied to the enable input of the counting trigger 11.

The counting trigger of the counting trigger 11 receives a clock signal (Fig. 2, g) through the second element EXCLUSIVE OR 9 (Fig. 2.3 n), and the counting trigger 11 switches at the moment the positive edge arrives at its counting input, if at that time its high-resolution input has a high level pulse in the signal (Fig. 2.3 l).

Normal operating conditions of the device are characterized by the time ratio of the signals (Fig. 2.3n) and (Fig. 2.3 l), at which a positive edge in the signal (Fig. 2.3 n) appears at the time when the signal (Fig. 2,3 l) there is a symbol characterizing the flow of errors, and not at those moments that correspond to the information symbols in the signal (Fig. 2,3 l). At the established phase of the clock signal shown in the diagram (Fig. 2e), this condition is fulfilled when the output of the counting trigger 11 has a low level (Fig. 2m) and the clock signal (Fig. 2e) passes to its counting input through the second the EXCLUSIVE or 9 element without inversion (Fig. 2n). On the positive fronts of the signal (Fig. 2n), the counting trigger 11 usually does not switch, because in healthy lines, high-level pulses in the signal (Fig. 2n), which characterize errors, appear relatively rarely.

If at the start of operation of the device at a steady-state clock signal according to the diagram (Fig. 2e), a high level appeared at the output of the counting trigger 11, then the signal (Fig. 2e) is inverted in the second element EXCLUSIVE OR 9 and one of the positive edges of the signal (Fig. 2n ) at the counting input of the counting trigger 11 coincides with the first high level pulse from the information sequence in the signal (Fig. 2n) (when the first character O of the transmitted information arrives). After that, at the end of the counting trigger 11, a low level will be set according to the diagram (Fig. 2m).

The device can get out of the normal mode only when a high level pulses appear in the signal (Fig. 2n), characterizing the presence of errors, since these pulses coincide with the positive edges in the signal (Fig. 2n) at the counting input of the counting trigger 11, which leads to switch it. After switching at its output, a high level appears, and the signal (Fig. 2n) at its counting input is inverted. TaKoi; the signal (Fig. 2n) switches the counting trigger 11 when the first high level pulse is received from the information sequence in the signal (Fig. 2n) to the initial state. At the same time, the output of the counting trigger 11 is again set to a low level (Fig. 2m), thereby eliminating the inverse of the clock signal in the second element EXCLUSIVE OR 9 (Fig. 2n). The counting trigger 11 is prepared for the perception of the next pulse from the sequence characterizing the error stream in the signal (Fig. 2L).

The error in the relative bi-pulse signal causes the appearance of one high-level pulse in the output signal of the counting trigger 11 (Fig. 2m). The duration of this pulse may vary depending on the time of the appearance of the Symbol O in a bi-pulse signal (Fig. 2a) after an error in it.

On the time diagrams (FIG. 3), on the contrary, normal working conditions are provided by having a high level at the output of the counting trigger 11 (FIG. 3m) and inverting the clock signal (FIG. RE) as it passes through the second element EXCLUSIVE OR 9 (FIG. Zn). The operation of the device in this version of the phasing is similar to that considered according to the diagrams (Fig. 2). However, at the output of the counting trigger 11, an error in the bi-pulse signal causes the appearance of one low-level pulse (Fig. 3m), and not a high one, as in the signal (Fig. 2m). The duration of this pulse is also different for the same reasons.

 Common to the output signal of the counting trigger 11 in the two considered variants (diagrams of Fig. 2m and 3m) is that in it one error in the input bi-pulse signal (Fig. 2,3a) corresponds to one transition from low to high (and one transition from high to low). Therefore, the output signal of the counting trigger 11 is an error signal with an error representation in the form of transitions

from one particular level to another. Representation of errors in the form of transitions is acceptable in many cases, since error counters processing the signal

errors in error rate meters, have a counting input and are triggered by a signal edge. If necessary, transitions in the error signal can be converted to impulses by known devices.

required duration.

Claims (1)

 Invention Formula A device for receiving a relative bi-pulse signal containing a pulse generator, the input of which is connected to the first input of the first trigger and is an input of the device, the output of the second trigger is connected to the first input of the first element EXCLUSIVE OR, the output of which is 20 information output of the device pulse driver output through a series-connected band-pass filter with a signal shaper and a frequency divider into two connected to the second input 25 of the first trigger and the first input of the second element and EXCLUSIVE OR, the second input of which is connected to the output of the counting trigger, the third trigger, the output of the first trigger is connected to the first input of the third 30 EXCLUSIVE OR element, characterized in that, in order to reduce the synchronization time and control of gating errors, an inverter is introduced the output of the frequency divider by two 5 is connected via an inverter to the first input of the third flip-flop, the second input of which is the device input, and the output is connected to the second input of the third element EXCLUSIVE OR, the output of which is connected 0 with the first input of the counting trigger, the second input of which is connected to the output of the second element EXCLUSIVE OR, and the output is the error output of the device, the output of the first trigger is connected to the second input 5 of the first element and the second input of the second trigger, the second input of which is connected to the output of the frequency divider two, which is the clock output of the device.  «« Jo «b Yom IV) c se