SU1608785A1 - Digital matched filter - Google Patents

Abstract

The invention relates to radio engineering and can be used to process noise-like phase-shift keyed signals. The purpose of the invention is to improve noise immunity. For this, a digitally matched filter containing a low-pass filter 1, a first adder 2, a 3-clock pulse generator, a delay element 6, a quantizer 9, a shift register 17 and a weight adder 18, the first and second elements OR 8 and 16, the first and second samplers 4 and 5, the second adder 7, the first and second groups of elements AND 10 and 15 and the group of delay elements 12 and OR 14, and the quantizer 9 is made multi-level. Processing the output normalized pulses of a multi-level quantizer 9 using elements 10, 12, 14, and 15 provides an adaptive bias of the binary quantization threshold during the time of action of the signal element in accordance with the estimated level of powerful structural interference. As a result of this bias, equivalent to reducing the amplitude of the interference at the input of the multi-level quantizer 9 by N times, where 2N is the number of quantization intervals, the noise immunity of the processing increases. 2 Il.

Description

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The invention relates to radio engineering can be used for the matched filtering of noise-like phase-manipulated signals.

The purpose of the invention is to increase the resilience.

Fig. 1 is an electrical block diagram of a digital matched filter; FIG. 2 shows timing diagrams that are taken by Io.

Digital matched filter contains low-pass filter 1, first adder 2, 3 clock pulse generator, first 4 and second 5 samplers, delay element 6, second adder 7, first element OR 8, multilevel quantizer 9, elements 10 of the first stage, input 11 , elements 12 of the delay group, output 13, elements OR 14 groups, elements 15 of the second group, the second element OR 16, shift register 17 and weight adder 18.

Digital matched filter works as follows.

An additive signal and noise mix, the input range of which is kept constant. Due to the automatic gain control, is fed to the input of the second sampler 5 and through the adder 2 ,. where a random-offset voltage is added to it from the output of low-pass filter 1. To the input of the first sampler 4. In the second sampler 5, samples are taken from the input action at discrete times tj, the interval between which is equal to the duration Te of the complex signal element and set by the generator 3 clock pulses. In the first discretizer 4, samples are taken at times tj + Tz, shifted relative to the pulses of the clock sequence by an amount of delay Gz, which is selected from the conditions Gz "Te: And Tz" Tcorrp; where Tcorrp is the interference correlation interval. The sequences of samples {Sj} i and (Sj} 2 from the outputs of the first 4 and second 5 samplers, respectively, through the adder 7 arrive at the input of the multilevel quantizer 9, which performs their level quantization at the times tj and tj-i-Tz, given by the output control pulses of the first element OR 8.

The signal (Fig. 2a) at the output of adder 7 performs the functions of combining sequences of samples {Sj} i and {Sj} 2 from the outputs of the first 4 and second 5 samplers and linear amplification to match the values of their amplitudes with the dynamic range of the multilevel quantizer 9.

The interference (signal) takes the values + Sn / + Sc and -Sn / -Sc. the corresponding 1 and O code interference (signal).

The sequence of samples Si2, 822.

S32i ... is a short pulse; The amplitudes are equal to the instantaneous values of the signal mixture and the powerful interference at the moments ti, t2, t3 .... and the sequence of samples Sii. S2i, 5з1 -; a set of pulses with amplitudes equal to the instantaneous values of the signal mixture, noise, and random bias voltage, intended to linearize the multi-level quantizer 9, at times ti + Gz; t2 +

5 + Тз; xs + ts ....

FIG. 2a, the quantization intervals of a multilevel quantizer 9 are indicated by dashed lines and are numbered in accordance with the numbers of its outputs.

0 1,2,32N.

At the moments of arrival of the control pulses (Fig. 2b) at the clock input of the multi-level quantizer 9 on N-2, N-1, N + 2, N + 3, N + 4 at the outputs connected to

5 inputs M-3, Lt2, N + 1, N + 2, N + 3 elements And 10, respectively, normalized pulses appear (Fig. 2c-i). Consistently connected 1st element AND 10, delay element 12, (i-l) -e element OR

0 14 and element 15 represent the 1st selection channel.

To clarify the operation of the selection channels, we consider one of them, for example (L-3) -th channel, at the input of which sequences are received (sflV and (ff (Fig. 2b). Through the element And 10 of this channel, the input of the delay element 12 is received only pulses {sfjz at time points t2, t4, te. These pulses are delayed by time Gz, through the OR 14 element arrive at the input of the AND element 15 of this channel and the second input of the OR element. 14 (N-2) -ro channel , providing passage to the inputs of which the element OR 16

fcplN - 3 „pulses of sequence j bffi

time points: 2 + Гз and t4 + Гз as well as the pulse of the sequence {Sfji. in mo5Q menttb + Tz.

Considering in a similar way the work of other selection channels shows that the pulse at the output of one of the elements of AND 15 appears in

55, the sample value Sji at the input of the multi-level quantizer 9 at the time tj + Gz falls into a higher or the same quantization interval in which the sample value Sj2 is found at time tj, i.e. at Sn Sc at each time point with an accuracy of D V

them: by the level of the quantization interval that the sampling value Sj2 falls into, the interference level is estimated, and it is used as a threshold for binary quantization of the signal from the mixture of signal, interference and linearizing bias voltage Sji. If the value of Sji exceeds the threshold value, then the output of the second element OR 16 is an impulse corresponding to logical 1. otherwise, the impulse is o / t, which corresponds to logical O

Output normalized pulses of the second element OR 16, taking the value O or 1, are successively written to the shift register 17 and compared with the code symbols of the expected signal in the weight adder 18, which forms the output signal. When / 1. where is the signal, the values of the output signal of the sixth adder 18 at each time point of sampling do not depend on the value of the signal mixture and noise at the input of the 11-th matched filter to the same sources and are distributed according to the normal law. Therefore, after smoothing the outputs of the signal by the filter 1, it uses the DL5 to form a random displacement voltage. In this case, the transmission coefficient of the filter 1 is chosen such that the intensity of the random displacement voltage ensures the effective linearization of the binary quantizer under the action of a mixture with amplitude.

Thus, in the proposed digital matched filter, the expression for the signal-to-noise ratio is (NSc / Snf. Where Sc and Sn is the signal amplitude and interference, which, in comparison with lime, provides energy gains by 201d M.dB.

Claims (1)

The invention is a digital matched filter that contains a clock, a delay element, kva, an output device and a follower. the shift register, a weight adder, the output of which is the output of a digital matched filter, a low pass filter and the first adder, the second input of which is an input of a digital matched filter, characterized in that, in order to improve the noise immunity, serially connected the first sampler, the input of which is connected to the output of the first adder, and the second adder, the output of which is connected to the input of a quantizer that is multilevel, and also the second sampling rate op, the input and output of which is connected to the second inputs of the first and second adders, respectively, the first OR element, the first input of which is connected to the clock input of the first discretization unit and the output of the delay element whose input is connected to the output of the clock generator, the clock input of the second sampler and the second input of the first element OR, the output of which is connected to the clock input of the multilevel quantizer, the second element OR, the output of which is connected to the input of the shift register, the first and second groups of elements AND, g upp delay elements and a group of OR elements, with the 1st output of a multilevel quantizer, where, 2N, N 2, is connected via a serially connected 1st element AND of the first group, a delay element of the group and (1-1) -e element of the OR group and element AND of the second group with (i-1) -M input of the second element OR. the output (1-1} of the element OR of the group is connected to the second input of the 1st element OR of the group, the second input (i-1) -ro of the element AND the second group is connected to the 1st output of the multi-level quantizer, the first output of which is connected through in series the connected first element of the first group and the delay element of the group with the second input of the first element OR of the group, and the second inputs of all elements of the first group are connected to the output of the clock generator.