SU1575322A1 - Discrete signal demodulator - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is to increase the reliability of reception of signals in frequency-limited channels with intersymbol interference and a high level of additive interference. The discrete signal demodulator contains filter 1, counters 2 and 3, sampler 5, programmable memory 6, discrete-analog delay line 8, switch 9, DAC 10, divider 11, accumulator-accumulator 12, divider 13 with variable coefficient. division, synchronization unit 15, decision unit 17. The goal is achieved by introducing detector 4, ADC 7, divider 14 with a variable coefficient. dividing line and adjustable delay line 16, with the help of which the problem of adaptive variation of the analysis interval and the decision point of the decision block in solving block 17 is solved depending on the signal-to-noise ratio at the input of the demodulator. 1 il.

Description

The invention relates to a communication technique and can be used for coherent processing of binary discrete signals.

The purpose of the invention is to increase the reliability of signal reception in frequency-limited channels with intersymbol interference and a high level of additive interference.

The drawing shows a structural electrical circuit of the proposed demodulator.

The demodulator contains filter 1, first and second counters 2 and 3, detector 4, sampler 5, programmable memory 6, analog-to-digital converter 7, discrete-analog delay line (DALS) 8, switch 9, digital-to-analog converter (D / A converter). ) 10, the first divider 11, the accumulator-accumulator 12, the second divider 13, the divider 14 with a variable division factor, the synchronization unit 15, the adjustable delay line 16 and the decisive unit 17

The demodulator works as follows.

The additive mixture x (t) of the useful signal and noise is fed to the input of filter 1, whose passband is determined from the condition UFb2 / AtMakc, rfleAt dKc is the maximum value of the discretization interval, equal to AtMBV, c TaMqlcc / N (TQ max max value analysis interval; N is the number of sample values from the input process

on the time interval

Oh t

ai ak

d

From the output of discretization 5, a sequence of sample values x (kAt) (, 2 ...) from the process x (t) is fed to the input of DALZ 8, which has N taps. The delay time between two adjacent DALS taps is equal to the sampling interval ftt Ta / N and is determined by the pulse frequency from the output of divider 11. During the time At, the discrete convolution of sample values from x (t) stored in DALS 8 is performed with sample values by the impulse response of the matched filter, recorded as code words in the programmable memory 6. In this case, the signal Se (t) corresponds to the impulse response containing N sample values from Se (t). To obtain on the time interval

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At discrete convolution values of N sample values x (t) with N sample values of the impulse response to N taps DALZ 8 through the switch 9 connects the input of the reference voltage of the DAC 10, at the same time on the digital inputs of which are 1-bit code words, digital equivalents of the sample impulse response values. At the output of accumulator 12 after adding 10 values of x (kit) weighted by means of a DAC, each discrete convolution value is formed at each time interval it. The decision in favor of one or another symbol de is taken in decision block 17 on the basis of a comparison of the values of the voltages at the output of the accumulator 12 at the time points (k 1, 2, ...) with a zero level. Let us consider in more detail the procedure of adaptive variation of the analysis interval and the decision time shift depending on the signal-to-noise ratio at the input of the discrete signal demodulator. A change in the magnitude of this ratio is usually associated only with a change in the power of the incoming useful signal at a constant (measured in advance) level of additive channel interference. In order to estimate the average power level of the incoming useful signal, detector 4 with a large value of the constant detection time is used. Under this condition, the voltage at the output of the detector 4 varies in proportion to the change in the average power of the incoming signal sequence. Using an analog-to-digital converter 7, this voltage is converted into a digital code, which serves to control the operation (changing the division factors) of the dividers 13 and 14 with a variable division factor. With the help of these dividers, the sampling frequency and the frequency of rewriting the sampled values from x (t) to DALS 8 are changed. As a result, the time interval for analyzing the input process is changed while maintaining a constant number of sampling values on this interval equal to N. Certain level values At the output of detector 4, their optimal values for the analysis interval Td correspond. Synchronously with changing frequency

A change occurs in the frequency of connecting the DALZ 8 taps using a switch 9 to the input voltage of the DAC 10. All possible forms of impulse responses of the discrete-analog matched filter corresponding to certain values of the analysis intervals Ta are written as 1-bit code words in a programmable storage device 6, each response form being represented by N number values. The choice of one or another form of impulse response from the memory of the programmable memory 6 is carried out with the help of the n-bit code supplied to the third inputs of the programmable memory 6. Each n-bit number has its own memory area of the programmable memory 6, where the impulse response values are recorded for a given analysis interval Ta. From the outputs of the programmable memory 6, the 1-bit numbers are fed to the digital inputs of the DAC 10, the output of which provides the values of the results of synchronous multiplication of the sample values x (t) from the outputs of DALS and the sample values of the pulse response stored in the programmable memory 6. With using accumulator 12, N values of the results of multiplying the indicated stresses are summed, and the output of accumulator 12 forms the value of the discrete convolution of the input process x (t) with the corresponding m impulse response over the interval TQ analysis. Such a formation of discrete convolution values takes place at each time interval & t. In accordance with the operation algorithm, decision block 17 analyzes the polarity of this voltage at the time t0 + Ta. The offset of the analysis interval is carried out using an adjustable delay line 16. The change in the delay time of the pulse sequence from the third output of the synchronization unit 15 is performed using an n-bit code from the outputs of the analog-digital converter 7. The adjustable delay line 16 can be performed, for example, based on the analog line, to taps which

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the keys are controlled by the decoders.

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Claims (1)

Invention Formula A discrete signal demodulator containing a series-connected filter whose input is the demodulator input, a sampler and a discrete-analog delay line, the control inputs of which are connected to the output of the first divider, the first and second counters, and the input of the second counter is connected to the input of the first divider , switch, second divider, programmable memory, decision unit, synchronization unit, serially connected digital-to-analogue converter and accumulator, and N first x switch inputs are connected to discrete-analog delay line outputs, p second inputs are connected to p outputs of the second counter, and output is connected to an input voltage reference of a D / A converter, 1 inputs of which are connected to 1 outputs of a programmable storage device, the first p inputs of which are connected to p the outputs of the second counter, and the second m inputs are connected to the m outputs of the first counter, the first output of the synchronization unit is connected to the corresponding input of the second divider, characterized in that To increase the reliability of receiving signals in frequency-limited channels with intersymbol interference and a high level of additive interference, the second divider is made with a variable division factor and serially connected detector and analog-to-digital converter, a divider with a variable division factor, adjustable delay line, the output of which is connected are introduced to the control input of the decision block, the first input to the second output of the synchronization unit, and n the second inputs to the n outputs of the analog-to-digital converter bodies which are also connected to inputs of the third n programmable memory device to the n inputs and the second divider and divider with a variable division factor, and the corresponding input of the divider with a variable division ratio connected to the third output of the synchronization unit, 0 five 0 five 0 five 715753228 and the output of the second divider is connected to the chick and to the control input of the adder — the input of the first divider; output divides the accumulator, the output of which is connected to l with a variable coefficient de input of the decision unit, output; The flippers are connected to the input of the first account connected to the detector input.