SU758028A1 - Radio pulse processing device - Google Patents

Description

The invention relates to radio engineering and can be used in detection equipment against the background of broadband interference — a radio pulse signal of unknown duration, consisting of a sum of simple interfering radio pulses of known frequency, i.e. signal with an unknown form of quadrature components complex-. envelope. ^υ

A device for processing a radio pulse signal containing two identical circuits from a series-connected phase-sensitive detector, a low-pass filter, an analog-digital converter and a shift register, a two-phase reference voltage generator, the outputs of which are connected to the reference inputs of phase-sensitive detectors, whose inputs are combined, a clock pulse generator, the output of which is connected to the clock inputs of analogue-25 digital converters and shift registers, two identical circuits from the follower included on the weighing unit, the adder and the squarer, inputs identical weighing units

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combined, and the outputs of the squares are connected to a common adder £ ΐ].

However, such a device for processing a radio pulse signal has low noise immunity when processing a signal of unknown duration, consisting of a sum of simple interfering radio pulses of a known frequency.

The purpose of the invention is to improve the noise immunity in signal processing of unknown duration, consisting of the sum of simple interfering radio pulses of known frequency.

This is achieved by the fact that a radio pulse signal processing device containing two identical circuits from a series-connected phase-sensitive detector, a low-pass filter, an analog-to-digital converter and a shift register, a two-phase reference voltage generator, whose outputs are connected to the reference inputs of the phase-sensitive detectors, whose inputs combined, the clock pulse generator, the output of which is connected to the clock inputs of analog-to-pFovoy3

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formers and shift registers

'dbe identical circuits with successively connected weighing units, adder and quad, identical inputs of weighing units are combined, and outputs of quadors are connected to a common adder, two identical circuits of a series-connected switch and a storage register are entered, two identical chains of a series-connected additional weighing unit, adder and quadrator, additional shift register, frequency divider, multichannel integrator, each channel of which consists of series-connected blocks weighing, the adder, the number of inputs of which increases from channel to channel, square root extractor and output adder, the source of reference signals, the outputs of which are connected to the second inputs of output adders, and the block of selection of the maximum signal, the outputs of the shift registers are connected to the inputs of switches, and the outputs of the storage registers are connected to the corresponding inputs of the respective weighing units, the outputs of the additional quadrants are connected to the inputs of the common adder, the output of which is connected to the input of the additional the shift register, the clock input of which is connected to the clock inputs of the switches and the output of the frequency divider, the input of which is connected to the output of the clock generator, the outputs of the additional shift register are connected to the corresponding inputs of the multichannel integrator weighing blocks, the output adders of which are connected to the inputs of the maximum signal selection block .

The drawing shows the functional electrical circuit of the device.

The device for processing a radio pulse signal contains two identical circuits from a series-connected phase-sensitive detector 1, a low-pass filter 2, an analog-digital converter 3 and a shift register 4, a two-phase reference voltage generator 5, a clock pulse generator 6, two identical circuits from the series-connected weighing unit 7, adder 8 and quad 9, a common adder 10, two identical circuits from a series-connected switch 11 and a storage register 12, two identical circuits from a series including The additional weighting units 13, the adder 14 and the quad 15, the additional shift register 16, the frequency delimiter 17, the multichannel integrator 18, each channel of which consists of the weighing unit 19,

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an adder 20, a square root extraction unit 21 and an output adder 22, a reference signal source 23 and a maximum signal selection unit 24.

The device works as follows.

The input signal using phase-sensitive detectors 1 and low-pass filters 2 is converted into quadrature components of the complex envelope, which are converted into digital signals using analog-digital converters 3 and fed to the information input of shift registers 4. The signals from the offsets of the shift registers 4 using the switches 11 are periodically transmitted to the storage registers 12 with a period of time during which the information in the shift registers 4 is completely updated. To implement this condition on the control input of the switches 11 are received by him-; pulses from the output of the frequency divider, the period of which is T = Hz / P _t , where Hz and P _t are the digit capacity of 4 shift registers and clock frequency, respectively. The time period is chosen so that the quadrature components of the complex envelope of the useful signal would change their sign during this time interval no more than once.

The output signals of storage registers 12 ~ by means of weighing units 7 and 13 are multiplied by the corresponding coefficients a · and b ^, and the coefficients are the discrete models of the reference voltage envelope and the function associated with it according to Hilbert. The output signals are summed with the help of the sonars 8 and 14. The output signals of the adders 8 and 14 are then squared and summed with the help of quadrs 9 and 15 and the total adder 10, respectively.

The output signal of the common adder 10 is fed to the information input of the additional register 16 shift.

• At its clock input, there are pulses from the output of frequency divider 17, having a period t.

Bit size η additional register 16 shift is determined by the maximum expected duration of the useful signal

n- (en1deg -D ^ ~ -) + 1,

where the symbol βηιίεΓ means the operation of determining the integer part of a number, in our case, the ratio of two quantities.

Additional output signals

register 16 shift come on

inputs of parallel-connected blocks g

19 weighings, the number of inputs of which

five

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increases from channel to channel. Adders 20 are connected in series with weighing units. Connecting weighing units 19 and adders 20 with the number of inputs increasing from channel to channel provides integration of signals that are

„Results of preliminary processing, for various time intervals; moreover, this integration is carried out with certain weights that are selected on the basis of the conditions for ensuring optimality of the device. The number of channels in the multichannel integrator 18 is selected based on the allowable amount of equipment.

The output signals of the adders 20 are normalized by the expectation and dispersion of the noise component, and the value of the expectation in all channels is fixed at zero. Normalization of dispersion is performed in blocks 21 for extracting the square root of the output signal of adders 20, normalizing the expectation using the output adders 22. To normalize dispersion, it is sufficient to perform an operation of extracting the square root, and this normalization will be performed automatically for any number of terms.

The output adders 22 and the source 23 of the reference signals provide the subtraction from the output signals of constant values equal to the corresponding mathematical expectations, which are determined by the expression

1) ₀ ; 7puO, 5 & - 0.5 * 6,

where? £ - the number of inputs of the corresponding block 19 weighing and adder 20.

The signals from the outputs of the output adders 22, the noise components of which have zero mathematical expectations and equal variances, arrive at the input of the maximum signal selection unit 24, which automatically selects the channel of the integrator in which the integration time most closely corresponds to the unknown duration of the input useful signal, which due to the highest signal-to-noise ratio in this channel with equal expectations and noise variances in all channels.

Thus, the use of the proposed device pulse processing signal provides in comparison with the known mouth-_

higher noise immunity when receiving, against the background of broadband interference, a signal of unknown duration consisting of the sum of simple interfering radio pulses of known frequency, i.e. signal with an unknown form of quadrature components of the complex envelope. This effect is achieved by the most complete extraction of the energy of the useful signal from its mixture with noise, with minimal noise accumulation, which leads to an increase in the signal-to-noise ratio after processing compared to existing devices.

Claims (1)

Claim A device for processing a radio pulse signal containing two identical circuits from a series-connected phase-sensitive detector, a low-pass filter, an analog-to-digital converter and a shift register, a two-phase reference voltage generator, the outputs of which are connected to the reference inputs of phase-sensitive detectors whose inputs are combined, a generator of clock pulses whose output connected to the clock inputs of analogue-digital converters and shift registers, two identical circuits are connected in series weighing unit, adder and quad, identical inputs of weighing units are combined, and quad outputs are connected to a common adder, characterized in that, in order to improve noise immunity when processing a signal of unknown duration consisting of a sum of simple interfering radio pulses of known frequency, two identical chains from sequentially switched on switch and storage register, two identical chains from series-connected additional weighing units, adder and quad, additional Additional shift register, divisor often. multichannel integrator, each channel of which consists of serially connected weighing unit, adder, the number of inputs of which increases from channel to channel, unit of square root extraction and output adder, reference source, outputs of which are connected to the second inputs of the output adders, and the maximum signal selection unit, with the output of the shift registers connected to the inputs of the switches, and the outputs of the storage registers connected to the corresponding inputs of the corresponding veve7 block 758028 eight ' connected to the corresponding inputs multichannel weighing units integrator, the output adders of which are connected to the inputs of the block select the maximum signal.