SU1598175A2 - Variable frequency divider - Google Patents

Abstract

The invention relates to a pulse technique and can be used in software-controlled devices for generating, issuing and processing information for dividing the pulse frequency with simultaneous frequency modulation of the output signal. The purpose of the invention, the extension of the frequency range of the output signal, is achieved by reducing the value of its lower limit for a given value of the division factor. The device contains a key 1 with a control signal storage, an OR-NOT 2 element, a pulse counter 3, a code comparison element 5, a modulation code entry bus 6, an input bus 7, a modulation code bus 8, a division ratio control bus 10. Introduction to the device of the inverter 4 and tire 9 of the sign of the modulation code, as well as an increase in the counter size of the pulse counter 3 per unit and the formation of a new set of inter-element links, allows to achieve the purpose of the invention. 1 il.

Description

The invention relates to a pulse technique and can be used in software-controlled devices for generating, issuing and processing information for dividing the pulse frequency with simultaneous frequency modulation of the output signal and is an improvement of the invention according to aath.cv. N ° 1517131.

The aim of the invention is to expand the frequency range of the output signal by reducing the value of its lower limit for a given value of the division factor.

The drawing shows an electric structured circuit of a controlled frequency divider.

The controlled frequency divider (UDCH) contains a key 1 with a control signal memorization, an OR-NOT 2 element, (n + 1) -disable counter of 3 pulses, an inverter 4, a code comparison element 5, a modulation code write bus 6, the input bus 7, the modulation code bus 8, the modulation symbol bus 9, the division ratio control bus 10 and the output bus 11. The information input and the control input of the key 1 are connected respectively to the bus 7 and the first output Equal to the code comparison element 5, the first the output is connected to the counting input of the counter 3 pulses, the information input is high the bit of which is connected to bus 9, the information inputs of the remaining bits are connected to bus 8, the older bit output is connected via inverter 4 to the enable input of the code comparison element 5, the write input is connected to the output of the IL AND –NE element 2, the first the input of which is connected to the bus 6, the second input with the second output of the key 1 and the bus 11. the third input with the second output More than 5 comparison code, the first and second groups of inputs of which are connected respectively with the remaining 4 outputs of the counter 3 pulses and tires ten.

The frequency divider works as follows.

The proposed UDCH makes it possible to divide the frequency of the input pulse signal with the possibility of simultaneous frequency modulation of the output pulse signal under the action of an external modulating effect. 5 The magnitude M of the modulating effect is specified in the UDCH by an additional binary code on buses 8 and 9, and the value K of the division factor is specified by the direct binary code on tires 10 and has a total

In the case of a bit, the p. Total expression for determining the value of the real division factor Kg of the UDCH when operating in a particular mode of operation is defined as follows:

K + 1 st, dL

Pn (3)

Odl MK

Substituting in (a) the boundary values from the region of determining the number M, we have expressions for determining the maximum Kg max and the minimum Kg min of the values of the real UDF dividing ratio for a given value of the number K:

Kg max K + 1 + 2, (b)

Kg min 1. (C)

The expression for determining the frequency of the output frequency-modulated UDCH signal is:

R - I FBX

out (g)

where FBX is the frequency of the input pulse signal fed to the bus 7.

When M O, we obtain from (d) an expression for determining the value of the carrier frequency:

with Rnesr.

Taking into account (b) and (c), we obtain from (d) the expression for the lower FH and upper FB boundaries of the frequency range of the output frequency-modulated UDCH signal for a given value of the K value when the M number varies from minimum to maximum: Fex

Fh

-2

K + 1 FB FBX.

After supplying voltage to the bus 7, the level O must be set, the code of the number M is installed on the tires 8 and 9, and the code of the number K on buses 10. To set the UHF to the initial state, a positive impulse must be fed to the bus 6. Under the action of this pulse, the code of the number M from the tires 8 and 9 is loaded into the counter 3. In the initial state, on the buses 6.7 and 11 there are levels O, on the tires 8 and 9 the code of the number M is set, on the tires 10 the code of the number K is set counter 3 contains the code of the number M.

Consider the operation of the UDCH with a certain constant value of the number K on tires 10 and different values of the number M on tires 8 and 9. Herewith, we assume that

Let tires 8 and 9 be set to a number. After setting the UDCH and the initial state in the counter 3 there is a code of the number zero. Since the code of the number stored in the counter 3 is less than the code of the number specified on buses 10, and level 1 operates at the output of inverter 4, element 5 is allowed to work and there are levels O at its two outputs. At the same time, at the control input of key 1 and At the input of the record of counter 3, there are levels O and H, respectively. After applying clock pulses to bus 7, the first two of them pass to the first output of key 1 and increase the number in counter 3 to two. As a result, the first output of element 5 and the control input of key 1 is set to level 1. The third clock pulse passes from bus 7 to the second output of key 1 and goes to bus 11 and through the element OR NOT 2 to the record input of counter 3. In this case On bus 11, an output pulse is generated, the code of the number specified on buses 8 and 9 is loaded into counter 3, and the UDCH returns to its original state. It should be noted that due to the properties of key 1, the duration of the output pulse of the UDCH is equal to the duration of the corresponding input pulse. If the clock pulses continue to flow to bus 7, then the UDF further operates in a similar way.

Thus, if a number code is set on tires 8 and 9, then in this case the UDF division factor for any value of K number on tires 10 that lies in the M K range is defined as) (in the described case).

Let the number code be set on tires 8 and 9. After setting the UDCH to its initial state, in the counter 3 there is a code of the number one. Since the code of the number stored in the counter 3 is less than the code of the number specified on buses 10, and level 1 operates at the output of inverter 4, both outputs of element 5 have levels O. At the control input of key 1 and at the input of the counter 3 there are respectively O and G levels. After applying the clock frequency pulses to the bus 7, the first of them passes to the first output of the key 1 and increases the number in the counter 3 to two. As a result, level 1 is set at the first output of element 5 and at the control input of key 1, and level O is maintained at the second output of element 5. The second clock pulse passes from bus 7 to second output of key 1 and goes further to bus 11 and through the OR-NOT 2 element at the input of the record of the counter 3. At the same time, an output pulse with the duration of the corresponding bus pulse 7 is formed on bus 11, the number code is loaded into counter 3, and the UHF returns to its initial state. If the clock pulses continue to flow 5 to the bus 7, then the further UDF operation is carried out similarly to that described.

Thus, if a number code is set on tires 8 and 9, then in this case the division ratio of the UDCH for any value of the number K on tires 10 lying in the range is defined as (in the described example).

Let the code number 15 be set on tires 8 and 9. After setting the UDCH to its original state, in the counter 3 there is a code of the number two. Since the number code stored in the counter 3 is equal to the number code specified on buses 10, and level 1 operates at the output of inverter A, the first and second outputs of element 5 have levels 1 and 0, respectively, as a result of which control key 1 and at the input of the record of counter 3, levels 1 operate. After 25 pulses of the clock frequency are sent to bus 7, each of them passes to the second output of key 1, confirms the initial state of counter 3 through the OR-NOT 2 element and is formed on bus 11. 30Thus, if on tires 8 .and 9

If the code of the number M 2 is given, then the division ratio of the UDCH in this case for any value of the number K on buses 10 lying in the range M K is defined as 35 Kd. (K - 1) (in this example, Kg 1).

Let the code of the number M be set on buses 8 and 9. After setting the UDCH to its initial state, counter 3 contains the code of M. Because the code of the number stored in 40 of the counter 3 is greater than the code of the number specified on tires 10, and Inverter 4 operates level 1, then on the first and second outputs of element 5 there are respectively O and 1 levels, as a result of which the 5 input controls the key 1 and the input to the record of counter 3 operates levels o. The counter 3 is constantly in boot mode code from tires 8 and 9. After the application of pulses of clock frequency to bus 7, each of their passes to the first output of the switch 1 and is supplied to the counting input of the counter 3. However, despite this, the state counter 3 is not changed, and the bus 11 is maintained at level O.

five;

Thus, if on tires 8 and 9 a code of the number M is set, the value of which exceeds the value of the code of the number K specified on tires 10 and lying in the range O K M

(in the example described), the division coefficient of the UDH in this case is defined as. those. The UDCH is set in the mode of prohibiting the passage of pulses from the bus 7 to the bus 11.

Let the code of the number M-1 be set on tires 8 and 9. After the UDF is reset to its initial state, in the counter 3 there is a code of the number minus one, i.e. all bits of counter 3 are set to 1. Since the output of inverter 4 is at level O, element 5 is prohibited and both outputs have levels O, as a result of which key 1 is set at the control input and counter 3 is set at the recording input O and 1, respectively. After applying clock pulses to bus 7, the first of them passes to the first output of key 1 and enters the counting input of counter 3, which causes all its bits to be switched to O. At the output of the inverter 4, level 1 is set, which allows element 5 to work Since the code of the number stored in counter 3 is smaller than the code of the number specified on bus 10, the O levels are kept at both outputs of the O. The next two pulses of the clock frequency (second and third) pass to the first output key 1 and increase the number in the counter 3 to two. As a result, the first output of element 5 and the control input of key 1 are set to level 1, and the second output of element 5 is maintained at level O. The fourth pulse of the clock frequency passes from bus 7 to second output of key 1 and goes to bus 11 and through element OR - NO 2 to the input of the record of the counter 3. At the same time, an output pulse is generated on the bus 11, the code of the number specified on the buses 8 and 9 is loaded into the counter 3, and the UDH returns to the initial state. If the clock pulses continue to arrive at the bus 7, the further operation of the UDCH is carried out similarly to that described.

Thus, if a number code is set on tires 8 and 9, then in this case the division coefficient of the UDCH for any value of the number K on the tires 10. lying in the range is defined as Cd (K + 2) (in the described case).

Let the number code be set on tires 8 and 9. After setting the UDCH to its original state, in the counter 3 there is a code of this number, i.e. the least significant bit of counter 3 is set to O, and the rest of its bits are set to G, which precludes operation

element 5. After applying clock pulses to bus 7, the first of them sets the low bit of the counter 3 to 1, and the second pulse sets all 5 bits of the counter 3 to 0. At the output of the inverter 4, level 1 is set, which allows the element to work 5. As a result of further operation of the UDCH on bus 11, an output pulse is selected, which coincides in duration and temporal position with the fifth pulse of bus 1. If the clock pulses continue to flow to bus 7, then the UHF operation is repeated. 15 Thus, if a number code is set on tires 8 and 9, then in this case the division ratio of the UDCH for any value of K number on tires 10 that lies in the range is defined as 20 Kd (K + 3) (in the considered example) .

It should be noted that for other negative values of the number M on tires 8 and 9 (i.e. in the general case for -3, -4, -5, ...- 2), the operation of the UDCH is carried out 25 similarly to that considered in the last two x and at the same time, each time when the value of the number M decreases by one as compared with the previous one, the division factor Kg of the UDCH increases by one respectively.

Thus, for the selected values of the code of the K number, its digit n and the codes of the M number, the most typical UDF operating modes would be considered and 35 for each of them the value of the real UDF dividing factor Kg was determined. These results can be obtained by substituting the source data in the expression (a). 0

Claims (1)

Claims of the invention The controlled frequency divider according to auth. Ss, NS 1517131, characterized in that, in order to extend the range 5, by changing the frequency of the output signal by reducing the value of its lower limit for a given value of the division factor, an inverter and a modulation code sign bus are entered into it, 0 code comparisons are provided with a resolution input, and the n-bit pulse counter is increased by one, with the additional bit being its highest bit, the information 5 whose input is connected to the sign bus of the modulation code, the output is connected via an inverter to the enable input of the operation of the code comparison element.