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Application filed by Войсковая Часть 32103filedCriticalВойсковая Часть 32103
Priority to SU4603581ApriorityCriticalpatent/SU1585802A2/ru
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Publication of SU1585802ApublicationCriticalpatent/SU1585802A/ru
Publication of SU1585802A2publicationCriticalpatent/SU1585802A2/ru
클럭 신호의 논리적인 결합에 의한 전자회로 테스팅 방법, 및 이러한 테스팅용 장치를 구비한 전자회로(A method for testing an electronic circuit by logically combining clock signals, and an electronic circuit provided with facilities for such testing)