SU1580364A1 - Multichannel priority device - Google Patents

Abstract

The invention relates to computing and can be used to control the access of several subscribers to a shared resource. The purpose of the invention is to improve the noise immunity of the device. The priority device contains three groups of elements HE 3, 4, 6, a group of elements OR 7, an element AND 10, two registers 9, 12, a group of shift registers 5, a priority selector of channels 14, an encoder 17. A priority selector of channels 14 contains a group of de-multiplexers and a group items are NOT. The device allows receiving the request signals from several communication channels, ensures the sequential allocation of a higher priority request and issuing to the outputs of the codes the numbers of their sources in the time division mode. 1 hp ff, 2 ill.

Description

20

25

possible combinations on address inputs - 15 corresponding logical buses 16.4 160п0

In the initial state, the logical buses (the outputs of the channel selector 16 are present, O, which is fed to the inputs of the encoder 17. The output of the encoder 17 produces a code 0.0.0, indicating that there are no requests about. At the outputs of the demultiplexers 19, there is 1 the HE elements 20 to the corresponding control inputs of the demultiplexers 19 and allow reception of signals through the inputs 13.1 to 13.P, and 1 of the output of the HO of the last demultiplexer 19 enters the output 15 of the channel selector and is the resolution for writing requests to the register 12

When 1 arrives at inputs 13 of node 14 at the output of the demultiplexer 19.1, corresponding to the combination of single signals at its address inputs5 and at output 16.1 of the device PCh 1 II

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dah corresponds to one open channel. The remaining channels are closed, t0e. are in the third state, in the presence of a voltage of logical 1 at the control input of the demultiplexer channels are closed

This circumstance allows you to connect the outputs of the demultiplexers 19 to the corresponding logical buses 16, on which the OR operation is carried out according to the wiring logic principle. Each logical bus corresponds to a request with its assigned priority number. With the closed channels of demultiplexers on logical buses, O is present, which is supplied through the corresponding resistors. Prioritization of the request is provided by the proposed scheme for combining the corresponding outputs of the demultiplexers on logical buses and by their operation control circuit. The numbers of the outputs of the demultiplexer being combined on the logical bus are determined from the expression d |

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35

is

testifying about

40

  2 + 2f (i-l), m-p

where 1

2, 3 "

(2), and the number of the logical tina p - 1, 2, 3 "o, t.

For example, on the logical bus 1601, the demultiplexer 19.1 channels are combined, which are open with logical combinations 001, 011, 101 and 111 at the A2P A1 and AO outputs, channels XI, X3, X5 and X7 are characteristic. The characteristic feature of these combinations is presence of 1 at the AO input, input status A2SA1 - any. The logical bus 16.2 combines Canada demultiplexes, which are open with logical combinations 010 and 110, at the inputs A2, A1 and AO, T, es cannapas X2 and X6 A characteristic feature of these combinations45

50

55

The fact that the request has been assigned the highest priority request 2.1. At the same time, the control inputs of the demultiplexers 19.2–19Ok form 1, which closes all channels of the demultiplexers 19.2–19, k and on the corresponding outputs 36 and 2 16.p selector and the output 15 of the channel selector is set to,

About output 15 is fed to the second input of the element 10 and prohibits the passage of the interrogation pulse to the clock input of the register 12, the single signal from the output 16.1 goes to the setup input of the trigger 8.1 of the register 9 and to the first input of the decoder 17, the trigger 8.1 is set to initial state At the output of the encoder 17, a code 0 ... 01 is generated indicating that the request

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25

thirty

35

H 1 II

 )

is

testifying about

The fact that the request has been assigned the highest priority request 2.1. At the same time, the control inputs of the demultiplexers 19.2–19Ok form 1, which closes all channels of the demultiplexers 19.2–19, k and on the corresponding outputs 36 and 2 16.p selector and the output 15 of the channel selector is set to,

About output 15 is fed to the second input of the element 10 and prohibits the passage of the interrogation pulse to the clock input of the register 12, the single signal from the output 16.1 goes to the setup input of the trigger 8.1 of the register 9 and to the first input of the decoder 17, the trigger 8.1 is set to initial state At the output of the encoder 17, a code 0 ... 01 is generated indicating that the request

accepted for service, came from the first channel. Upon completion of the service, the incoming request from channel 2 "1", the external device outputs to the device input 11 a single signal, which arrives at the setup input of the register 12 and sets it to the initial state. At the inputs 13, the priority selector 14 is set to O, which brings the demultiplexers 19 to the initial state. At the output of the channel selector 15 is set 1, which is fed to the second input of the element AND 10. With the arrival of the next interrogation pulse, the element And 10 is triggered to the first input of the element And 10 and a single signal arrives at the clock input of the register 12, which will write to the corresponding bits register information stored in triggers 8.2 and 8.3 of register 9c

Claims (2)

Invention Formula 1, A multichannel priority device containing a group of shift registers, a first register, an encoder, a priority channel selector, the outputs of which are connected to the inputs of an encoder, the outputs of which are the outputs of the device, so that , in order to improve the noise immunity of the device, three groups of NOT elements, a group of OR elements, a second register and an AND element are entered into it, the device polling input is connected to the clock inputs of the group shift registers and the first input of the AND element each request device input connected to the input of the element of the same name is NOT the first group, the outputs of the elements of the first group are not connected to the reset inputs of the group shift registers and the inputs of the corresponding elements of the second group NOT, the outputs of which are connected to the information inputs of the corresponding group shift registers, the outputs of the second bits of which through NOT elements of the third group are connected to the first inputs of the same-named elements OR groups, the second inputs of which are connected to the outputs of the third bits of the same name shift group registers, output The elements of the OR group are connected to the clock inputs of the corresponding bits of the first register, the output of each bit of which is connected to the information input of the same name of the second register, the reset input of which is connected to the reset input of the device, the clock input of the second register is connected to the output of the And element, the second the input of which is connected to the first output of the priority channel selector, the subsequent outputs of which are connected to the reset inputs of the corresponding bits of the first register, the single outputs of the second register with are united with the respective information channel priority selector inputs, 2. The device according to claim 1, characterized in that the priority channel selector contains a group of demultiplexers, a resistor and a group of elements NOT, and the address inputs of group demultiplexers are connected to the corresponding inputs of the priority channel selector, the zero output of each group demultiplexer is connected through the corresponding element of the group NOT to the control input of the subsequent group demultiplexer and through a resistor to the device logical zero bus, the zero output of the last group demultiplexer is connected to the first Exit priority - channel selector outputs demultnpleksorov subsequent groups combined and connected to corresponding priority channel selector outputs a control input of the first demultiplexer is connected to the group bus logic zero device selecting each input demultiplexer is connected to an input of the logical device units.