SU1444964A1 - 3b4b-3 binary code encoder - Google Patents

Abstract

The invention relates to telecommunications and can be used in digital transmission systems organized over fiber-optic and radio-relay communication lines. The aim of the invention is to improve the noise immunity of the encoder. The device contains a synchronization unit 1, an output signal shaper 2, a NOT 3 element, a serial register 4, a code group synchronization shaper 5, a parallel register 6, a code conversion unit 7, a clock frequency shaper 8, an element, 9 controls, and an HE element 10, 3 C .P. f-ly, 4 ill., 8 tablets.

Description

§

(L

with:

with

ten

11444964

The invention relates to telecommunications and can be used to transmit digital information via fiber optic and radio relay communication lines.

The purpose of the invention is to increase the encoder immunity.

FIG. 1 shows a block diagram of the binary code encoder ЗВ4В-3; in fig. 2 - time diagrams of the device; in fig. 3 - practical implementation of the former of the first symbol in the code group; on ig. 4 - digital sum counter on the border of code groups.

The encoder contains a synchronization block 1, an output signal generator 2, a HE 3 element, a serial register 4, a code 5 synchronizer shaper, a parallel register 6, a code conversion block 7, a clock frequency actuator 8, a frequency auto-sweep block 9, and a HE element 10 .

The synchronization unit 1 contains an HE element 11, a phase detector 12, frequency converters 13 and 14.

e pt d you n

n s

15 gr

su ko but

to you po ru ru poo cha

20

25

There are three alphabets in the table, each of which is used with the corresponding value of the current central sum (TCS) at the boundaries of the code groups by the time of arrival of the core group. The DSL is defined as the algebraic sum of the amplitudes of the pulses in the transmitted signal from the beginning of the transmission to the present moment.

The code conversion block 7 contains triggers 15-18, counter 19 digit-30 For example, if by the time of transfer of the sum on the code group boundary encoded by group 001 (Table 1) the counter 20 is a digital sum in the code group, the memory element 21, drivers 22-25 characters in the code group.

TPC -2, this group is transmitted by code group 1101 to the CA in the group of +2. At the same time, by the time the next coded group arrives, the TCS will be (-2) + (+ 2) (O) and the next group will be coded with a group of -2 from the alphabet with Tl. C As follows from the coding algorithm

Shaper 2 output signal z5 contains the trigger 26 and multiplex. sor 27.

FIG. 2 shows the following signals: a - the original binary signal; b - clock signal at the output of the first 40 vani clock frequency linear

TPC -2, this group is transmitted by code group 1101 to CA in groups of +2. At the same time, the TCS by the arrival time of the next coded group will be (-2) + (+ 2) (O and the next group will be coded with a group from the alphabet -2 with Tl. C) As follows from the coding algorithm

the item is NOT 3; c, d id are the signals at the outputs of the serial register 4; e is the signal at the output of the generator 5 of the sync signal of code groups; W - signals at the outputs of the parallel register 6; h - signals at the outputs of the memory element 21; - and, k, l, m - signals at the outputs of the first 22, second 23, third 24 and fourth 25 characters in the code group, respectively; n is the signal at the output of the frequency divider 13; o - signals at the outputs of the first, second, third and fourth triggers 15, 16, 17 and 18; n - signals at the outputs of the digital sum counter 20 in the code group;., p - signals at the outputs of the digital sum counter 19 at the boundaries of the code groups; с - output signal

element II; t is the signal at the output of the first frequency divider by two 23; y - the signal at the output of the imaging unit 8 clock frequency; f - signal at the output of the multiplexer 27; K - signal at the output of the element is NOT 10; C - the signal at the output of the device.

The device works as follows.

The conversion according to the encoding law ZV4B-3 is carried out in accordance with Table. one.

Table 1 next to each code group indicates the value of the digital

sums, defined as an algebraic sum of the amplitudes of the pulses in the code group, provided that the normalized voltage -1 and +1 are assigned to the symbols O and 1 of the code.

There are three alphabets in the table, each of which is used with the corresponding value of the current digital sum (TCS) at the boundaries of the code groups by the time the coded group arrives. A DSL is defined as the algebraic sum of the amplitudes of the pulses in a transmitted signal from the beginning of the transmission to the present moment.

For example, if at the time of transmission of the coded group 001 (Table 1)

For example, if at the time of transmission of the coded group 001 (Table 1)

wani clock frequency linear

TPC -2, this group is transmitted by code group 1101 to the CA in the +2 group. At the same time, by the time the next coded group arrives, the TCS will be (-2) + (+ 2) (O) and the next group will be encoded by a group of -2 in the alphabet with Tl .C 0. As follows from the coding algorithm, it will increase to 1, 33 times. At the same time, in the device the number of levels in the transmitted linear signal is two, which allows, with equal clock frequencies of the linear signal, to increase the noise immunity of the transmitted signal approximately two times.

The binary signal (Fig. 2, a) is written to the serial register 4 (Fig. 1, Fig. 2, c, d, e) by a clock signal from the output of the element HE 3 (Fig. 2.6) and is rewritten by the clock signal of the code groups (Fig. 2, f), coming from the output of the generator 5 of the sync signal of the code groups, to the parallel register 6 (Fig. 2, g). The signals from the outputs of the parallel register 6 (Fig. 2, g) are fed to the corresponding inputs of the drivers 22, 23, 24

and 25 of the first, second, third and fourth symbols in the code group. The remaining inputs of these drivers 22 - 25 receive signals from the output of the memory element 21 (FIG. 2, h), which is not (information about the value of TIS in the signal. For example , the ratio of the signals in Fig. 2, C 00 corresponds to the value of the TCS 0.10 - TCS + 2. And 1 - TCS -2. In accordance with this, the shaper 22-- 25 form the symbols of the ЗВ4В-3 code at their outputs (according to the table. 1) shown in parallel B110 (Fig. 2, and, k, l, m) In Fig. 2, the first transformation is highlighted in bold line. Group 001 (Fig. 2, a, g) with TC D (FIG. 2, s) encoded group 1101 (FIG. 2, and k, l, m) (see. Table. 1).

The signals from the outputs of the formers 22-25 (Fig. 2, l, m) arrive at the information inputs of the corresponding triggers 15, 16, 17 and 18, to the clock inputs of which the signal is output from the second frequency divider 13 (Fig. 2, n) . The signals from the outputs of the trigger 15 - 18 (Fig. 2, o) arrive at the corresponding inputs of the counter 20 of the digital sum in the code group, the signals at the output of which (figure 2, p) carry information about the digital sum in the code group: 00 - CA 0 ; 01 - CA -2; 10 - CA +2. Coded in binary form, the values of the CA in the code group (Fig. 2, p) are fed to the inputs of the counter 19 CA on the border of the code groups, the other inputs of which from the outputs of the element 21 receive the values

TCS on the border of code groups, also presented in binary form

(Fig. 2, h). The signals at the output of counter 19 are depicted in FIG. 2, p.

The synchronization of the signals involved in the processing and conversion of the binary signal (Fig. 2, a) is carried out using the synchronization unit 1, and the temporal relationships between them are shown in Fig. 2. 2, b, e, u, s, t, y, x.

The signals from the outputs of the trigger 15-18 (Fig. 2, o) are sent to the corresponding information. The inputs of the multiplexer 27, the address inputs of which receive signals from the outputs (Fig. 2, c, t) of the frequency dividers 53 and 14. The pulses of the clock frequency of the linear signal (Fig. 2, y) from the output of the imager 8, are inverted by the element 10 NOT (Fig. 2, x) and arrive

0

j 0

five

0

five

0

0

five

the clock input of the fifth trigger 26, the information input of which receives the signal from the output of the multiplexer 27 (Fig. 2, f). The trigger 26 is necessary to eliminate the creeps at the output of the multiplexer 27 and to generate the signal of the binary code ZVAV-3 (Fig. 2, n).

The sequential 4 and parallel 6 registers can be executed in synchronized registers on D-flip-flops, and the shaper 5 of the code group clock signal - in the form of a frequency divider by three. Phase detector 12 can be made in the form of a digital phase detector on a D-trigger, on circuit I, etc. The clock frequency generator 8 can be made in the form of a clock master oscillator, and block 9 in the form of, for example, series-connected low-pass filters, an amplifier and a varicap that controls the frequency of the generator.

Formers 22-25 of the first, second, third and fourth characters in the code group should be performed in accordance with the truth table presented in Table. 2 and obtained from the conversion table ZV4V-3 (Table II

In Table 2, A and B are signals from the output of memory element 2 (Fig. 2, 3), X ,, Xj and h are input symbols (fig. 2, g), YJ, Y, YJ, Y are code symbols (Fig. 2, and, k, l, m). In accordance with the table. 2, truth tables of shapers 22–25 of the first, second, third, and fourth symbols in the code group (Fig. 1) are obtained.

In tab. 3 - the truth table of shaper 22 of the first character in the code group is given.

. In tab. 3, the following notation is entered: x is an idle state. Under the table. Figure 3 shows the signals that must be sent to the information inputs of a KP7 type multiplexer.

In tab. 4 shows the truth table shaper 23 of the second symbol in the code group. : In tab. 5 shows the table of the true shaper 23 of the third symbol in the code group.

In tab. 6 shows a table of the ns-I mystery of the former of the fourth character in the code group.

Formers 22-25 in accordance with the table. 3-6, can be performed on KP7 type multiplexers. An example of the implementation of the former first signal generator in code group 8 is given in Table. 3

In accordance with the table, 1 obtained table. 7

In tab. 7 shows the truth table of the digital sum counter in the code group.

From tab. 7 it follows that the CA counter in code group 20 is implemented on type 2I-AND 4I-NO logic elements, where the output signals Z Zjj of counter 20 are described by the following logical functions:

and

2

/ Y,

. V v v

Ij 12 3 t

Y, Y, Y Y, Yj Yj Y

2 Yf -2 W

Truth tables

counter

CA on the borders of code groups 19, obtained using table. 1, are presented in table. eight.

An example of the implementation of the counter 19 digital sums on the border of code groups on multiplexers of type K2 in accordance with the table. 8 is shown in FIG. four.

Claims (4)

1. A binary code encoder ЗВ4В-3 containing a shaper of the code group clock, whose input is the clock input of the encoder, a code conversion unit and a clock frequency shaper that is 6 tons, so that, in order to increase the desensitization, the elements NOT are entered; synchronization, control, output driver, parallel register and serial registers, the input of the first element is NOT combined with the code group clock generator input, the output is connected to the synchronization input post edovatelnogo register, the outputs of which are connected to the data inputs of the parallel register, the first, second to third outputs of which are connected to the like input code conversion unit shaper output clock code groups is connected to the clock input of the parallel register and the first input of the first output of which is the synchronization unit, through the element control is connected to the input of the clock frequency generator, the output of which through the second element is NOT connected to the clock input of the output driver and directly to the second input of the synchronization unit. The second output of which is connected to the fourth input of the code conversion unit, the outputs of which are connected to information inputs output driver, the third output of the synchronization unit is connected to the fifth input of the conversion unit code and the first address shaper of the output signal, the fourth output of the synchronization unit is connected to the second address input of the shaper of the output signal, the output of which is the output of the encoder, the information input of the serial register is the information input of the encoder. I five 2, Encoder of claim. 1 ,. differ 5 0 I and with the fact that the code conversion block contains the first - fourth triggers, the digital sum counter in the code group, the digital counter on the code group boundary, the memory element and the symbol formers in the code group, the first, second and third information inputs of the drivers the characters in the code group are combined respectively and are the first, second and third inputs of the block, the output of each character generator in the code group is connected to the first input of the same-name trigger, the outputs of all the triggers are connected to the corresponding moves in counter digital sum code group, the outputs of which are connected to the data inputs of counter digital sum at the border of code groups, the outputs 5 of which are connected to the information inputs of the memory element, the outputs of which are connected to the corresponding address inputs of the digital sum counter on the border of code groups and character conditioners in the code group, the clock input of the memory element is the fourth input of the block, the second inputs of all the triggers are combined and are the fifth input of the block, the outputs of all the flip-flops are the outputs of the block. 3. Encoder under item 1, characterized in that the driver output signal contains a trigger 0 five 7.14449648 and a multiplexer, the output of which approach is the second output keys to the first input of the trigger block, the output of the first divider and the second input and output of which ow -. You are connected to the input of the second, respectively, divided by the clock input of the frequency and is a quarter of the output of the driver, the information of the block, the output of the second divider Both the first and second address inputs are connected to the input of the multiplexer dy element. They are the same name, NOT, the first input of the phase detector. the inputs of the driver. and is the third output of the block, ., 10 second input of the phase detector, its 4. The encoder in clause J, the distinguishing output and the input of the first divider, and with the fact that the synchronization unit is performed on the frequency dividers, the phase detector and the NOT element, are output the first input and output and the second input of the unit, respectively. T a b. l and c a 1 144496АJO Continuation of table 2 144А96412 Table A .l. 001 010 on 100 101 110 111 00o 1 o 1 o 1 o 1 01о 1 о 1 о 1 о 1 10o 1 o 1 o 1 o 1 11XXXXXXXX  L + TabliaaZ . 000001010on100 101po111 001oooo1 11o 011oooo1 11o 10 1oooo111o PxXXXXXXX -f +. + J Table 6 .. 000001010on100 101 no111 0011110000 01I1110 0 10 10 10110 0 00 llxXXXX X XX + G + -t-j. j and KL m and about P 2; - - Lg 5g / 77 J 11 II T-t U-J L-J I-J t1 I-I Do .. x LTijnLrxjnjT ruajrxrurL - 1 o - is - y FIG. g FIG. H Fy