SU1559345A1 - Device for computation of natural logarithm - Google Patents

Abstract

The invention relates to computing and can be used in general-purpose and specialized computers for calculating logarithms of numbers. The purpose of the invention is to simplify the device and increase speed. The goal is achieved by the fact that the device contains information input 1, register 2, the first block of permanent memory 3, the first switch 4, the multiplier 5, the second block of permanent memory 6, the counter 7, the second switch 8, the accumulating adder 9, the shifter 10, the adder 11, the synchronization unit 12, the start input 13, the output 14 of the sign of the end of the calculations, and the information output 15. The operation of the device is based on the relations: X = X ₀ ^. 1 / β ₁ ^. 1 / β ₂ ^{. ....} 1 / β _N-1 ^. Α _N

LNX = LNX ₀ -LNβ ₁ -...- LNβ _N-1 + LNΑ _N. 1 il.

Description

315

The invention relates to computing and can be used in general-purpose and specialized computers for calculating logarithms of numbers.

The purpose of the invention is to simplify the device and increase speed.

The drawing shows a block diagram of a device for calculating the natural logarithm.

The device contains information input 1, register 2, first block 3 of permanent memory, first switch 4, multiplier 5, second block 6 of permanent memory, counter 7, second switch 8, accumulating adder 9, shifter 10, adder 11, block 12 synchronization, launch input 13, output N of the calculation end, information output 15.

The device works as follows.

Argument X is fed to the information input 1 of the device. The trigger input 13 receives a trigger signal. The synchronization unit 12 generates a signal at the first output, which is input to the register entry 2. At the same time, at the output 1 of the sign of the end of the calculations, a signal is generated that turns off the device information input 1.

In the second cycle, signals C1 - C7, C9 and A1 are formed. According to the signals A1, the first switch 4 is configured to connect the first input to the output. The PB of the C5 signal in the multiplier is calculated

m ti Size --- ho

value, X / X0, where X0 is the value of the first group of bits of the number X. The size of the number X0 is determined by the digit of the first block 3 constant

the input of the second block 6 of the permanent memory, where the full-size value of 1pXv is formed, which is read by the GL signal. The signals Sb and C7 adjust the adder 11 in such a way that it only skips the value of the product from the output of multiplier 5, which is fed to the input of register 2 and written to it on the trailing edge of the signal C1.

On the falling edge of the SOC signal, in the counter 7 a code 01 is set. The counter is 7 logj C.ti + 1) -discharge and its outputs are connected to the upper address inputs. They define the page

the memory with which the device operates in a given tact. The distribution is as follows: 00 - X0, 01- (-In / 3,), 10- (-1pr), 11 - (- ln |} 3), etc. The second cycle of operation ends.

In the third cycle, the signals C1-C7, C9 and A1 are formed again. Code A1 at the input of the first switch C is formed so that a connection is formed to the second input at the switch output. In this case, n-bits of register 2 are connected to the second input of switch 4, starting with the lower order of the previous group.

The current group of n bits goes to the input of the multiplier 5 and the second block 6 of the permanent memory. The second memory area contains a table of values.

In p (-1n (2t-5,), where oG, 2.00 .. .0 xxx. ..X

n - 1 bits; n bits Multiplier 5 generates value

s /, (2-5: 1) (1- Ј ()

five ,

35

40

50

five

where pЈ, 0.00 .. ... .x,

n - 1 bits; n bits The input of the multiplier 5 and the constant memory unit 6 receives only significant bits of the quantity oi,, In the permanent memory unit 6, the corresponding shift and unit in the whole part are taken into account during the firmware. When multiplying, the corresponding shift must be made physically. This operation is performed by the shifter 10, the control inputs of which receive an A2 code, which adjusts it to shift the number by n − 1 bits towards the lower bits with one time inversion. The second input of the adder 11 receives the value o (, therefore, the required value og o, -, cx, is generated at its output. The resulting value on the trailing edge is entered into register 2. The value In ft read from block 6 of the permanent memory by signal C It enters through the second switch 8 to the input of accumulating adder 9 where it is added to the previous value by the signal C9. Counter 7 by the SOC signal is incremented by one

In the following cycles, everything repeats with the exception of codes A1 and A2, which vary so that the first switch k connects new groups of bits, and the shifter 10 increases the number of bits by which the multiplication result is shifted multiple of n-1.

In the last clock cycle, the first switch is configured so that it selects the next group of bits. Counter 7 is in the unit position, i.e. (11 ... 1). A memory field is connected where the value is written

1 at -2x

where X - n bits of the last selected group. At the same time, in the penultimate and last clock cycles, the signal C1 does not end and the result from the output of bargain 11 is not recorded in the register. The signal Ck is also not applied, and the output of memory block 6 is turned off. C8 and C9 signals are applied. The input of accumulating adder 9 receives the result from the output of adder 11 via the second switch 8 without the whole unit, which is zeroed. This value is added to the previous result stored in accumulating adder 9.

In the final stage, the signals C1, C8 and C9 are removed and the result present at the output of the adder I is recorded in the register 2, and the current result is recorded in the accumulating adder 9. The signals CA and C9 are then applied. The signal from the last memory region reads the value - 1/2 d5, which is added to the current result. Thus, in the adder the value is formed

H lnX0-ln ft, -Inflj -... ,,.

j lO2 + (X, c - 2 ft

which is the approximate logarithm of the desired quantity, i.e. 1pc

Claims (1)

Invention Formula A device for calculating the natural logarithm containing a register, first and second switches, a multiplier, a first block of permanent memory, an accumulator, and a synchronization block, characterized in that, in order to simplify the device and increase its speed, it contains an adder, a counter, the second block is constant memory, shifter and second switch, with the first output the synchronization unit is connected to the register write enable input, K- (K 2,3, ..., P, where p is the number of groups, register outputs; rb Ј 2,3,, n / 2i, n is the number of bits of the argument) the register output group is connected respectively to the K-th group of information inputs of the first switch, and 0 youngest bit 1 st (, 3, ...,) the register output groups is the highest bit of the jth (, P) register output groups, the first register output group is connected to the address5 and inputs of the first permanent memory block, the outputs of which are connected to the first group of information inputs of the first switch, the outputs of which are connected with the first information 0 multiplier inputs and lower address inputs of the second block of permanent memory, the higher address inputs of which are connected to the outputs of the counter, the outputs of the second block of constant 5 memories are connected to the first information inputs of the second switch, the outputs of which are connected to the information inputs of the accumulating adder, the second information inputs of the second switch are connected to the information inputs of the device, to the register inputs and to the outputs of the adder, the inputs of the first term of which are connected through the shifter to the multiplier outputs , the inputs of the second term of the adder are connected to the second information inputs of the multiplier and the outputs of the register; the read enable input of the first block PICs constant memory coupled to the second output of the synchronization unit, the input of which is an input device startup, the third output synchronization unit connected to the counting input of the counter, the fourth 5 output - with the read input of the second memory block, the fifth output - with the multiplier enable input, the sixth output - with the first pass enable input 0 summand adder, seventh output - with the addition input of the summation adder, eighth output - with the control input of the second switch, ninth output - with the control input of the accumulating adder, the output of which is the output of the device, the tenth output of the synchronization unit is connected to the control the first input of the first switch eleventh output - with up5 0 715593 58 the equalizer input, the twelve-character end of the computation device The central output is the output of the infusion.