SU813443A1 - Polynomial computing device - Google Patents

Description

(54) FACILITY FOR CALCULATING POLYNOMES

one

The invention relates to computing and is intended to compute algebraic polynomials at high speed.

Known devices with registers, adders and counters 1,

However, these devices with increased requirements for speed cannot provide the necessary speed for calculating algebraic polynomials.

The closest in technical essence and the achieved result to the proposed is a device containing the first register, the output of which is connected to the multiplier input of the first multiplier, the multiplicand input of which is connected to the output of the second register, the first input of which is connected to the first output of the third register, which input is connected with the output of the first adder, the first input of which is connected to the output of the first multiplier, the cycle counter, the first input of which is connected to the first input of the device, and the output of the cycle counter is Connected to the first output of the device 2.

The disadvantage of such a device is its low speed.

The purpose of the claimed invention is to improve speed.

The goal is achieved by the fact that the device for calculating polynomials contains the first register, the output of which is connected to the multiplier input of the first multiplier, the multiplicand input of which is connected to the output of the second register, the first input of which is connected to the first output of the third register, which input is connected to the output of the first adder, the first input of which is connected to the output of the first multiplier, the cycle counter, the first input of which is connected to the first input of the device, and the output is connected to the first exit of the device, entered multiplier, three adders, registers, cycle number setting block, four memory blocks, write control block, initial address shaper, the outputs of the write control block are connected respectively to the first inputs of the memory blocks, the second inputs of KOTOfXJX are connected to the second input of the device, and the input of the fourth register, the output of the first memory block 0 is connected to the second inputs

The second register and the first adder, the output of the second block, are connected to the first inputs of the fifth register and the second adder, the first output of which is connected through the sixth register to the second input of the fifth {1st register, the output of the first register is connected to the first inputs of the second, third and fourth multipliers, the outputs of which are connected respectively to the second input of the second adder and the first inputs of the third and fourth adders, the first outputs of which are connected respectively to the inputs of the seventh and eighth registers, output .tre The first memory block is connected to the first inputs of the ninth register and the second input of the third adder, the second output of which is connected to the second input of the fourth adder, the output of the seventh register is connected to the second input of the ninth register, and the first and second outputs of the eighth registrar are connected respectively to the second output of the device and to the first input of the tenth register, the output of the fourth memory block is connected to the second input of the tenth register and to the third input of the fourth adder, the first output of the second, multiplier is connected to the second input the house of the second adder, the second output of which is connected to the third input of the third adder, the second output of the third register is connected to the third input of the second adder, the first output of the fourth register and the output of the fifth register are connected respectively to the second and third inputs of the second multiplier, the second output of which is connected to the input of the first register, the second output of the fourth register to the second and third input of the fourth multiplier and the second input of the third multiplier, the output of the fourth multiplier is connected to the third input of the third the fourth multiplier, the fourth and fifth inputs of the second multiplier, and with the input of the eleventh register, the output of which is connected to the fourth input of the third multiplier, the fifth input of which is connected to the output of the ninth register, the second output of the third multiplier is connected via the twelfth register to the fourth input of the fourth multiplier, the fifth input in which is connected to the output of the ninth register, the third input of the device is connected through the thirteenth register to the inputs of the initial address generator and the block for specifying the number of cycles whose outputs are They are connected respectively with the input of the recording control unit and the second input of the loop counter.

Figure 1 is a block diagram of a device for calculating plinomas; in fig. 2 - placement of coefficients

the polynomial degree in FIG. 3; the distribution of the coefficients in the cells of the blocks.

The device for calculating polymers contains registers 1 and 2, um5 knife 3, adder 4, registers 5 multiplier 8, adder 9, registers 10-12, multiplier 13, adder 14, register 15-17, multiplier 18, adder 19, register 20 , blocks 21–24 of memory, block 25 of writing control, shaper 26 of initial address, register 27, block 28 of setting the number of cycles, counter 29 cycles, inputs 30–32 of the device, outputs 33–34 of the device,

5In the device polynomials of the form

.. .. + and where Y is the value of the computed

polynomial; a „, a„., ... - coefficients poly-,

noma;

X - independent variable;

 - the degree of the polynomial, a positive integer, is divided into four branches, in which the values of Y, Y, 3, Y are calculated, the sum of which is Y.

Moreover, the values of Y, Y4, Oz, Y4 are calculated simultaneously. in the device, polynomials of any degree L415 can be calculated. With and 15, the coefficients with the absence of their oldest powers x x (, ats, ..., ats + - () are assumed to be equal to zero. The coefficients a,, ..., a, a come from the memory to the input 30 of the device and are placed in blocks 21-24,

In the case where the missing coefficients are replaced in memory cell locations. At the same time, if all coefficients occupying the first memory cells are absent, all the remaining coefficients are estimated in one cell up one cell until at least 5 in one of the first cell blocks: it will contain a nonzero coefficient code, and the change in the position of the coefficients the cells of the memory blocks are combined with their loading with the help of blocks 26 and 25.

The determination of the number of cycles of operation of the device necessary for calculating a polynomial of a given degree is carried out by block 28. The number of cycles 1 is determined depending on the degree of the given polynomial n as follows when

The loop counter 29 is used to determine when the calculation of the polynomial ends.

Claims (2)

The operation of the device (by the example of calculating a polynomial of degree) 5 is as follows. The computation of a polynomial begins with the fact that register 27 enters the order of a given polynomial at input 31 of the device. Block 28 determines the required number of calculation cycles, which is recorded in loop counter 29. Block 26 determines the address of the cell, starting with which the coefficients of the polynomial entering the device are expanded in memory blocks. The address from the output of block 26 enters the record control block 25. The inputs 30 of the device receive the values of the independent variable X, which are written to register 6 and then the coefficient of the polynomial, hell, a. . . , a, ao. The coefficients enter the device in the order of decreasing their numbers and are placed in the cells of the blocks 21-24 according to the signals from the output of the recording control unit 25 (FIG. 3). The value of the independent variable x from the second output of register 6 goes to the first inputs of the multiplicand and multiplier of the multiplier 18 and to the first input of the multiplicand multiplier 13, the value of x obtained in the multiplier 18, from its first output is written to the register 11 and goes to the third input of the multiplier 13 and At the first inputs of the multiplicand multiplier multiplier 8. The value obtained at the first output multiplied l 13 is written to register 16. At the first output of multiplier 8, the value x is obtained, which is written to register 1, Simultaneously, from blocks 21-24. the values of the coefficients located in the first cells are written to registers 2, 7, 12, 17, respectively. The output of register 1 is connected to the multiplier 3 input and to the multiplier 8, 13B inputs, and to the multiplier 3 inputs, 8, 13, 18, respectively, the outputs of registers 2, 7, 12, 17 are connected. Then, a multiplication operation is performed simultaneously in all multipliers. The results of multiplying from the output of the multiplier 3 and from the second outputs of the multipliers 8, 13, 18 go to the first inputs of adders 4, 9, 14, 19, respectively, and the second inputs are fed to the values of coefficients read from the second memory blocks. The result from the first outputs of the adders is written to registers 5, 10, 15, 20 and then transmitted to them through the second inputs to registers 2, 7, 12, 17. After that, the signal received at input 32 of the device is subtracted from the delayed counter of 29 cycles. unit This completes the first calculation cycle, as a result of which in register 2 the value of register 7 is found, the value in register 12 is a .., in register 17, value a and in the counter of cycles 29 value. The second calculation cycle is performed in the same way as the first cycle, except that the result from register 5 is not transferred to register 2, but stored so, until the next cycle. After executing the second calculation cycle, register 5 contains the value (, in register 7, the value (), in register 12, the value (a), in register 17, the value and in the cycle counter 29, the value. When the final calculation cycle is performed, where the first output of register 6 is connected to the second input of multiplier multiplier 8, to the third input of the multiplicand of which is connected the output of register 7, the output of register 11 is connected to four, that input of multiplier 13, the fifth input of multiplicand of which is connected to the output of register 12, the output of register 16 Full construction It is connected to the fourth input of the multiplier 18, the fifth input of which is connected to the output of the register 17, the second output of the register 5 is connected to the third input of the adder 9, the first input of which is connected to the second output of the multiplier 8, the second output of the adder 9 is connected to the third input of the adder 14, the first the input of which is connected to the second output of the multiplier 13, the second output of the adder 14 is connected to the second input of the adder 19, the first input of which is connected to the second output of the multiplier 18. The (+) x value obtained at the first output of the multiplier 8 goes to the first The second input of the adder 9 is summed there with the operand () arriving at the third input of the adder from the second output of the register 5. The sum from the second output of the adder 9 enters the input of the adder 14 and is summed there with the product. (a,) X a) x, coming from the first output of the multiplier 13. The sum from the second output of the adder 14 enters the third input of the adder 19, the first input of which receives the product) x from the first output of the multiplier 18. From the output of the adder 19 value the computed polynomial is written to register 20. A unit is subtracted from the contents of cycle counter 29, after which a signal is output to the control unit at the second output 34, which terminates the computation of the polynomial and the result from the first output of register 20 at the first output 33 is removed from the device. The application of the proposed device allows to increase the speed of calculating algebraic polynomials by 4 times. The invention The device for calculating polynomials, containing the first register, the output of which is connected to the input of the multiplier of the first multiplier, the input of which is connected to the output of the second register, the first input of which is connected to the first output of the third register, the input of which is connected to the output of the first adder, the first input of which is connected to the output of the first multiplier; the cycle counter, the first input of which is connected to the first input of the device, and the output is connected to the first output of the device, which is different from the fact that, in order to improve speed, three multipliers, three adders, registers, a block for setting the number of cycles were entered into it, four memory blocks, a write control block, a starting address generator, the outputs of the write control block are connected respectively to the first inputs of the memory blocks whose second inputs are connected to the second input of the device and to the fourth register input, the output is not The first memory block is connected to the second # 1 inputs of the second register and the first adder, the output of the second memory block is connected to the first inputs of the fifth register and the second adder, the first output of which is connected through the 1st register to the bottom of the fifth register, the output of the first register is connected to the first inputs of the second, third and fourth multiply, lei, the outputs of which are connected respectively to the second input of the second cy 1 mate and the first inputs of the third and fourth adders, the first outputs of which are connected respectively to the input The seventh eighth register, the output of the third memory block is connected to the first inputs of the ninth register and the second input of the third adder, the second output of which is connected to the second input of the fourth adder, the output of the seventh register is connected to the second input of the ninth register, the first and second outputs of the eighth the register is connected respectively to the second output of the device and to the first inputs of the tenth register; the output of the fourth memory block is connected to the second input of the tenth register and to the third input of the fourth adder, the first The second output of the second multiplier is connected to the second input of the second totalizer, the second output of which is connected to the third input of the third adder, the second output of the third register is connected to. the third input of the second adder, the first output of the fourth register and the output of the fifth register are connected respectively to the second and third inputs of the second multiplier, the second output of which is connected to. the input of the first register, the second output of the fourth register to the second and third inputs of the fourth multiplier and the second input of the third multiplier; the output of the fourth multiplier. connected to the third input of the third multiplier, the fourth and fifth inputs of the second multiplier, and to the input of the eleventh register, the output of which is connected to the fourth input of the third multiplier, the fifth input of which is connected to the output of the ninth register, the second output of the third multiplier is connected through the twelfth register to the fourth input of the fourth multiplier The fifth input of which is connected to the output of the tenth register, the third input of the device is connected via the thirteenth register to the inputs of the initial address generator and the block for setting the number of cycles, the outputs of which are connected respectively to the input of the recording control unit and the second input of the cycle counter. Sources of information taken into account in examination 1, USSR Author's Certificate No. 556446, cl. G 06 F 15/32, 1976, 2. US patent number 3978326, cl. 235-152, 1970 (prototype). (gfl I yt TT jff 32 ryy.Z