SU1557568A1 - Device for interfacing processor and multiple-unit memory - Google Patents

Abstract

The invention relates to computing and can be used to increase the amount of memory in the construction of computer systems based on microcomputers. The aim of the invention is to reduce the hardware cost of the device when creating a multi-block processor memory. The goal is achieved by the fact that an address counter and a single vibrator are entered into the device containing the address switch, address decoder, array number register, channel transmitter, channel receiver, first and second channel transceivers. 5 ill., 1 tab.

Description

The invention relates to computing and can be used to increase the amount of memory when building microcomputer-based computing systems.

The aim of the invention is to reduce the hardware cost of the device required to create a large multi-block memory.

Figure 1 presents the block diagram of the proposed device; figure 2 - the structure of the complex using the device; FIGS. 3 and 4 show timing diagrams of the operation of the device in write and read cycles; figure 5 is an example of a functional diagram of the address decoder.

Device 1 (FIG. 1) contains address decoder 2, register 3 numbers of the array, channel transmitter 4, channel receiver 5, first and second channel transceivers 6 and 7, address counter 8, address switch 9, one-shot 10, first output 11 of the decoder 2 addresses, output 12 channel transceiver 6, second output 13 of terminal 2 address, output 14 of channel transceiver 7, third and fourth outputs 15 and 16 of the decoder 2 addresses, outputs 17, 18 and 19 of the channel receiver 5, output 20 of register 3 of the array number , information inputs / outputs 21 devices 1, in Odes 22, 23 and 24 address synchronization signals, reading and writing a group of inputs of a channel receiver 5, information inputs-outputs 25 of the second channel transceiver 7, outputs 26 of the address counter 8, outputs 27 of the address switch 9, seventh output 28 of the address decoder 2, output 29 of the single-oscillator 10, the fifth and sixth outputs 30 and 31 of the address decoder, the reset input 32 of the device 1, the processor bus 33 and the processor multi-memory bus 34.

QS

The interfacing device 1 is intended for interfacing a processor with a multi-block memory (FIG. 2) containing memory blocks 35 consisting of memory nodes (banks) 36.

The address decoder 2 (FIG. 5) consists of the address register 37, the decoder 38, and the fixed memory node 39. In the address register 37, the address is strobed to the device 1. The decoder 38 is intended

to decode the address supplied to device 1. When signals to the decoder 38 are received from the outputs of the AO register of the address 37, the corresponding outputs 41, 42 and 43 of the decoder 38 generate signals for selecting the address, status and data registers registers. Node 39 performs the function of conjunction between input signals in accordance with the table.

Note.

In the time diagrams (Figs. 3 and 4) of the operation of the device in the write and read cycles, the following symbols are taken: a - signals on the data lines of the processor's main line} b - signal of the OEM address clock on the processor's main line; c is the readout signal of DTA on the processor main; g - signal recording DZP on the processor bus; d - signal at the output of the launch of the decoder 2 addresses; e is the signal at the output of the one-shot 10; W - signals on the data address lines of the multi-block memory mainline; e - address synchronization signal on the multi-block memory bus; and - the DZP recording signal on the multi-block memory bus; K - readout signal of DChT on the multi-block memory mainline; l, m - signals on the first and second outputs of the decoder 2 addresses.

Device 1 operates as follows.

The entire address space of the multi-block memory bus 34 is divided into segments, which can be of arbitrary size. Each segment is assigned one memory block 35. The volume of each block of memory 35 is divided into equal parts — banks of 36 banks, and the volume of each bank of 36 memory is equal to the volume of the segment. The memory segment is the space through which the memory block 35 is available for

(+) - the presence of a signal;

(-) - no signal, i

device 1, and the selection of a memory cell within memory block 35 is performed using the lower-order address bits supplied to memory blocks 35 from input-output 25, forming bi-directional data address lines of multi-block memory bus 34. The selection of the required memory bank 36 is performed by using the higher bits of the Dov address fed to the blocks of the memory 35 from the outputs of the 20 most significant bits of the address. In the address space of the processor bus 33, device 1 occupies three addresses: a data register (RD); Address Register (PA); a state register (PC), with the help of which data is exchanged between the processor and multi-block memory, the RD is intended for data exchange between the processor and the multi-block memory, PA - to set the initial address of the read data array in memory blocks 35, a PC — to set the higher bits of the trunk address 34 of the multi-block memory.

The device 1 performs the replacement of the address of the PD by the current address of the trunk 34 of the multi-block memory when it is translated into blocks of memory 35 in the write and read cycles of the processor at the address of the PD.

When turning on the power of the system, the processor sets the reset signal of the SET, which at input 32 resets

0

five

0

five

the register 3 of the array number and the address counter 8, while the processor becomes accessible to the zero memory bank 36 of the zero memory block 35 from the zero address. If it is necessary to access the multi-block memory from an arbitrary address, using the PA and PC are set respectively the starting address of the readable data array from the corresponding memory block 35 and the high-order bits of the address by which the corresponding memory bank 36 of this memory block 35 is selected. .

Record information in the register of address 7 of the transceiver, through which

and the status register is as follows. The processor sets the address of the PA or PC at the first information inputs-outputs 21 of the interface 1, which through the first channel transceiver 6 enters the address decoder 2, then the processor sets the synchronization signal of the MBO address at the input 22 of the signal of the device address synchronization In the decoder there are 2 addresses, Next, the processor sets the input-output 21 data: the starting address in the corresponding memory block 35 when writing to PA or the higher bits of the address when writing to the PC. These data through the first channel transceiver 6 arrive at the information inputs of the counter 8 addresses and register 3 numbers of the array. Next, the processor sets at write input 24 a write write command command, which enters the write input of address decoder 2, and if PA or PC is accessed, respectively, outputs 30 and 16 of address decoder 2 will receive write signals to address counter 8 or register 3 array, on the front of these signals, the data is written respectively to the address counter 8 or register 3 of the array number. Next, the processor ends the cycle of accessing the device 1, removing the signal to the ACU "

Writing to the memory cell of memory block 35 is performed as follows.

In the initial state, the first channel transceiver 6 is enabled to receive signals from the inputs-outputs 21 of the device 1 to the outputs 12, the second channel transceiver 7 is switched on to transmit data from the information inputs 27 to the inputs-outputs 25, and

address mutator 9 is enabled for data broadcasting from outputs 12 of the first channel transceiver 6 to you | moves 27. At the beginning of the write cycle, the address of the remote controller enters the input of the address decoder 2, is decoded by it as the address of the remote controller, and output 28 shows the trigger signal of the one-shot 10, on the front of which it starts and switches its address 29 to the signal from its output 29 address from the output 26 of the counter 8 addresses to the information inputs of the second channel

0

five

0

the address enters trunk 34 of multi-block memory. Next, the address enters the memory blocks 35, and the processor sets the synchronization signal of the MBP address, which through the channel receiver 5 enters the main memory 34 of the multi-block memory. On the front of the OBM signal, the RD address gates in the decoder 2 addresses and gates the current address in the multi-block memory, after that the one-shot 10 finishes forming a pulse at its output 29 and the switch 9 of the address returns to its initial state. The pulse duration at the output 29 of the one-shot 10 is chosen equal to the time the address is retained by the processor on the data address lines of the processor main 33 in channel access cycles. Next, the processor sets the data to be written to the memory at the inputs / outputs 21 of the device. These data are transmitted via the first channel transceiver 6, the address switch 9, the second channel transceiver 7 to the multi-block memory bus 34 and to the memory blocks 35. Next, the processor sets the DZP write signal, which is fed to the input of the address decoder 2 and through the channel receiver 5 to the multi-memory memory trunk 34 — at the output 31 of the address decoder 2, a count signal appears, and

0, one of the memory blocks 36 records data into a memory location corresponding to the current address. Further . the processor removes the DZP signal, while the memory bank 36 ends

There is no data record, and at the output 31 of the address decoder 2, the signal of the account is captured, by slice of which the content of the counter 8 of address1 changes by one, i.e. device 1 is prepared

five

0

is pressed to the next write or read cycle, and the processor ends the current write cycle, removing the MBP signal. The time diagram of voltages in the recording mode is shown in Fig.3 „

Data is read from multi-block memory as follows.

In the address part of the read cycle, the operation is similar to the write cycle, then the processor sets the readout signal of the DPT on the processor main line 33, which is fed to the read input of the address decoder 2, and through the channel receiver 5 is transmitted to the multi-block memory main line 34. In this case, control device 1 appears at outputs 11 and 13, switching the first and second channel transceivers 6 and 7 to transmit data from the multi-block memory bus 34 to the processor bus 33, and output 31 of the address decoder 2 appears - an invoice, at this time, from the selected memory bank 36 from the memory cell corresponding to the current address, data is being read, which, from the multi-block memory main line 34, are transmitted to the processor main 33, which reads this data and ends the read cycle This means that in device 1 the first and second transceivers are switched to the initial state, and the cutoff of the counting signal causes the current address in counter 8 to be changed by one.

Claims (1)

Invention Formula 45 A device for interfacing a processor with a multi-block memory, comprising an address switch, a channel receiver, the input and output groups of which are the corresponding input and output groups of the device for connection to the processor's synchronization buses and the multi-block 50 50 five 0 memory, two channel transceivers, the inputs / outputs of which are | corresponding entrances exits. | devices for connecting to the information buses of the processor and multi-block memory buses, and the control inputs, respectively, to the first and second outputs of the address decoder, the group of synchronization inputs of which are connected to the input group of the device for connecting to the synchronization buses of the processor trunk, and the third output is connected to the input of the channel transmitter, the output of which is connected to the input-output of the device for connection to the information buses of the processor, the register of the array number, the write input to The oho is connected to the fourth output of the address decoder, and the output is connected to the informational- 1 formation input of the channel transmitter and is the output of the device for connecting to the address bus of a multi-block memory, the output of the second channel transceiver connected to the information input of the first channel transceiver, the output of which connected to the information inputs of the address decoder and the register of the array number, characterized in that, in order to reduce hardware costs, an address counter and a one-shot are entered into it, The output of the first channel transceiver is connected to the information input of the address counter and the first information input of the address switch, the output and the second information input of which are connected respectively to the information input of the second channel transceiver and the output of the address counter, whose recording and counting inputs are connected respectively to the fifth and sixth the outputs of the address decoder, the seventh output of the one-way connected via the one-shot to the control input of the address switch, the reset inputs of the array number register and the address counter is the input to the device to connect to the processor reset bus. / H I V L. jj V / l $ /. /  Tojjf; Jtf Wj J J4 " J Jtf Is .J a HDQEESHX s b-state fes / ftwwe / v / l 0i / f.5  - state 8 zltlichno Yal