SU1552406A1 - Device for measuring signal-low-frequency ratio - Google Patents

Abstract

The invention relates to television. The purpose of the invention is to reduce the measurement time. The device contains fixing unit 1, switches 2 and 5, time selector 3, low pass filter 4, voltage converter 6, A / D converter 7, control signal generator 8, memory block 9, calculation unit 10, display unit 11, subtractor 12, maximum selection block 13 and generator 14 addresses. The whole measurement cycle is carried out in two stages. At the first stage, the signal is measured, and at the second stage, the low-frequency noise level is measured. Further, based on the results obtained, the ratio of the signal level to the level of the low-frequency noise is calculated. In this case, the time required to measure this ratio is halved. 1 il.

Description

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The invention relates to television measurements and can be used to measure low frequency background noise.

The purpose of the invention is to reduce the measurement time.

The drawing shows a block diagram of a device for measuring the signal / low frequency interference ratio,

The device contains a fixing unit 1, the first switch 2, a time selector 3, a low-pass filter U (LPF), a second switch 5, a voltage converter 6, an analog-to-digital converter (A / D converter) 7, a forcing control signal 8, memory unit 9, calculation unit 10, display unit 11, subtractor 12, maximum selection unit 13 and address generator.

 The device works as follows.

At the first stage of the measurement cycle, the measurement of the scale of the signal is made. At the same time, the TV signal fixed on the rear pads of horizontal damping pulses in the TV fixing unit 1 is fed to a voltage converter 6, which may be series-connected low-pass filters that separate the luminance signal, C the peak detector. 8 transducer transforms the signal voltage to k}, which goes to the first input of the second switch 5. From its output, this voltage goes to the ADC 7, where it is digitized and stored in the memory register of the block 10 calculations.

At the second stage, the low-frequency background noise level is measured, and the signal is fed to the inputs of the first switch 2 directly through the fixing unit 1. Switch 2 is used to select the measurement mode. The total component of the low-frequency background noise level is measured without a level fixation, and the multiplicative component is by a level fixation. From the output of the commutator 2, the signal, which excludes synchronization pulses from the full TV signal, is fed to the input of the low-pass filter k, designed to reduce the error due to the presence of fluctuation

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interference. From the output of the LNP signal, the signal through the second switch 5 enters the ADC 7, where it is converted into digital form in specified areas of the raster defined by address generator 1.

The counts obtained during the first frame are stored in memory block 9. In subsequent frames of the measurement cycle, repeating the same addresses, the signal is converted to ADC 7 and the sample difference calculated in the first and subsequent frames and in the subtractor 12. The resulting difference enters the maximum selection unit 13, where in a time equal to the half-period of the difference frequency, the maximum value coming from the subtractor 12. This value corresponds to the level of background noise. The measured value of the background noise enters the calculation unit 10, where the ratio of the background noise level to the signal level is calculated.

The resulting ratio is displayed in the display unit 11,

The address generator 11 can be made in the form of a serial register counter and a clock pulse generator. The counter is reset by frame pulses, and counts the pulses of the rows. The code from the counter goes to the address lines of the memory block 9. The shift register is reset by the pulse of the rows, and the signal in it is advanced by pulses from the clock generator. The pulses from the successive bits of the shift register are fed to the A / D converter 7, the input of the memory unit, and the control input of the maximum selection unit 13.

The maximum selection block 13 is constructed as follows. The signal from the output of the subtractor 12 is fed to one input of the arithmetic unit (AU). A signal O is applied to its second input. Depending on the sign of the input difference, the operation 0-S or 0 + S is selected in the AU. Thus, a positive number is always set at the output of the AU. The signal from the output of the AU is fed to the inputs of the comparator directly and through the register. The write enable input to the register is connected to the comparator output, and a signal from the AND-address generator is supplied to its clock input. At the beginning of the measurement cycle, the register is zeroed out, and at the end of the cycle its contents are equal to the maximum absolute value of the signal at the output of the subtractor 12.

The use of the device allows a 2-fold reduction in the time required for measuring the signal-to-low-frequency interference ratio at the telecentres and when monitoring TV receivers.

Claims (1)

Apparatus of the Invention A device for measuring the signal-to-frequency interference ratio, comprising a latching unit, a driver for controlling signals, a memory unit, a computing unit, a display unit, and the first switch, the output of which is connected to the first signal through a series-connected time selector the input of the second switch, the second signal input of which is connected to the output of the voltage converter and the output to the first input of the analog-digital converter, the input of the voltage converter connected to the first signal input of the first switch and with the output of the fixing unit, the first, second, third, fourth outputs of the control signal generator are alternately connected to the control inputs of the second and first switches, the time selector and the fixing unit, respectively, the input of which is combined with the second signal input of the first comm5 the driver of the control signal generator is the device input, characterized in that, in order to shorten the measurement time, a subtractor, a maximum selection unit and an address generator are inputted, the output of the analog-to-digital converter in parallel connected to the signal input of the memory unit, the first input of the subtractor, and the first signal input of the computing unit, the output of which is connected to the signal input of the display unit, the fifth, sixth, seventh, and eighth outputs of the control signal generator, in sequence. alternately connected to the control inputs, respectively, of the display unit, maximum selection unit, calculation unit and memory unit, the ninth and tenth outputs of the driver of control signals are connected to the first and second inputs of the address generator, the first and second outputs of which are connected to the address inputs, respectively analog-to-digital converter and maximum selection block, the output of which is connected to the second signal input of the computing unit, the third and fourth outputs of the address generator are connected to the first and second addresses The common inputs of the memory block, the output of which is connected to the second input of the subtractor, the output of which is connected to the signal input of the block 0 five five select the maximum.