JP2002014123A - Spectrum analyzer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a respective values of a positive peak and a negative peak, and to provide concurrently an average value thereof, without imposing a processing load to an analyzer, to display them. SOLUTION: A signal output from a VBW filter 16 is detected by a detection part 18. The detection part 18 has a positive peak detecting means 18a for detecting the maximum value of the signal, and a negative peak detecting means 18b for detecting the minimum value of the signal, and holds a positive peak value and a negative peak value respectively. A switch 28 is switched by each clock of an A/D-converting part 19, and outputs the respective peak values to a switch waveform memory 20. A signal-processing part 21 conducts reading in a sampling period with an N-multiplied (N=2 or more) value of that in the A/D converting part 19 with respect to display in a display part 19, and calculates the average value by an averaging processing part 22 to update it on a real-time basis to be displayed on the display part 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spectrum analyzer, and more particularly, to a spectrum analyzer capable of selectively or simultaneously displaying a negative peak value, a positive peak value, and an average thereof.

[0002]

2. Description of the Related Art Conventionally, a spectrum analyzer can select and convert one or both of an average value of a maximum value (positive peak) and an average value of a minimum value (negative peak) during a measurement period. The most suitable conversion mode is selected for analysis.

[0003] The peak values of these signals can be obtained by roughly two methods. 1. A method of narrowing the band (video signal band) of a VBW filter provided in a spectrum analyzer to obtain a video average. 2. A method of obtaining a signal by averaging the signal after a plurality of samplings at a predetermined N samplings.

[0004]

Problems to be Solved by the Invention In the method,
Although an average value can be obtained by one sampling, there is a problem that a response time is required due to a hardware limitation of the apparatus and a measurement time is required. As a result, the speed of video averaging cannot be increased. 2. In the method of (1), since the value at the time of sampling for each predetermined cycle is used, the peak value of the signal cannot be obtained, and the sampling of a plurality of screens is averaged. It took time and processing time.

[0005] Further, in the above 1.2. In either configuration, only the average value of the positive peak or the average value of the negative peak or only the average value of the waveform that is not peak-held can be obtained, and the average between these positive peaks and the negative peaks can be obtained. No value could be obtained. As a result, when performing analysis from various viewpoints depending on the type of signal, even when an average value of the waveforms of the negative peak and the positive peak is required, this cannot be performed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in particular, has as its object to provide a spectrum analyzer capable of obtaining and displaying an average value of a positive peak and a negative peak without imposing a processing load on an apparatus. And

[0007]

In order to achieve the above object, a spectrum analyzer according to the present invention comprises a receiving section (6) for sweeping the frequency of a signal under measurement at a predetermined cycle, converting the signal into an intermediate frequency signal, and outputting the intermediate frequency signal; Receiving the intermediate frequency signal,
A detection unit (18) that detects and outputs a positive peak value and a negative peak value of the signal under measurement and is reset by a clock, and outputs the output of the detection unit with a predetermined sampling number m (integer) within the predetermined period. An A / D converter (19) which samples in synchronization with a clock, converts the data into digital data, and outputs the digital data; and receives k (in an integer from 1 to m) sampling numbers in response to the digital data within the predetermined period. A signal processing unit (21) for calculating and outputting an average value of the positive peak value and the negative peak value;
A display section (17) for receiving an output of the signal processing section and displaying the output as a spectrum waveform of the signal under measurement.

The display section (17) displays a spectrum waveform based on the positive peak value of the signal under measurement, a spectrum waveform based on the negative peak value of the signal under measurement, and a positive peak value of the signal under measurement. Any of the spectrum waveforms based on the average value of the negative peak values can be selected or can be displayed simultaneously.

The A / D conversion section (19) has one A / D converter, and alternates a positive peak value or a negative peak value of the signal under measurement detected by the detection section (18). The signal processing unit (21) calculates the average value of the positive peak value and the negative peak value every h (an integer of 2 or more and m or less) sampling numbers by switching every clock. It may be configured.

The detection section (18) includes a positive peak detection circuit (26) and a negative peak detection circuit (27) connected in parallel to an input signal path of the signal under measurement, and the positive peak detection circuit And a holding circuit provided in the negative peak detection circuit for holding each detected peak value. The A / D converter (19) independently controls the outputs of the positive peak detection circuit and the negative peak detection circuit. A / D conversion may be performed.

According to the above configuration, the positive peak value and the negative peak value of the input signal under measurement are detected. Further, an average value of the positive peak value and the negative peak value is calculated. A positive peak value, a negative peak value, and a spectrum waveform of an average value thereof are selectively or simultaneously displayed on the display unit.

[0012]

FIG. 1 is a block diagram showing a schematic configuration of a spectrum analyzer according to the present invention. Hereinafter, the configuration of the spectrum analyzer 1 of the present example will be described along the signal processing procedure with reference to FIG.

A high-frequency analog signal under test of, for example, several hundred KHz to several GHz, which is input through the input terminal 2,
The signal level is adjusted to a specified level by an attenuator (not shown), input to the signal mixer 6, and output via an IF filter 7. The high-frequency signal to be measured is supplied to the signal mixer 6.
After being synthesized with the local oscillation signal from the local oscillator 5 to be converted into an intermediate frequency signal having an intermediate frequency, band-limited by the IF filter 7, logarithmically converted by the LOG converter 15, and input to the VBW filter 16. You.

One sweep time is set and input to the sweep control unit 12 by the user, and a sweep is performed over a sweep frequency range (measurement frequency range) with the set sweep time.
As a result, the frequency of the intermediate frequency signal output from the signal mixer 6 also changes in synchronization with the sweep operation.

The IF filter 7 is composed of an analog band pass filter, and has a bandwidth (R
BW) is variably set. The IF filter 7 removes unnecessary frequency components of the intermediate frequency signal input from the signal mixer 6 and passes only the intermediate frequency signal of the frequency component having a variably set bandwidth, and the gain is adjusted by an amplifier (not shown). After that, it is input to a LOG conversion unit (LOG) 15.

The intermediate frequency signal input from the IF filter 7 via an amplifier (not shown) is output after the signal level is converted by the LOG conversion unit 15 into dB units.
(DC) component), then the next analog VBW
Input to the filter 16. In the VBW filter 16,
The high frequency component (noise component) of the frequency spectrum waveform finally displayed on the display unit 17 as an output unit is removed to output a signal.

The signal output from the VBW filter 16 is detected by the next detector (DET) 18. The detection unit 18 includes a positive peak detecting unit 18a that detects a maximum value of the signal, and a negative peak detecting unit 18b that detects a minimum value of the signal. Each of these detectors 18a and 18b is provided with a peak hold circuit (not shown), which is reset by the next clock and holds a new peak value in the next cycle. Then, the positive peak value and the negative peak value during the clock cycle synchronized with the sampling cycle are respectively held.

The signal detected by the detector 18 is converted into digital data by an A / D converter 19. The A / D converter 19 performs sampling in synchronization with the clock at a predetermined sampling number m (integer) within a predetermined period in which the frequency is swept. The digital data is sequentially stored and accumulated in the waveform memory 20 in the signal processing unit 21. Then, the display unit 17 as an output unit, based on the output of the waveform memory 20, performs one frequency sweep (or one
Data of a predetermined number of points (N) (for a predetermined time interval) is output and displayed as characteristics of the signal under measurement.

The A / D conversion section 19 is connected to the display section 1
7 is k times the number of predetermined points N per frequency sweep (or per predetermined time interval) (k = 1 or more and m
The output of the detection unit 18 is sampled at a rate of the number of points kN (hereinafter referred to as a sampling point) of the following integer, and digital data is output. And
The digital data is sequentially stored in the waveform memory 20.

A signal processing unit 21 composed of a DSP, a CPU, and the like, based on the digital data stored in the waveform memory 20, uses a horizontal axis (time axis or frequency axis) on the display screen of the display unit 17. An effective value of data corresponding to a sweep time between one point of display data (hereinafter, referred to as a display point) is calculated. That is, the averaging unit 22 provided in the signal processing unit 21 receives the digital data output from the waveform memory 20, averages the digital data at a plurality of sampling points (k), and newly displays the value as one. The data is obtained as point data, and data of a predetermined number of display points (N) per one frequency sweep or one predetermined time interval is output to the display unit 17. The details of the averaging will be described later.

FIG. 2 is a circuit diagram showing the detector 18. The input signal from the VBW filter 16 is input to a positive detection circuit 26 and a negative detection circuit 27, respectively. Each of the detection circuits 26 and 27 is provided with a peak hold circuit, and holds the respective peak value until a reset signal RST is input.
After the reset signal RST is input, the updated peak value is held.

The positive peak value held by the positive detection circuit 26 and the negative detection circuit 27
One of the negative peak values held by the switch 28 is selectively output to the A / D converter 19 by switching the switch 28. Buffers 29a and 29b are provided at the input and output stages of the detector 18, respectively.

The switch 28 is switched at a predetermined cycle based on a clock output from the clock generator 23 of the signal processor 21. Thereby, the reset signal R
A positive peak value or a negative peak value during a period until ST is input is output. Here, the reset signal RST is output in synchronization with the clock of the A / D conversion unit 19, but the signal processing unit 21
Twice the cycle of the clock of the converter 19 (multiplied by N: N = 2)
Output RST-P or RST-N. Thus, the signal input to the detection circuit 18 is always detected as a peak by both the positive detection circuit 26 and the negative detection circuit 27. Note that writing and reading to and from the waveform memory 20 are performed in synchronization with this.

Next, the operation of the above configuration will be described with reference to the time chart of FIG. When the signal waveform (a) output from the VBW 16 is input to the detection unit 18, the positive detection circuit 26 detects and holds the positive peak value of the input signal, and the negative detection circuit 27 outputs the negative peak value of the input signal. Detect and hold the value. As shown in FIG. 3, the positive detection circuit 26 and the negative detection circuit 27 each time the RST-P and RST-N reset signals are input, that is, the DET MODE shown in FIG.
Period of signal (H: POS, L: NEG) period (P in the figure)
The positive peak value and the negative peak value during the period described in OS and NEG) are detected.
As shown, the POS and NEG periods are A / D
This is a cycle obtained by doubling the clock of the conversion unit 19,
Both the OS and NEG peak values are detected.

Each time the clock (AD CLOCK described in FIG. 2B) of the A / D converter 19 is input, the switch 28 switches between the positive detection circuit 26 and the negative detection circuit 2.
7 are alternately switched. As a result, the switch 28 is connected to the positive peak detection circuit 2 as shown in FIG.
6, the positive peak value (the value indicated by a black circle) in the POS period up to that point is output to the A / D converter 19 when the clock of the A / D converter 19 is input. At the time of the next clock, the switch 28 is switched to the negative peak detection circuit 27, and at the time of this clock input, the negative peak value (the value indicated by a white circle) in the NEG period up to that time is output to the A / D converter 19.

The A / D converter 19 A / D converts the alternately input positive peak value and negative input peak value at a predetermined sampling period (the above-mentioned AD CLOCK), and stores the converted values in the corresponding frequency storage area of the waveform memory 20. Store sequentially. The waveform memory 20 stores a plurality of peak values (for example, the predetermined number of display points N = 501) corresponding to the frequency band displayed on the display unit 17, and new peak values are captured by frequency sweeping. At this time, the waveform memory 20 of the corresponding frequency value is updated.

The averaging section 22 calculates the average of the positive peak value and the negative peak value which are alternately captured (POS peak value + NEG peak value).
/ 2. Thus, when the POS peak value is input, the average value with the immediately preceding NEG peak value is calculated,
The average value of the corresponding frequency portion is displayed on the display unit 17 (an average is obtained for every h sampling numbers; h = an integer of 2 or more and m or less). The timing of the display update is performed in the cycle of AD DATA shown in FIG. 3D (the timing at which the pair of the positive peak value and the negative peak value are acquired).

Thus, as shown in the display example of FIG. 4, an average value (solid line) of the positive peak value and the negative peak value (both are indicated by dotted lines) can be displayed on the display unit 17 as in the display example of FIG. become. In the drawing, the horizontal axis indicates the frequency range for a predetermined clock (for example, 501 times) of the A / D converter 19, and the vertical axis indicates the level at each frequency. Then, according to the apparatus having the above configuration, the display of the frequency portion for which the average value is calculated in the unit of obtaining the positive peak value and the negative peak value (POS / NEG display rewriting cycle) is sequentially updated in real time.

Further, the averaging processing unit 22 having the above configuration calculates the average value each time the positive peak value and the negative peak value are acquired, so that the average value can be numerically displayed in real time. It becomes possible. For example, it becomes possible to numerically display the average value of the positive peak value and the negative peak value at the position where the marker M is set on the waveform of FIG.

(Second Embodiment) In the first embodiment, a single A / D converter is switched by using the switch 28 for each clock of the A / D converter 19.
The configuration in which the conversion unit (A / D converter) 19 performs A / D conversion has been described, but the configuration is not limited to this. For example, as shown in FIG. 5, an A / D converter 19a is provided after the positive peak detection circuit 26 and the negative peak detection circuit 27, respectively.
With the configuration provided with 19b, the switch 28 can be dispensed with. With this configuration, the positive peak value and the negative peak value of the input signal can be simultaneously detected. It goes without saying that a single A / D converter having 2CH inputs can be used.

In the above embodiment, the local oscillator 5 has a configuration in which the oscillation frequency is swept (frequency sweep) over a predetermined frequency range by the sweep signal from the sweep control unit 12 in the frequency domain state. In the time domain state, the sweep signal from the sweep control unit 12 is not sent to the local oscillator 5, and the local oscillator 5 is set to a fixed oscillation frequency. In this case, a waveform having the horizontal axis as the time axis and the vertical axis as the signal level is displayed on the display unit 17.

[0032]

According to the first aspect of the present invention, the signal processor averages the positive peak value and the negative peak value of the signal under measurement for every k (an integer of 1 to m) sampling numbers. Since the spectrum is displayed on the display unit as a spectrum waveform, the average value of the positive peak and the negative peak of the measured signal measured in real time can be displayed on the display unit. In addition, the speed of video averaging on display can be increased with a simple configuration. According to the second aspect, any one of a positive peak value, a negative peak value of the signal under measurement, and a spectrum waveform based on an average thereof can be displayed, or at the same time, so that the signal under measurement can be displayed. Analysis can be performed from various viewpoints according to the type.
Further, the positive peak value or the negative peak value of the signal under measurement is alternately switched for each clock by using one A / D converter, and A / D conversion is performed.
A configuration in which the average value of the positive peak value and the negative peak value is obtained for each (an integer of 2 or more and m or less) sampling numbers may be employed. The average value can be obtained in real time. According to the fourth aspect, the detection unit is provided in each of the positive peak detection circuit and the negative peak detection circuit connected in parallel to the input signal path of the signal under measurement, and the positive peak detection circuit and the negative peak detection circuit. And a holding circuit for holding each detected peak value, and the A / D converter is configured to A / D convert outputs of the positive peak detection circuit and the negative peak detection circuit independently of each other. , The peak values can be independently detected by the two parallel systems, and the average value can be processed in real time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a spectrum analyzer of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a detection unit.

FIG. 3 is a timing chart showing the operation of each unit of the apparatus.

FIG. 4 is a diagram showing a display waveform on a display unit.

FIG. 5 is a circuit diagram showing a configuration of a second embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Spectrum analyzer, 5 ... Local oscillator, 6 ... Signal mixer, 7 ... IF filter, 12 ... Sweep control part, 15
... LOG conversion unit, 16 VBW filter, 17 display unit, 18 detection unit, 18a positive peak detection means, 18b negative peak detection means, 19 (19
a, 19b) A / D conversion unit, 20 waveform memory, 21
... Signal processing unit, 22 ... Averaging processing unit, 28 ... Switch.

Claims (4)

[Claims] 1. A receiving section (6) for performing frequency sweep of a signal under measurement at a predetermined period, converting the signal into an intermediate frequency signal, and outputting the intermediate frequency signal, and receiving the intermediate frequency signal and receiving a positive peak value and a negative peak value of the signal under measurement. A detection unit (18) that detects and outputs a value and is reset by a clock; and outputs a digital data by sampling an output of the detection unit in synchronization with the clock at a predetermined sampling number m (integer) within the predetermined period. A / D conversion unit (1)
9) and receiving k (1 or more m
A signal processing unit (21) for calculating and outputting an average value of the positive peak value and the negative peak value for each of the following number of samplings; and a spectrum waveform of the signal under measurement in response to an output of the signal processing unit. And a display unit (17) for displaying as a spectrum analyzer. 2. The display section (17) includes a spectrum waveform based on a positive peak value of the signal under measurement, a spectrum waveform based on a negative peak value of the signal under measurement, and a positive peak value of the signal under measurement. 2. The spectrum analyzer according to claim 1, wherein any one of the spectrum waveforms based on the average value of the negative peak values can be selected or simultaneously displayed. 3. An A / D converter (19) comprising:
A signal processing unit (21), wherein the signal processing unit (21) has a / D converter, and alternately switches a positive peak value or a negative peak value of the signal under measurement detected by the detection unit (18) for each clock to convert the data into digital data. Is h (an integer of 2 or more and m or less)
3. The spectrum analyzer according to claim 1, wherein an average value of the positive peak value and the negative peak value is obtained for each sampling number. 4. The detection section (18) includes: a positive peak detection circuit (26) and a negative peak detection circuit (27) connected in parallel to an input signal path of the signal under measurement; and the positive peak detection circuit. And a holding circuit provided in the negative peak detection circuit to hold each detected peak value. The A / D conversion unit (19) makes the outputs of the positive peak detection circuit and the negative peak detection circuit independent of each other. 3. The spectrum analyzer according to claim 1, wherein the A / D conversion is performed.