1355140 (1) 九、發明說明 【發明所屬之技術領域】 本發明係槪略而言，爲與測定調諧器的特性之裝置有 ' 關，更詳細爲與爲了調整或檢査調諧器，而高速測定調諧 器的特性之裝置有關。 【先前技術】 • 第I圖係表示依據以往技術之測定調諧器的特性之裝 置的功能方塊圖，第2圖係說明依據以往技術之測定調諧 器的特性之手法的流程圖。如第1圖所示般，以往的裝置 係具備：CPU1、及PLL頻率合成器2、及線性檢波手段 3、及對數檢波手段 4、及 VSWR(Voltage Standing Wave Ratio :電壓駐波比率）測定手段5、及開關6、及A/D轉 換器7。 首先，CPU1係將調諧頻率（通道頻率）設定爲特定 ® 頻率（例如，801.25MHz )所需之控制訊號輸出至調諧器 1〇(步驟201)。調諧器10因應控制訊號，而將調諧頻率 設定爲特定頻率。調諧器10進一步產生具有把調諧頻率 與中間頻率（例如，43.5MHz )予以相加的頻率（局部頻 率（例如，844.75MHz))的訊號。 (線性測定） CPU]係設定開關6，使得開關6從線性檢波手段3 輸入具有中間頻率之訊號的電壓，且將其輸出至A/D轉換 -4- ⑧ (2) 1355140 器7 (步驟202 ) » 接著，CPU 1將把掃視頻率（Fs)設定爲第1頻率 (初期頻率）（Fsl)(例如，78 7.75MHz)所需之第1控制 訊號輸出至PLL頻率合成器2(步驟203) "PLL頻率合 成器2因應第1控制訊號，而產生具有第1頻率（Fsl) 之RF訊號，將其輸出至調諧器10及VS WR測定手段5。 調諧器10係從PLL頻率合成器2輸入具有第1頻率 ® (Fsl)之 RF訊號，並將RF訊號的反射訊號輸出至 VSWR測定手段5。調諧器10將具有第1頻率（Fsl)之 RF訊號與具有局部頻率之訊號加以混合，而生成混合訊 號。調諧器10進一步藉由對應中間頻率之濾波器而將混 合訊號加以濾波，來生成具有中間頻率之訊號。調諧器1 0 將具有中間頻率之訊號輸出至線性檢波手段3及對數檢波 手段4。 線性檢波手段3係從調諧器1〇輸入具有中間頻率之 ® 訊號，來檢測具有中間頻率之訊號的電壓。線性檢波手段 3係將具有中間頻率之訊號的電壓輸出至開關6。開關6 係從線性檢波手段3輸入具有中間頻率之訊號的電壓，將 其輸出至A/D轉換器7。A/D轉換器7則將具有中間頻率， 之訊號的電壓轉換爲數位値，而輸出至CPU 1。CPU1將第 1控制訊號輸出至PLL頻率合成器2後，於經過特定的掃 視間隔（△ ts)(例如，3 // sec)前，從A/D轉換器7取入 數位値’將數位値及第1頻率（Fsl )當成第1線性測定値而 加以記憶（步驟2 0 3 )。 (3) 1355140 CPU1判定掃視頻率（Fs)是否與第η頻率（最終頻 率）（F sn )(例如，8 1 4 · 7 5 ΜΗ ζ)相等或比其小（步驟 2 04 )。在掃視頻率（Fs)與第n頻率（Fsn)相等或比其小 時，CPU1判定掃視沒有結束。在掃視頻率（Fs)不與第η 頻率（Fsn )相等或不比其小時，CPU1判定掃視已結束。 在掃視頻率（Fs)與第η頻率（Fsn )相等或比其小時， CPU1每隔特定的掃視間隔（△ ts )，將掃視頻率（Fs)只增 ® 加特定的頻率（AFs)(例如，〇.〇225MHz)(步驟203)。 即CPU 1從輸出第1控制訊號時起，於只經過特定的掃視 間隔（△ ts )時，將把掃視頻率（Fs)設定爲第2頻率 C Fs2 = FsI + A Fs )所需之第2控制訊號輸出至PLL頻率合 成器2"PLL頻率合成器2生成具有第2頻率（Fs2)之RF 訊號，調諧器10將具有第2頻率之RF訊號與具有局部頻 率之訊號加以混合，之後，藉由對應中間頻率之濾波器， 而生成具有中間頻率之訊號。線性檢波手段3檢測出具有 ® 中間頻率之訊號的電壓，開關6將具有中間頻率之訊號的 電壓輸出至A/D轉換器7，A/D轉換器7將具有中間頻率 之訊號的電壓轉換爲數位値，而輸出至CPU1。CPU1將第 2控制訊號輸出至PLL頻率合成器2後，於經過特定的掃 視間隔（△ ts )前，從A/D轉換器7取入數位値，將數位 値及第2頻率（Fs2)當成第2線性測定値而加以記憶（步驟 203 ) ° η 如此，PLL頻率合成器2生成具有第1頻率051)~第 頻率（Fsn)之RF訊號，調諧器〗〇生成具有對應的中1355140 (1) Nine, the invention belongs to the technical field of the invention. The present invention is, in a nutshell, a device for measuring the characteristics of a tuner, and more specifically for high-speed measurement in order to adjust or inspect a tuner. The device of the characteristics of the tuner is related. [Prior Art] Fig. 1 is a functional block diagram showing a device for measuring characteristics of a tuner according to the prior art, and Fig. 2 is a flow chart showing a method for measuring characteristics of a tuner according to the prior art. As shown in Fig. 1, the conventional apparatus includes a CPU 1, a PLL frequency synthesizer 2, a linear detecting means 3, a logarithmic detecting means 4, and a VSWR (Voltage Standing Wave Ratio) measuring means. 5. Switch 6 and A/D converter 7. First, the CPU 1 outputs a control signal required to set the tuning frequency (channel frequency) to a specific ® frequency (for example, 801.25 MHz) to the tuner 1 (step 201). The tuner 10 sets the tuning frequency to a specific frequency in response to the control signal. The tuner 10 further generates a signal having a frequency (local frequency (e.g., 844.75 MHz)) for adding the tuning frequency to the intermediate frequency (e.g., 43.5 MHz). (Linear measurement) The CPU] sets the switch 6 so that the switch 6 inputs the voltage having the signal of the intermediate frequency from the linear detecting means 3, and outputs it to the A/D conversion -4- 8 (2) 1355140 device 7 (step 202) Then, the CPU 1 outputs the first control signal required to set the scan rate (Fs) to the first frequency (initial frequency) (Fsl) (for example, 78 7.75 MHz) to the PLL frequency synthesizer 2 (step 203). The PLL frequency synthesizer 2 generates an RF signal having a first frequency (Fs1) in response to the first control signal, and outputs it to the tuner 10 and the VS WR measuring means 5. The tuner 10 inputs an RF signal having a first frequency ® (Fsl) from the PLL frequency synthesizer 2, and outputs a reflected signal of the RF signal to the VSWR measuring means 5. The tuner 10 mixes the RF signal having the first frequency (Fs1) with the signal having the local frequency to generate a mixed signal. The tuner 10 further filters the mixed signal by a filter corresponding to the intermediate frequency to generate a signal having an intermediate frequency. The tuner 10 outputs a signal having an intermediate frequency to the linear detecting means 3 and the logarithmic detecting means 4. The linear detection means 3 inputs a signal having an intermediate frequency from the tuner 1 to detect a voltage having an intermediate frequency signal. The linear detection means 3 outputs a voltage having a signal of an intermediate frequency to the switch 6. The switch 6 inputs a voltage having a signal of an intermediate frequency from the linear detecting means 3, and outputs it to the A/D converter 7. The A/D converter 7 converts the voltage having the intermediate frequency, the signal, into a digital volume, and outputs it to the CPU 1. After outputting the first control signal to the PLL frequency synthesizer 2, the CPU 1 takes in the digits from the A/D converter 7 before passing through a specific scanning interval (Δ ts) (for example, 3 // sec). And the first frequency (Fsl) is stored as the first linear measurement (step 2 0 3 ). (3) 1355140 CPU1 determines whether the sweep rate (Fs) is equal to or smaller than the nth frequency (final frequency) (F sn ) (for example, 8 1 4 · 7 5 ΜΗ ζ) (step 2 04). When the scan video rate (Fs) is equal to or smaller than the nth frequency (Fsn), the CPU 1 determines that the panning is not ended. When the scan video rate (Fs) is not equal to or less than the nth frequency (Fsn), the CPU 1 determines that the panning has ended. When the sweep rate (Fs) is equal to or smaller than the nth frequency (Fsn), the CPU 1 increments the scan rate (Fs) by a specific frequency (AFs) every specific scan interval (Δ ts ) (for example, 〇.〇 225 MHz) (step 203). That is, the CPU 1 sets the scan rate (Fs) to the second frequency C Fs2 = FsI + A Fs when the specific scan interval (Δ ts ) is elapsed from the time when the first control signal is output. The control signal output to the PLL frequency synthesizer 2 " PLL frequency synthesizer 2 generates an RF signal having a second frequency (Fs2), and the tuner 10 mixes the RF signal having the second frequency with a signal having a local frequency, and then borrows A signal having an intermediate frequency is generated by a filter corresponding to the intermediate frequency. The linear detecting means 3 detects the voltage having the signal of the intermediate frequency, and the switch 6 outputs the voltage having the signal of the intermediate frequency to the A/D converter 7, and the A/D converter 7 converts the voltage having the signal of the intermediate frequency into Digital digits are output to CPU1. After outputting the second control signal to the PLL frequency synthesizer 2, the CPU 1 takes in the digital 値 from the A/D converter 7 before passing through the specific scanning interval (Δ ts ), and takes the digital 値 and the second frequency (Fs2) as The second linear measurement is memorized and stored (step 203) ° η. Thus, the PLL frequency synthesizer 2 generates an RF signal having a first frequency 051) to a first frequency (Fsn), and the tuner is generated with a corresponding medium.
-6- (4) 1355140 間頻率之訊號，CPU1將第1頻率（Fsl)〜第η頻率（Fsn) 及與其對應之數位値當成第1線性測定値〜第η線性測定 値而加以記憶（步驟203 )。第3圖係說明具有藉由第1 圖之CPU1及PLL頻率合成器2所生成的第1頻率（Fsl)~ 第η頻率（Fsn )之RF訊號所需之圖。如第3圖所示般， RF訊號的頻率，係隨時間而增加。 β (對數測定） 在步驟2 04中，於掃視頻率（Fs)不與第η頻率（Fsn) 相等或不比其小時，CPU1判定掃視已經結束。CPU 1設定 開關6，使得開關6從對數檢波手段4輸入將具有中間頻 率之訊號的電壓予以對數轉換之對數電壓，並將其輸出至 A/D轉換器7 (步驟205 )。 與步驟203及步驟204相同，CPU1生成將掃視頻率 (Fs)設定爲第1頻率〜第η頻率所需之第1控制訊號〜第 ® η控制訊號，PLL頻率合成器2生成具有第1頻率（Fsl)〜 第η頻率（Fsn)之RF訊號，調諧器10生成具有對應的 中間頻率之訊號，對數檢波手段4檢測出具有對應的中間 頻率之訊號的對數但壓，A/D轉換器7輸出對應之對數電 壓的數位値，CPU 1將第1頻率（Fsl)〜第η頻率（Fsn)及 與其對應之數位値當成第I對數測定値〜第η對數測定値 而加以記億（步驟206及步驟207 )。 (VSWR測定） (5) 1355140 在步驟207中，於掃視頻率（Fs)不與第η頻率（Fsn) 相等或不比其小時，CPU1判定掃視已經結束》CPU1設定 開關6，使得開關6從VSWR測定手段5輸入表示訊號及 從其之反射訊號所求得之電壓駐波比的電壓，將其輸出至 A/D轉換器7 (步驟208 )。另外，電壓駐波比係電壓駐 波的極大値與極小値之比。 與步驟203及步驟204相同，生成將掃視頻率（Fs)設 ® 定爲第1頻率〜第η頻率所需之第1控制訊號〜第η控制 訊號，PLL頻率合成器2生成具有第1頻率（Fsl)〜第η頻 率（Fsn )之訊號，VSWR測定手段5檢測出表示對應之 電壓駐波比的電壓，A/D轉換器7將表示對應之電壓駐波 比之電壓的數位値予以輸出，CPU1將第1頻率（Fsl)〜第η 頻率（Fsn)及與其對應之數位値當成第1 VSWR測定値〜 第nVSWR測定値加以記憶（步驟209及步驟210)。 在步驟210中，於掃視頻率（Fs)不與第n頻率（Fsn) ® 相等或不比其小時，CPU 1判定掃視已經結束。 (測定値之表示） 作爲調諧器的特性之線性測定、對數測定及VSWR測 定一結束時，CPU 1生成描繪第1線性測定値〜第η線性 測定値、第1對數測定値〜第η對數測定値及第1 VSWR 測定値〜第nVSWR測定値所需之控制資料，將其輸出至 顯示器。第4圖係表示這些測定値被顯示於顯示器之例。 第4圖中，線性測定値、對數測定値及VSWR測定値，係 -8- (6) 1355140 個別以直線、虛線、1點虛線所表示。使用者可以一面所 顯示的調諧器的特性，而一面調整或檢查調諧器。 【發明內容】 [發明之揭示] [發明所欲解決之課題] 依據以往技術之測定調諧器的特性之手法，係對1個 調諧頻率（通道頻率）來實行線性測定、對數測定及 • VSWR測定，所以，需要進行如第3圖之訊號的掃視共3 次。換言之，爲了調整或檢查調諧器，使用者需要對於1 個調諧頻率，等待訊號的3次掃視。 本發明之目的在於縮短調整或檢查調諧器的時間。本 發明之另外一個目的，係在於提供高速測定調諧器的特性 之裝置。本發明之其它目的，藉由參照以下說明之發明的 實施形態、及說明書所附之圖面及申請專利範圍，該業者 理應可以容易理解。 [解決課題所需之手段] 依據本發明之測定調諧器的特性之裝置，其特徵爲具 備：從起始頻率（Fsl)至最終頻率（Fsn)來掃視RF訊號 的頻率（Fs)，將所被掃視之RF訊號輸出至調諧器 (1〇)之手段（1、2);及從調諧器（10)輸入具有中間 頻率的·訊號，而檢測具有中間頻率的訊號之電壓的手段 (3):及從調諧器（10)輸入具有中間頻率之訊號，而 檢測將具有中間頻率的訊號之電壓予以對數轉換之對數電 -9- ⑧ (7) (7)1355140 壓的手段（4)，及從前述手段（1、2)輸入前述RF訊 號’且輸入前述RF訊號的反射訊號，而檢測表示電壓駐 波比之電壓的手段（5):及於RF訊號的頻率（Fs)從起始 頻率（Fsl )至最終頻率（Fsn)被掃視之第1期間，將具有 中間頻率的訊號之電壓、將具有中間頻率的訊號之電壓予 以對數轉換之對數電壓、及表示電壓駐波比之電壓予以取 入之手段（6、 7、 81、 82、 83、 1) » 前述取入手段係具備：輸入具有中間頻率的訊號之電 壓、將具有中間頻率的訊號之電壓予以對數轉換之對數電 壓 '及表示電壓駐波比之電壓，且於前述第1期間，將切 換爲具有中間頻率的訊號之電壓、將具有中間頻率的訊號 之電壓予以對數轉換之對數電壓、及表示電壓駐波比之電 壓中之其中一種而加以輸出予以重複之手段（6、1):及 將具有中間頻率的訊號之電壓、將具有中間頻率的訊號之 電壓予以對數轉換之對數電壓、及表示電壓駐波比之電壓 中之其中一種轉換爲數位値而取入之手段（7、Π 。 或前述取入手段係具備：輸入具有中間頻率的訊號之 電壓，且轉換爲數位値而加以取入之手段（81、1):及 輸入將具有中間頻率的訊號之電壓予以對數轉換之對數電 壓，且轉換爲數位値而加以取入之手段（82、1 ):及輸 入表示電壓駐波比之電壓，且轉換爲數位値而加以取入之 手段（83、1 )。 依據本發明之測定調諧器的特性之裝置，其係具備： CPU(l)、及PLL頻率合成器（2 )、及線性檢波手段 -10- ⑧ (8) 1355140 (3)、及對數檢波手段（4)、及 VSWR測定手段 (5 )、及開關（6 )、及A/D轉換器（7) 。CPU(l)係於-6- (4) Signal of frequency between 1355140, CPU1 memorizes the first frequency (Fsl) to the nth frequency (Fsn) and the corresponding digital digits as the first linear measurement 値 to the η linear measurement ( (step 203). Fig. 3 is a view showing the need for RF signals having the first frequency (Fsl) to the nth frequency (Fsn) generated by the CPU 1 and the PLL frequency synthesizer 2 of Fig. 1 . As shown in Figure 3, the frequency of the RF signal increases over time. β (logarithm measurement) In step 2 04, when the scan rate (Fs) is not equal to or less than the nth frequency (Fsn), the CPU 1 determines that the panning has ended. The CPU 1 sets the switch 6 so that the switch 6 inputs the logarithmic voltage which logarithmically converts the voltage having the signal of the intermediate frequency from the logarithmic detecting means 4, and outputs it to the A/D converter 7 (step 205). Similarly to steps 203 and 204, the CPU 1 generates a first control signal to a +n control signal required to set the scan rate (Fs) to the first to nth frequencies, and the PLL frequency synthesizer 2 generates the first frequency ( Fsl) ~ RF signal of the nth frequency (Fsn), the tuner 10 generates a signal having a corresponding intermediate frequency, and the logarithmic detection means 4 detects the logarithm of the signal having the corresponding intermediate frequency but the voltage, the output of the A/D converter 7 Corresponding to the digit 値 of the logarithmic voltage, the CPU 1 counts the first frequency (Fsl) to the nth frequency (Fsn) and the corresponding digital digits as the first logarithmic measurement 値 to the n-th logarithm measurement (step 206 and Step 207). (VSWR measurement) (5) 1355140 In step 207, when the scan rate (Fs) is not equal to or less than the nth frequency (Fsn), the CPU 1 determines that the panning has ended. CPU1 sets the switch 6, so that the switch 6 is determined from the VSWR. The means 5 inputs a voltage indicating the signal and the voltage standing wave ratio obtained from the reflected signal thereof, and outputs it to the A/D converter 7 (step 208). In addition, the voltage standing wave ratio is the ratio of the maximum 値 to the minimum 电压 of the voltage standing wave. Similarly to steps 203 and 204, the first control signal to the nth control signal required to set the scan rate (Fs) to the first frequency to the nth frequency are generated, and the PLL frequency synthesizer 2 generates the first frequency ( Fsl) to the signal of the nth frequency (Fsn), the VSWR measuring means 5 detects the voltage indicating the corresponding voltage standing wave ratio, and the A/D converter 7 outputs the digital value 电压 indicating the voltage of the corresponding voltage standing wave ratio. The CPU 1 memorizes the first frequency (Fsl) to the nth frequency (Fsn) and the corresponding digital digits as the first VSWR measurement 値 to the nVSWR measurement ( (steps 209 and 210). In step 210, when the scan rate (Fs) is not equal to or less than the nth frequency (Fsn) ® , the CPU 1 determines that the pan has ended. (Representation of measurement )) When the linear measurement, the logarithmic measurement, and the VSWR measurement of the characteristics of the tuner are completed, the CPU 1 generates the first linear measurement 値 to the n-th linear measurement 値, and the first logarithmic measurement 値 to the n-th log determination.控制 and the control data required for the first VSWR measurement 値 ~ nVSWR measurement ,, and output it to the display. Fig. 4 shows an example in which these measurements are displayed on a display. In Fig. 4, linear measurement 値, logarithmic measurement 値 and VSWR measurement 値, -8- (6) 1355140 are indicated by straight lines, broken lines, and 1-dotted lines. The user can adjust or check the tuner while displaying the characteristics of the tuner. [Disclosure of the Invention] [Disclosure of the Invention] [Problems to be Solved by the Invention] According to the technique of measuring the characteristics of a tuner in the prior art, linear measurement, logarithmic measurement, and VSWR measurement are performed on one tuning frequency (channel frequency). Therefore, a sweep of the signal as shown in Figure 3 is required for 3 times. In other words, in order to adjust or check the tuner, the user needs to wait for 3 sweeps of the signal for 1 tuning frequency. It is an object of the invention to reduce the time to adjust or check the tuner. Another object of the present invention is to provide an apparatus for measuring the characteristics of a tuner at a high speed. Other objects of the present invention will be readily understood by reference to the embodiments of the invention described hereinafter and the accompanying drawings and claims. [Means for Solving the Problem] The apparatus for measuring characteristics of a tuner according to the present invention is characterized in that it has a frequency (Fs) for scanning an RF signal from a start frequency (Fsl) to a final frequency (Fsn). Means for outputting the scanned RF signal to the tuner (1, 2); and inputting a signal having an intermediate frequency from the tuner (10), and detecting the voltage of the signal having the intermediate frequency (3) : and inputting a signal having an intermediate frequency from the tuner (10), and detecting a logarithmic conversion of the voltage of the signal having the intermediate frequency by a logarithmic electrical signal - 9 - 8 (7) (7) 1355140 (4), and Inputting the RF signal ' from the foregoing means (1, 2) and inputting the reflected signal of the RF signal, and detecting the voltage representing the voltage standing wave ratio (5): and the frequency (Fs) of the RF signal from the starting frequency (Fsl) to the final frequency (Fsn) being scanned for the first period, the voltage of the signal having the intermediate frequency, the logarithmic voltage of the logarithmically converted voltage of the signal having the intermediate frequency, and the voltage representing the voltage standing wave ratio are taken Means of entry (6, 7, 81, 82, 83, 1) » The above-mentioned means for taking in is: a voltage for inputting a signal having an intermediate frequency, a logarithmic voltage for logarithmically converting a voltage of a signal having an intermediate frequency, and a voltage representing a voltage standing wave ratio, and the first During the period, switching to a signal having an intermediate frequency, a logarithmic voltage of a logarithmic conversion of a voltage having an intermediate frequency, and a voltage representing a voltage standing wave ratio are outputted and repeated (6. 1): and means for taking the voltage of the signal having the intermediate frequency, the logarithmic voltage of the logarithmically converted voltage of the signal having the intermediate frequency, and the voltage representing the voltage standing wave ratio into one digit. 7. The above-mentioned means of taking-in means having the means of inputting a voltage having a signal of an intermediate frequency and converting it into a digit and taking it in (81, 1): and inputting a logarithm of the voltage of the signal having the intermediate frequency a means of converting the logarithmic voltage and converting it to a digital ( (82, 1): and inputting a voltage representing a voltage standing wave ratio, and The means for measuring the characteristics of the tuner according to the present invention includes: a CPU (1), a PLL frequency synthesizer (2), and a linear detection means. -10- 8 (8) 1355140 (3), and logarithmic detection means (4), and VSWR measurement means (5), and switch (6), and A/D converter (7). CPU(l) is attached to
每一特定的掃視間隔（△ ts )產生控制訊號，將第1控制 '訊號〜第η控制訊號輸出至PLL頻率合成器（2 ) 。PLL 頻率合成器（2 )係因應第1控制訊號〜第η控制訊號， 而生成具有從第I頻率（Fsl)〜第η頻率（Fsn)爲止被掃視 之頻率（Fs)的RF訊號，將前述RF訊號輸出至調諧器 ® (10)。線性檢波手段（3)係從調諧器（10)輸入具有 對應前述RF訊號的中間頻率之訊號，而檢測具有中間頻 率的訊號之電壓。對數檢波手段（4)係從調諧器（1〇) 輸入具有對應前述RF訊號之中間頻率的訊號，而檢測將 具有中間頻率的訊號之電壓予以對數轉換之對數電壓。 VSWR測定手段（5 )係從PLL頻率合成器（2)輸入前述 RF訊號，且由調諧器（10)輸入前述RF訊號的反射訊 號，而檢測表示電壓駐波比之電壓。開關（6)係從線性 ® 檢波手段（3)輸入具有中間頻率的訊號之電壓，且從對 數檢波手段（4)輸入將具有中間頻率的訊號之電壓予以 對數轉換之對數電壓，並從VSWR測定手段（5 )輸入表 示電壓駐波比之電壓。CPU(l)係於每一特定的開關間隔 (Δη)來設定開關（6)。開關（6)係於每一特定的開 關間隔（Δη) ’切換爲具有中間頻率的訊號之電壓、將 具有中間頻率的訊號之電壓予以對數轉換之對數電壓、及 表示電壓駐波比之電壓中之其中一種而將其輸出至A/D轉 換器（7 ) 。A/D轉換器（7 )係將從開關（6 )所輸出之 -11 - (9) 1355140 訊號轉換爲數位値，而輸出至CPU(l)。CPU(l)係於RF訊 號的頻率（Fs)從起始頻率（Fsl )至最終頻率（Fsn)被掃視 之第1期間，將具有中間頻率的訊號之電壓的數位値、將 具有中間頻率的訊號之電壓予以對數轉換之對數電壓的數 位値、及表示電壓駐波比之電壓的數位値從 A/D轉換器 (7 )加以取入。 依據本發明之測定調諧器的特性之裝置，係也可以具 ® 備：0卩1；(1)、及PLL頻率合成器（2)、及線性檢波手段 (3)、及對數檢波手段（4)、及 VSWR測定手段 (5 )、及第1 A/D轉換器（81)、、及第2A/D轉換器 (82 )、及第 3A/D轉換器（83 )。第 1A/D轉換器 (81)係從線性檢波手段（3)輸入具有中間頻率的訊號 之電壓。第2A/D轉換器（82)係從對數檢波手段（4)輸 入將具有中間頻率的訊號之電壓予以對數轉換之對數電壓 電力。第3A/D轉換器（83 )係從VSWR測定手段（5 )輸 ® 入表示電壓駐波比之電壓。CPU(l)係於RF訊號的頻率（FS) 從起始頻率（Fsl)至最終頻率（Fsn)被掃視之第1期間， 從第1 A/D轉換器（81)取入具有中間頻率的訊號之電壓 的數位値、從第2A/D轉換器（82)取入將具有中間頻率 的訊號之電壓予以對數轉換之對數電壓的數位値、從第 3A/D轉換器（83)取入表示電壓駐波比之電壓的數位 値。 【實施方式】 -12- 1355140 do) 以下說明之發明的實施形態，係表示申請專利範圍所 記載之發明的例示性實施形態，本發明不應被限定於以下 之實施形態。 (第1實施形態） 依據本發明之測定調諧器的特性之裝置，係和以往的 裝置相同，爲具備：CPU(l)、及PLL頻率合成器（2)、 及線性檢波手段（3)、及對數檢波手段（4)、及VSWR 測定手段（5 )、及開關（6 )、及A/D轉換器（7 )。但 是，依據本發明之CPU 1及開關6的動作，係具有與以往 的動作不同之部份。第5圖係說明測定調諧器的特性之手 法所需之流程圖，第6圖係說明對於被掃視之訊號，將測 定値加以取入之時序所需之圖。 首先，CPU 1將把調諧頻率（通道頻率）設定爲特定 頻率所需之控制訊號輸出至調諧器1〇(步驟50 1)。調諧 器1〇因應控制訊號，將調諧頻率設定爲特定頻率。調諧 器10進一步生成具有將調諧頻率與中間頻率予以相加之 頻率（局部頻率）的訊號。 接著，CPU1將把掃視頻率（Fs)設定爲第1頻率（起 始頻率）（Fsl )所需之第1控制訊號輸出至PLL頻率合 成器2 (步驟5 02 ) 。PLL頻率合成器2因應第1控制訊 號，而生成具有第1頻率（Fsl)之訊號，並將其輸出至 調諧器10及VSWR測定手段5。調諧器10從PLL頻率合 成器2輸入具有第]頻率（Fs〗）之訊號，並將訊號的反 -13- ⑧ (11) 1355140 射訊號輸出至VSWR測定手段5。調諧器10將具有第1 _ 頻率（Fsl)之訊號與具有局部頻率之訊號加以混合，而 生成混合訊號。調諧器〗〇進一步藉由對應中間頻率之據 波器而將混合訊號加以濾波，而生成具有中間頻率之訊 號。調諧器10將具有中間頻率之訊號輸出至線性檢波手 段3及對數檢波手段4。 線性檢波手段3從調諧器10輸入具有中間頻率之訊 ® 號，而檢測出具有中間頻率之訊號的電壓。線性檢波手段 3將具有中間頻率之訊號的電壓輸出至開關6» 對數檢波手段4從調諧器10輸入具有中間頻率之訊 號，檢測出將具有中間頻率之訊號的電壓加以對數轉換之 對數電壓。線性檢波手段3將把具有中間頻率之訊號的電 壓予以對數轉換之對數電壓輸出至開關6。VSWR測定手 段5係從PLL頻率合成器2輸入具有第1頻率（Fsl)之 .訊號，從調諧器1〇輸入具有第1頻率（Fsl)之訊號的反 ® 射訊號。VSWR測定手段5從訊號及其之反射訊號來檢測 出表示電壓駐波比之電壓。VSWR測定手段5將表示電壓 駐波比之電壓輸出至開關6。 在將第1控制訊號輸出至PLL頻率合成器2時， CPU1係將開關6加以設定，其結果爲：開關6從線性檢 波手段3輸入具有中間頻率之訊號的電壓，將其輸出至 A/D轉換器7 (步驟502 ) 。A/D轉換器7將具有中間頻 率之訊號的電壓轉換爲數位値，而輸出至CPU 1。CPU 1在 設定完開關後，於經過特定的切換間隔（△ tt )(例如，1 -14- (12) 1355140Each specific scanning interval (Δ ts ) generates a control signal, and outputs the first control 'signal to nth control signal to the PLL frequency synthesizer (2). The PLL frequency synthesizer (2) generates an RF signal having a frequency (Fs) to be swept from the first frequency (Fsl) to the nth frequency (Fsn) in response to the first control signal to the nth control signal. The RF signal is output to the Tuner® (10). The linear detecting means (3) detects a signal having an intermediate frequency from the tuner (10) by inputting a signal having an intermediate frequency corresponding to the RF signal. The logarithmic detection means (4) inputs a signal having an intermediate frequency corresponding to the RF signal from a tuner (1), and detects a logarithmic voltage which is logarithmically converted by a voltage having a signal of an intermediate frequency. The VSWR measuring means (5) inputs the RF signal from the PLL frequency synthesizer (2), and the tuner (10) inputs the reflected signal of the RF signal to detect the voltage indicating the voltage standing wave ratio. The switch (6) inputs the voltage of the signal having the intermediate frequency from the linearity detection means (3), and inputs the logarithmic voltage of the signal having the intermediate frequency from the logarithmic detection means (4), and determines the logarithmic voltage from the VSWR. Means (5) inputs a voltage representing a voltage standing wave ratio. The CPU (1) sets the switch (6) for each specific switching interval (Δη). The switch (6) is switched between a voltage of a signal having an intermediate frequency at each specific switching interval (Δη), a logarithmic voltage of a logarithmically converting a voltage of a signal having an intermediate frequency, and a voltage representing a voltage standing wave ratio. One of them is output to the A/D converter (7). The A/D converter (7) converts the -11 - (9) 1355140 signal output from the switch (6) into a digital 値 and outputs it to the CPU (1). The CPU(1) is in the first period during which the frequency (Fs) of the RF signal is swept from the start frequency (Fsl) to the final frequency (Fsn), and the digital value of the voltage of the signal having the intermediate frequency will have an intermediate frequency. The voltage of the signal is logarithmically converted to the logarithmic voltage and the digital 値 representing the voltage standing wave ratio is taken from the A/D converter (7). The apparatus for measuring the characteristics of the tuner according to the present invention may also be equipped with: 0卩1; (1), and PLL frequency synthesizer (2), and linear detection means (3), and logarithmic detection means (4) And the VSWR measuring means (5), the first A/D converter (81), the second A/D converter (82), and the third A/D converter (83). The first A/D converter (81) inputs a voltage of a signal having an intermediate frequency from the linear detecting means (3). The second A/D converter (82) receives a logarithmic voltage power that logarithmically converts a voltage of a signal having an intermediate frequency from a logarithmic detection means (4). The third A/D converter (83) is input from the VSWR measuring means (5) to a voltage indicating a voltage standing wave ratio. The CPU(1) is based on the frequency (FS) of the RF signal from the start frequency (Fsl) to the final frequency (Fsn) being scanned for the first period, and the first A/D converter (81) is taken in with the intermediate frequency. The digit 値 of the voltage of the signal is taken from the second A/D converter (82) by the digit 値 of the logarithmic voltage of the logarithmically converted voltage of the signal having the intermediate frequency, and is taken in from the third A/D converter (83). The digital 値 of the voltage of the voltage standing wave ratio. [Embodiment] -12- 1355140 do) The embodiment of the invention described below is an exemplary embodiment of the invention described in the claims, and the invention is not limited to the following embodiments. (First Embodiment) The apparatus for measuring the characteristics of the tuner according to the present invention is similar to the conventional apparatus, and includes a CPU (1), a PLL frequency synthesizer (2), and a linear detecting means (3). And logarithmic detection means (4), and VSWR measuring means (5), and switch (6), and A/D converter (7). However, the operations of the CPU 1 and the switch 6 according to the present invention have different parts from the conventional operations. Fig. 5 is a flow chart showing the method required to measure the characteristics of the tuner, and Fig. 6 is a view showing the timing required for the timing of the measurement to be taken for the signal to be swept. First, the CPU 1 outputs a control signal required to set the tuning frequency (channel frequency) to a specific frequency to the tuner 1 (step 50 1). The tuner 1 sets the tuning frequency to a specific frequency in response to the control signal. The tuner 10 further generates a signal having a frequency (local frequency) at which the tuning frequency is added to the intermediate frequency. Next, the CPU 1 outputs the first control signal required to set the scan rate (Fs) to the first frequency (starting frequency) (Fsl) to the PLL frequency synthesizer 2 (step 5 02). The PLL frequency synthesizer 2 generates a signal having the first frequency (Fs1) in response to the first control signal, and outputs it to the tuner 10 and the VSWR measuring means 5. The tuner 10 inputs a signal having a frequency [Fs] from the PLL frequency synthesizer 2, and outputs a signal of the inverse -13-8 (11) 1355140 of the signal to the VSWR measuring means 5. The tuner 10 mixes the signal having the 1st frequency (Fsl) with the signal having the local frequency to generate a mixed signal. The tuner further filters the mixed signal by means of a data filter corresponding to the intermediate frequency to generate a signal having an intermediate frequency. The tuner 10 outputs a signal having an intermediate frequency to the linear detecting means 3 and the logarithmic detecting means 4. The linear detecting means 3 inputs a signal having an intermediate frequency from the tuner 10, and detects a voltage having a signal of an intermediate frequency. The linear detecting means 3 outputs a voltage having an intermediate frequency signal to the switch 6» The logarithmic detecting means 4 inputs a signal having an intermediate frequency from the tuner 10, and detects a logarithmic voltage which logarithmically converts a voltage having a signal having an intermediate frequency. The linear detecting means 3 outputs a logarithmic voltage of a logarithmic converted voltage of a signal having an intermediate frequency to the switch 6. The VSWR measurement section 5 inputs a signal having a first frequency (Fs1) from the PLL frequency synthesizer 2, and inputs a reverse signal of a signal having a first frequency (Fsl) from the tuner 1 . The VSWR measuring means 5 detects the voltage representing the voltage standing wave ratio from the signal and its reflected signal. The VSWR measuring means 5 outputs a voltage indicating the voltage standing wave ratio to the switch 6. When the first control signal is output to the PLL frequency synthesizer 2, the CPU 1 sets the switch 6. As a result, the switch 6 inputs a voltage having an intermediate frequency signal from the linear detecting means 3, and outputs it to the A/D. Converter 7 (step 502). The A/D converter 7 converts the voltage having the signal of the intermediate frequency into a digital volume and outputs it to the CPU 1. CPU 1 passes a specific switching interval (△ tt ) after setting the switch (for example, 1 -14- (12) 1355140
Msec)前，從A/D轉換器7將數位値取入，將數位値及第 F /IV 率 頻 驟 步 憶 記 以 加 而 値 定 測 性 線 第 成 當 於設定完開關後，在經過特定的切換間隔（Δπ) 時’ CPU 1再度設定開關6,其結果爲：開關6從對數檢 波手段4輸入將具有中間頻率之訊號的電壓予以對數轉換 之對數電壓，將其輸出至A/D轉換器7(步驟5 02 )。 ® A/D轉換器7將把具有中間頻率之訊號的電壓予以對數轉 換之對數電壓轉換爲數位値，而輸出至CPU1。CPU1於再 度設定開關後，在經過特定的切換間隔（ΔΠ)前，從 A/D轉換器7將數位値加以取入，把數位値及第1頻率 (Fsl )當成第1對數測定値而加以記憶（步驟502 )。 於再度設定完開關後，在經過特定的切換間隔（ △ tt )時，CPU 1再度設定開關6，其結果爲：開關6從 VSWR測定手段5輸入表示從訊號及其之反射訊號所求得 B 之電壓駐波比的電壓，將其輸出至 A/D轉換器7(步驟 502 ) 。A/D轉換器7將表示電壓駐波比之電壓轉換爲數 位値，而輸出至CPU 1。CPU 1於再度設定完開關後，於經 過特定的切換間隔（ΔΠ)前，從A/D轉換器7將數位値 予以取入，把數位値及第1頻率（Fsl)當成第1VSWR測 定値而加以記憶（步驟502) ^ 如此，CPU1於每一特定的切換間隔（△ tt )，設定開 關6，其結果爲：開關6係以線性檢波手段3、對數檢波 手段4及V S WR測定手段5之順序來切換開關6之輸入 -15- (13) (13)1355140 (參照第6圖）。另外，開關6的輸入一被切換時，則 CPU 1從A/D轉換器7將數位値加以取入。因此，CPU丨係 以線性測定値、對數測定値及VSWR測定値之順序來讀取 數位値（參照第6圖）。 CPU1判定掃視頻率（Fs)是否與第n頻率（最終頻 率）（Fsn)相等或比其小（步驟5 03 )。於掃視頻率（Fs) 和第η頻率（Fsn )相等或比其小時，CPU1於每一特定的 掃視間隔（△ ts = 3X △ tt )，將掃視頻率（Fs)只增加特定的 頻率（AFs)(步驟502)。即CPU1於從輸出了第1控 制訊號起，在只經過特定的掃視間隔（△ ts )時，將把掃 視頻率（Fs)設定爲第2頻率（Fs2 = Fsl+AFs)所需之第2 控制訊號輸出至PLL頻率合成器2。PLL頻率合成器2生 成具有第2頻率（Fs2)之訊號。調諧器10將具有第2頻 率之訊號的反射訊號輸出至VSWR測定手段5。調諧器1〇 將具有第2頻率之訊號與具有局部頻率之訊號加以混合， 藉由對應中間頻率之濾波器來生成具有中間頻率之訊號。 調諧器10將具有中間頻率之訊號輸出至線性檢波手段3 及對數檢波手段4。 於將第2控制訊號輸出至PLL頻率合成器2時， CPU 1將開關6加以設定，其結果爲：開關6從線性檢波 手段3輸入具有中間頻率之訊號的電壓（步驟5 02 ) ^ CPU 1於設定完開關後，於經過特定的切換間隔（△ tt ) 前，從A/D轉換器7將數位値加以取入，並把數位値及第 2頻率（Fs2 )當成第2線性測定値而加以記憶（步驟 -16- 502 )。 (14) 1355140 於設定完開關後，於經過特定的切換間隔（Δη) 時，CPU1再度設定開關6,其結果爲：開關6從對數檢 * 波手段4輸入把具有中間頻率之訊號之電壓予以對數轉換 之對數電壓（步驟5 02 ) 。CPU 1於再度設定完開關後， 於經過特定的切換間隔（ΔΠ)前，從A/D轉換器7將數 位値加以取入，把數位値及第2頻率（Fs2 )當成第2對 ® 數測定値而加以記憶（步驟5 02 )。 於再度設定完開關後，於經過特定的切換間隔（ △ tt)時，CPU 1再度設定開關6，其結果爲：開關6從 VSWR測定手段5輸入表示由訊號及其之反射訊號所求得 之電壓駐波比的電壓（步驟502 ) 。CPU1於再度設定完 開關後，於經過特定的切換間隔（Δη)前，從A/D轉換 器7將數位値加以取入，把數位値及第2頻率（Fs2 )當 成第2VSWR測定値而加以記億（步驟502 )。 ® 於步驟503中，掃視頻率（Fs)不與第η頻率（Fsn)相 等或不比其小時，CPU 1判定掃視已經結束。 如此，PLL頻率合成器2生成具有第1頻率（Fsl) 〜第η頻率（Fsn)之訊號，CPU 1將第1線性測定値〜第 η線性測定値、第1對數測定値〜第n對數測定値、及第 1VSWR測定値〜第nVSWR測定値加以記憶（步驟 502 ) 〇Before Msec), the digital 値 is taken in from the A/D converter 7, and the digital 値 and the F/IV rate sigma are memorized to add and determine the deterministic line. At a specific switching interval (Δπ), the CPU 1 resets the switch 6, and as a result, the switch 6 inputs a logarithmic voltage that logarithmically converts the voltage having the signal of the intermediate frequency from the logarithmic detection means 4, and outputs it to the A/D. Converter 7 (step 5 02). The ® A/D converter 7 converts the logarithmic voltage of the voltage having the intermediate frequency signal into a logarithmic value and outputs it to the CPU 1. After the CPU 1 resets the switch, the digital 値 is taken in from the A/D converter 7 before the specific switching interval (ΔΠ) elapses, and the digital 値 and the first frequency (Fsl) are taken as the first logarithmic measurement. Memory (step 502). After the switch is set again, when a specific switching interval (Δ tt ) elapses, the CPU 1 sets the switch 6 again. As a result, the switch 6 inputs the signal from the VSWR measuring means 5 indicating that the signal and its reflected signal are obtained. The voltage of the voltage standing wave ratio is output to the A/D converter 7 (step 502). The A/D converter 7 converts the voltage representing the voltage standing wave ratio into a digital value, and outputs it to the CPU 1. After the CPU 1 sets the switch again, the digital 値 is taken in from the A/D converter 7 before the specific switching interval (ΔΠ), and the digital 値 and the first frequency (Fsl) are taken as the first VSWR measurement. The memory is memorized (step 502). Thus, the CPU 1 sets the switch 6 at each specific switching interval (Δ tt ). As a result, the switch 6 is based on the linear detecting means 3, the logarithmic detecting means 4, and the VS WR measuring means 5. In order to switch the input of switch 6 - 15 (13) (13) 1355140 (refer to Figure 6). Further, when the input of the switch 6 is switched, the CPU 1 takes in the digital 从 from the A/D converter 7. Therefore, the CPU 读取 reads the digit 値 in the order of linear measurement 对, logarithmic measurement 値, and VSWR measurement 参照 (refer to Fig. 6). The CPU 1 determines whether or not the scan rate (Fs) is equal to or smaller than the nth frequency (final frequency) (Fsn) (step 503). When the sweep rate (Fs) and the nth frequency (Fsn) are equal or smaller, the CPU1 increases the scan rate (Fs) by only a specific frequency (AFs) for each specific scan interval (Δ ts = 3X Δ tt ). (Step 502). That is, the CPU 1 sets the second control rate (Fs2 = Fsl + AFs) to the second frequency (Fs2 = Fsl + AFs) when the specific scanning interval (Δ ts ) is passed from the output of the first control signal. The signal is output to the PLL frequency synthesizer 2. The PLL frequency synthesizer 2 generates a signal having a second frequency (Fs2). The tuner 10 outputs a reflection signal having a signal of the second frequency to the VSWR measuring means 5. The tuner 1 混合 mixes the signal having the second frequency with the signal having the local frequency, and generates a signal having an intermediate frequency by a filter corresponding to the intermediate frequency. The tuner 10 outputs a signal having an intermediate frequency to the linear detecting means 3 and the logarithmic detecting means 4. When the second control signal is output to the PLL frequency synthesizer 2, the CPU 1 sets the switch 6, and as a result, the switch 6 inputs the voltage having the signal of the intermediate frequency from the linear detecting means 3 (step 5 02 ) ^ CPU 1 After the switch is set, the digit 値 is taken in from the A/D converter 7 before the specific switching interval (Δ tt ), and the digit 値 and the second frequency (Fs2) are regarded as the second linear measurement. Remember (steps 16-502). (14) 1355140 After setting the switch, the CPU1 sets the switch 6 again after a certain switching interval (Δη) has elapsed. As a result, the switch 6 inputs the voltage of the signal having the intermediate frequency from the logarithmic check wave means 4. The logarithmic voltage of the logarithmic transformation (step 5 02 ). After the CPU 1 sets the switch again, the digital 値 is taken in from the A/D converter 7 before the specific switching interval (ΔΠ), and the digital 第 and the second frequency (Fs2) are regarded as the second pair of numbers. The enthalpy is measured and remembered (step 5 02 ). After the switch is set again, the CPU 1 sets the switch 6 again after a certain switching interval (Δ tt) has elapsed. As a result, the switch 6 inputs the signal from the VSWR measuring means 5 indicating that the signal and its reflected signal are obtained. The voltage of the voltage standing wave ratio (step 502). After the CPU 1 sets the switch again, the digital 値 is taken in from the A/D converter 7 before the specific switching interval (Δη) elapses, and the digital 値 and the second frequency (Fs2) are taken as the second VSWR measurement. Remember 100 million (step 502). ® In step 503, the scan rate (Fs) is not equal to or less than the nth frequency (Fsn), and the CPU 1 determines that the pan has ended. In this manner, the PLL frequency synthesizer 2 generates a signal having the first frequency (Fs1) to the nth frequency (Fsn), and the CPU 1 measures the first linear measurement 値 to the η linear measurement 値, the first logarithmic measurement 値 to the nth logarithm値, and the 1st VSWR measurement 値 ~ nVSWR measurement 値 are memorized (step 502) 〇
依據本發明之測定調諧器的特性之手法，爲了對丨個 調諧頻率（通道頻率）實行線性測定 '對數測定及VSWH -17- (15) 1355140 測定，只要進行一次如第3圖所示之訊號的掃視即可。因 此，調諧器的特性，可被高速測定，調整或檢查調諧器的 時間可被縮短。 (第2實施形態） 於第1實施形態中，CPU 1係於每一特定的切換間隔 (Δ tt= Δ ts/ 3 ) ’將開關6加以設定，其結果爲：開關 ^ 6以線性檢波手段3、對數檢波手段4及VSWR測定手段 5之順序來切換開關6之輸入（參照第6圖）。 於第2實施形態中，CPU 1係於每一特定的切換間隔 (Δ tt= Δ ts )，將開關6加以設定，其結果爲：開關6 以線性檢波手段3、對數檢波手段4及VSWR測定手段5 之順序來切換開關6之輸入（參照第7圖）。 於第2實施形態中，PLL頻率合成器2係生成具有第 1頻率（Fsl)〜第η頻率（Fsn)之RF訊號，CPU1將第 ® 1線性測定値〜第（n/3 )線性測定値、第1對數測定値〜 第（n/3 )對數測定値、及第 1VSWR測定値〜第 (n/3)VSWR測定値加以記憶。測定値之數目和第1實施形 態相比，雖爲1/3，但是，對於一個調諧頻率（通道頻 率）實行線性測定 '對數測定及VSWR測定，所以，只要 進行1次之如第3圖所示之RF訊號的掃視即可。因此， 調諧器的特性可被高速測定’調整或檢査調諧器之時間可 被縮短》 -18- (16) (16)1355140 (第1及第2實施形態的變形） 特定的切換間隔（△ tt )與特定的掃視間隔（△ ts ) 之關係，並不限定於前述之2個例子。因此，例如，也可 以是Att= 2Ats。另外，也可以是Att= Ats/G。即不管 特定的切換間隔（Δ tt )與特定的掃視間隔（△ ts )之關 係，RF訊號之掃視頻率在從第1頻率（Fsl)〜第η頻率 (Fsn )爲止被掃視之間，開關6以任意之特定的切換間 隔（Att)來切換開關6之輸入即可。 另外，特定的切換間隔（Δ tt )也可以不是被固定的 値。即特定的切換間隔（△ tt)也可以隨著時.間而變化。同 樣地，特定的掃視間隔（△ ts )也可以不是被固定的値。 進而，開關6也可不管線性檢波手段3、對數檢波手 段4及VSWR測定手段5之順序而來切換開關6之輸入。 例如，開關6以線性檢波手段3、對數檢波手段4、線性 檢波手段3、對數檢波手段4及VSWR測定手段5之順序 來切換開關6之輸入亦可。 (第3實施形態） 第8圖係表示依據本發明之測定調諧器的特性之另一 個裝置的功能方塊圖，第9圖係說明依據本發明之測定調 諧器的特性之另一個手法所需之流程圖，第10圖係說明 對於被掃視之RF訊號，取入測定値之時序所需的圖〃 如第8圖所示般，於第3實施形態中，本發明的裝置 係具備：CPU1、及PLL頻率合成器2、及線性檢波手段 -19- (17) (17)1355140 3'及對數檢波手段4、及VS WR測定手段5、及A/D轉換 器 81 、 82 及 83 。 不具備開關之本發明之裝置的CPU1，於將第1控制 訊號輸出至PLL頻率合成器2後，於經過特定的掃視間隔 (△ ts )(例如，3 # sec )之前，將3個數位値從A/D轉 換器81、82及83幾乎同時取入，而記憶第1線性測定 値、第1對數測定値及第1VSWR測定値（步驟902 ) (參照第1 〇圖）》 如此，PLL頻率合成器2生成具有第1頻率（Fsl ) 〜第η頻率（Fsn )之RF訊號，CPU1將第1線性測定値 〜第η線性測定値、第1對數測定値〜第η對數測定値' 及第1 VSWR測定値〜第nVSWR測定値加以記憶（步驟 902 )。 (其它實施形態） 該業者可以將前述之第1〜第3實施形態加以變形， 而容易地構成申請專利範圍所記載之發明。 例如，變更第3實施形態，於RF訊號之掃視頻率從 第1頻率（Fsl )〜第η頻率（Fsn)爲止被掃視之間，第 1線性測定値〜第h線性測定値、第1對數測定値〜第j 對數測定値、及第I VSWR測定値〜第kVSWR測定値相互 獨立而被記憶於CPU1亦可。 例如，於第1〜第3實施形態中，RF訊號之掃視頻率 從第1頻率（Fsl)〜第n頻率（Fsn)—面減少一面被掃 -20- (18) 1355140 視亦可。即RF訊號之掃視頻率可由第η頻率（Fsn)〜第 S F κί\ 率 頻 1Λ 少 減 而 【圖式簡單說明】 第〗圖係表示依據以往技術或本發明之測定調諧器的 特性之裝置的功能方塊圖。 第2圖係說明依據以往技術之測定調諧器的特性之手 ®法所需之流程圖。 第3圖係說明具有藉由第1圖中的CPU1及PLL頻率 合成器2所生成的第1頻率（Fsl)〜第η頻率（Fsn)之訊號 所需之圖。 第 4圖係表示顯示有線性測定値、對數測定値及 VSWR測定値之例。 第5圖係說明依據本發明之測定調諧器的特性之手法 所需之流程圖。 ® 第6圖係說明對於被掃視之訊號，將測定値加以取入 之時序所需之圖。 第7圖係說明對於被掃視之訊號，將測定値加以取入 之時序所需之圖。 第8圖係表示依據本發明之測定調諧器的特性之裝置 的功能方塊圖。 第9圖係說明依據本發明之測定調諧器的特性的手法 所需之流程圖。 第1 〇圖係說明對於被掃視之訊號，將測定値加以取 -21 - ⑧ (19) (19)1355140 入之時序所需之圖。 【主要元件符號說明】 2 : PLL頻率合成器 3 :線性檢波手段 4 :對數檢波手段 5 : V S W R測定手段According to the method for measuring the characteristics of the tuner of the present invention, in order to perform linear measurement 'logarithmic measurement' and VSWH -17-(15) 1355140 for one tuning frequency (channel frequency), the signal as shown in FIG. 3 is performed once. Glance at it. Therefore, the characteristics of the tuner can be measured at high speed, and the time for adjusting or checking the tuner can be shortened. (Second Embodiment) In the first embodiment, the CPU 1 sets the switch 6 for each specific switching interval (Δ tt = Δ ts / 3 ). As a result, the switch 6 is linearly detected. 3. The input of the logarithmic detection means 4 and the VSWR measuring means 5 is switched (see Fig. 6). In the second embodiment, the CPU 1 sets the switch 6 for each specific switching interval (Δ tt = Δ ts ), and as a result, the switch 6 is measured by the linear detecting means 3, the logarithmic detecting means 4, and the VSWR. The order of means 5 is used to switch the input of switch 6 (see Figure 7). In the second embodiment, the PLL frequency synthesizer 2 generates an RF signal having a first frequency (Fs1) to an nth frequency (Fsn), and the CPU 1 linearly measures the first to the first (n/3). The first logarithmic measurement 値 ~ the (n/3) logarithmic measurement 値, and the first VSWR measurement 値 to the (n/3) VSWR measurement 値 are memorized. Although the number of measured enthalpy is 1/3 compared with the first embodiment, the linear measurement 'logarithm measurement and VSWR measurement are performed on one tuning frequency (channel frequency), so that it is performed once as shown in FIG. The glance of the RF signal can be displayed. Therefore, the characteristics of the tuner can be measured at high speed. 'The time for adjusting or checking the tuner can be shortened. -18- (16) (16) 1355140 (Modification of the first and second embodiments) Specific switching interval (△ tt The relationship with the specific saccade interval (Δ ts ) is not limited to the above two examples. Therefore, for example, it is also Att = 2Ats. Alternatively, it may be Att=Ats/G. That is, regardless of the relationship between the specific switching interval (Δ tt ) and the specific scanning interval (Δ ts ), the scan rate of the RF signal is swept between the first frequency (Fsl) and the nth frequency (Fsn), and the switch 6 The input of the switch 6 can be switched at any particular switching interval (Att). In addition, the specific switching interval (Δ tt ) may not be fixed. That is, the specific switching interval (Δ tt) may also vary with time. Similarly, the specific saccade interval (Δ ts ) may not be fixed 値. Further, the switch 6 can switch the input of the switch 6 regardless of the order of the linear detecting means 3, the logarithmic detecting means 4, and the VSWR measuring means 5. For example, the switch 6 may switch the input of the switch 6 in the order of the linear detecting means 3, the logarithmic detecting means 4, the linear detecting means 3, the logarithmic detecting means 4, and the VSWR measuring means 5. (Third Embodiment) Fig. 8 is a functional block diagram showing another apparatus for measuring the characteristics of a tuner according to the present invention, and Fig. 9 is a view showing another method required for measuring the characteristics of the tuner according to the present invention. FIG. 10 is a view showing the timing required for taking in the measurement timing of the RF signal to be scanned. As shown in FIG. 8, in the third embodiment, the apparatus of the present invention includes: CPU1. And PLL frequency synthesizer 2, and linear detection means -19-(17) (17) 1355140 3' and logarithmic detection means 4, VS WR measuring means 5, and A/D converters 81, 82 and 83. The CPU 1 of the apparatus of the present invention which does not have a switch outputs three digits before the specific scanning interval (Δ ts ) (for example, 3 # sec ) after the first control signal is output to the PLL frequency synthesizer 2 The A/D converters 81, 82, and 83 are taken in almost the same time, and the first linear measurement 値, the first logarithmic measurement 値, and the first VSWR measurement 记忆 are stored (step 902) (refer to FIG. 1). Thus, the PLL frequency The synthesizer 2 generates an RF signal having a first frequency (Fsl) to an nth frequency (Fsn), and the CPU 1 measures the first linear measurement 値 to the η linear measurement 値, the first logarithmic measurement 値 to the nth logarithm 値' and the first 1 VSWR measurement 値 ~ nVSWR measurement 値 is memorized (step 902). (Other Embodiments) The above-described first to third embodiments can be modified, and the invention described in the patent application can be easily constructed. For example, in the third embodiment, the first linear measurement 値 to the h-th linear measurement 値 and the first logarithmic measurement are performed between the first video frequency (Fsl) and the n-th frequency (Fsn). The 値~j-log measurement 値 and the first VSWR measurement 値 to the kVSWR measurement 値 are independent of each other and may be memorized in the CPU 1. For example, in the first to third embodiments, the scan rate of the RF signal is swept from the first frequency (Fsl) to the nth frequency (Fsn) to the surface -20-(18) 1355140. That is, the scan rate of the RF signal can be reduced by the nth frequency (Fsn) to the SF κί\ rate 1 【. [Simplified illustration] The diagram shows the device according to the prior art or the apparatus for measuring the characteristics of the tuner of the present invention. Functional block diagram. Fig. 2 is a flow chart showing the flow required by the hand method for measuring the characteristics of a tuner according to the prior art. Fig. 3 is a view showing the signals required for the first frequency (Fs1) to the nth frequency (Fsn) generated by the CPU 1 and the PLL frequency synthesizer 2 in Fig. 1 . Fig. 4 shows an example in which a linear measurement 値, a logarithmic measurement 値, and a VSWR measurement 显示 are shown. Figure 5 is a flow chart showing the steps required to determine the characteristics of the tuner in accordance with the present invention. ® Figure 6 is a diagram showing the timing required to take the measured enthalpy for the signal being scanned. Figure 7 is a diagram showing the timing required to take the measured enthalpy for the signal being scanned. Figure 8 is a functional block diagram showing an apparatus for measuring the characteristics of a tuner according to the present invention. Fig. 9 is a flow chart showing the method required for measuring the characteristics of the tuner according to the present invention. The first diagram shows the map required to take the timing of the -21 - 8 (19) (19) 1355140 for the signal being scanned. [Description of main component symbols] 2 : PLL frequency synthesizer 3 : Linear detection means 4 : Logarithmic detection means 5 : V S W R measurement means
7 : A/D轉換器 10 :調諧器 8 1 : A/D轉換器 82 : A/D轉換器 83 : A/D轉換器7 : A/D converter 10 : Tuner 8 1 : A/D converter 82 : A/D converter 83 : A/D converter
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