JPH10126217A - Decimation filter - Google Patents
Decimation filterInfo
- Publication number
- JPH10126217A JPH10126217A JP27240996A JP27240996A JPH10126217A JP H10126217 A JPH10126217 A JP H10126217A JP 27240996 A JP27240996 A JP 27240996A JP 27240996 A JP27240996 A JP 27240996A JP H10126217 A JPH10126217 A JP H10126217A
- Authority
- JP
- Japan
- Prior art keywords
- filter
- decimation filter
- signal
- frequency
- rbwn
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/16—Spectrum analysis; Fourier analysis
- G01R23/165—Spectrum analysis; Fourier analysis using filters
- G01R23/167—Spectrum analysis; Fourier analysis using filters with digital filters
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- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- General Physics & Mathematics (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、デシメーションフ
ィルタに関し、特にスペクトラム・アナライザ、ネット
ワーク・アナライザ、無線機テスター変調解析装置等、
高周波信号を周波数変換し、ベースバンドにて解析する
装置全般に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decimation filter, and more particularly to a spectrum analyzer, a network analyzer, a radio equipment tester modulation analyzer, and the like.
The present invention relates to an apparatus for converting a high-frequency signal into a frequency and analyzing the converted signal at a baseband.
【０００２】[0002]
【従来の技術】図３はスペクトラムアナライザの従来例
のブロック図である。入力信号であるＲＦ信号はミキサ
Ｍｉｘ１１と局部発振器Ｌｏｃａｌ１１によってＩＦ周
波数ＩＦ１に変換され、バンドパスフィルタＢＰＦ１に
よって帯域制限される。同様にして、ＩＦ周波数ＩＦ１
はミキサＭｉｘ１２と局部発振器Ｌｏｃａｌ１２によっ
てＩＦ周波数ＩＦ２に変換され、バンドパスフィルタＢ
ＰＦ２によって帯域制限され、ＩＦ周波数ＩＦ２はミキ
サＭｉｘ１３と局部発振器Ｌｏｃａｌ１３によってＩＦ
周波数ＩＦ３に変換される。ＩＦ周波数ＩＦ３はいくつ
かのバンドパスフィルタＢＰＦ３1，ＢＰＦ３2，…，Ｂ
ＰＦ３ｎを通過した後、対数アンプＡＭＰによってダイ
ナミックレンジが拡大され、検波器ＤＴで電力が検出さ
れる。検出された電力はビデオフィルタＶＦを通過した
後、Ａ／Ｄ変換器ＡＤにより数値化される。ここで、局
部発振器Ｌｏｃａｌ１１を掃引すれば、掃引周波数幅に
応じたスペクトラムを測定できる。2. Description of the Related Art FIG. 3 is a block diagram of a conventional example of a spectrum analyzer. An RF signal as an input signal is converted into an IF frequency IF1 by a mixer Mix11 and a local oscillator Local11, and band-limited by a bandpass filter BPF1. Similarly, IF frequency IF1
Is converted to an IF frequency IF2 by the mixer Mix12 and the local oscillator Local12, and the bandpass filter B
The band is limited by the PF2, and the IF frequency IF2 is controlled by the mixer Mix13 and the local oscillator Local13.
It is converted to the frequency IF3. IF frequency IF3 includes several band-pass filters BPF3 1 , BPF3 2 ,.
After passing through the PF 3n, the dynamic range is expanded by the logarithmic amplifier AMP, and the power is detected by the detector DT. After passing through the video filter VF, the detected power is digitized by the A / D converter AD. Here, if the local oscillator Local11 is swept, a spectrum corresponding to the sweep frequency width can be measured.
【０００３】図４（１）、（２）は従来のデシメーショ
ンフィルタのブロック図である。FIGS. 4A and 4B are block diagrams of a conventional decimation filter.
【０００４】図４（１）のデシメーションフィルタで
は、入力信号であるＲＦ信号をミキサＭｉｘ１１と局部
発振器Ｌｏｃａｌ１２によって中間周波数ＩＦ１に変換
し、バンドパスフィルタＢＰＦ１によって帯域制限し、
さらにミキサＭｉｘ１２と局部発振器Ｌｏｃａｌ１２に
よって中間周波数ＩＦ２に変換し、Ａ／Ｄ変換器ＡＤに
よってデジタル信号に変換し、直交検波、フィルタリン
グを行なってベースバンド・ベクトル信号Ｉ，Ｑを得て
復調、変調等の処理を行なう。In the decimation filter shown in FIG. 4A, an RF signal, which is an input signal, is converted into an intermediate frequency IF1 by a mixer Mix11 and a local oscillator Local12, and band-limited by a band-pass filter BPF1.
Further, the signal is converted to an intermediate frequency IF2 by a mixer Mix12 and a local oscillator Local12, converted to a digital signal by an A / D converter AD, subjected to quadrature detection and filtering to obtain baseband vector signals I and Q, demodulated, modulated, etc. Is performed.
【０００５】図４（２）のデシメーションフィルタで
は、中間周波数ＩＦ２を得るまでは図４（１）のデシメ
ーションフィルタと同じであるが、直交検波をアナログ
で実行し、Ａ／Ｄ変換とフィルタリングをベースバンド
・ベクトル信号Ｉ，Ｑ毎に実行する点が図４（１）のデ
シメーションフィルタと異なっている。The decimation filter shown in FIG. 4 (2) is the same as the decimation filter shown in FIG. 4 (1) until the intermediate frequency IF2 is obtained. However, the quadrature detection is executed in analog, and the A / D conversion and the filtering are performed. It differs from the decimation filter of FIG. 4A in that the process is executed for each of the band vector signals I and Q.
【０００６】[0006]
【発明が解決しようとする課題】図３に示した従来のス
ペクトラムアナライザは下記のような欠点があった。 （１）バンドパスフィルタＢＰＦ３1，ＢＰＦ３2，…は
ひとつひとつアナログ回路にて構成しなくてはならない
ため、調整工数を要し、温度によるドリフトも発生す
る。また、１００Ｈｚ以下の狭帯域フィルタは実現のた
めに非常に高い技術を要する。 （２）検波器と対数アンプは部品点数も多く、調整個数
も多く、電力消費が高い。また、対数アンプは７段程度
の直線アンプの組み合わせであり、厳密な対数演算では
なく、誤差がつきまとう。The conventional spectrum analyzer shown in FIG. 3 has the following disadvantages. (1) Since each of the band-pass filters BPF3 1 , BPF3 2 ,... Must be constituted by an analog circuit, an adjustment man-hour is required, and drift due to temperature occurs. In addition, a narrow band filter of 100 Hz or less requires a very high technology for realization. (2) The detector and the logarithmic amplifier have a large number of parts, a large number of adjustments, and high power consumption. Further, the logarithmic amplifier is a combination of about seven stages of linear amplifiers, and is not a strict logarithmic operation but has an error.
【０００７】また、図４に示した従来のデシメーション
フィルタは、 （１）図４（１）の場合、高速（１ＭＨｚ以上）のＡ／
Ｄ変換器と、大容量のメモリが必要で、また高速でサン
プリングするため、フィルタリング等の処理の負荷が大
きい。 （２）図４（２）の場合、図４（１）の場合よりも低速
でサンプリングが可能であるが、Ａ／Ｄ変換器が２個必
要で、装置が複雑であり、また直交検波をアナログで行
うため、直交検波部でのレベルがあっていないと、Ｉ，
Ｑの出力にレベル差が生じるという欠点がある。The conventional decimation filter shown in FIG. 4 has the following problems: (1) In the case of FIG. 4A, a high-speed (1 MHz or more) A / D
Since a D converter and a large-capacity memory are required, and sampling is performed at high speed, the load of processing such as filtering is large. (2) In the case of FIG. 4 (2), sampling can be performed at a lower speed than in the case of FIG. 4 (1). However, two A / D converters are required, the apparatus is complicated, and quadrature detection is performed. Since the analog detection is performed, if the level in the quadrature detector does not match, I,
There is a disadvantage that a level difference occurs in the output of Q.
【０００８】本発明の目的は、上記の問題点を解消した
デシメーションフィルタを提供することにある。An object of the present invention is to provide a decimation filter which solves the above-mentioned problems.
【０００９】[0009]
【課題を解決するための手段】本発明のデシメーション
フィルタは、中間周波数を帯域制限するフィルタ素子と
して、１個または多段に連結された、アナログ処理によ
るＦＩＲフィルタを用いる。The decimation filter according to the present invention uses a single or multi-stage FIR filter by analog processing as a filter element for band-limiting an intermediate frequency.
【００１０】ここで、アナログ処理によるＦＩＲフィル
タとはアナログデジタルフィルタ（ＡＤＦ）（参考文
献：（株）鷹山発行「ニューロン素子への道程」より
「ニューロン素子技術資料：アナログデジタルフィルタ
（ＡＤＦ）の動作原理」）である。このＡＤＦはニュー
ロン素子により構成され、入力信号はアナログ入力信号
とデジタル制御信号、出力信号はアナログ出力信号であ
り、内部にサンプル・ホールド回路を有し、サンプル・
ホールド回路の時間間隔はそれに与えるサンプリングク
ロックで決まる。サンプル・ホールド回路の各段の出力
はアナログ乗算器につながり、アナログ乗算器のもう一
方の入力に８ビット等の分解能を持つＤ／Ａ変換器の出
力を加える。Ｄ／Ａ変換器の値に適当な係数を与えれ
ば、サンプル・ホールド回路の段数に応じたＦＩＲフィ
ルタが形成される。上記係数は動作中でも書き換え可能
である。[0010] Here, the FIR filter by analog processing is an analog digital filter (ADF) (reference: published by Takayama Co., Ltd., “A Path to Neuron Devices”, “Technical Data of Neuron Devices: Operation of Analog Digital Filter (ADF)”). Principle)). The ADF is composed of neuron elements, the input signal is an analog input signal and a digital control signal, the output signal is an analog output signal, and has an internal sample and hold circuit.
The time interval of the hold circuit is determined by the sampling clock applied thereto. The output of each stage of the sample and hold circuit is connected to an analog multiplier, and the output of a D / A converter having a resolution of 8 bits or the like is applied to the other input of the analog multiplier. If an appropriate coefficient is given to the value of the D / A converter, an FIR filter corresponding to the number of stages of the sample and hold circuit is formed. The above coefficients can be rewritten during operation.
【００１１】従来、デジタル信号処理で実現したフィル
タ処理をアナログ処理で行なうため、処理速度が格段に
早くなる、配線数、部品点数が少なくて済む、消費電力
が減る、フィルタの調整が不要、温度ドリフトがなくな
る。Conventionally, since filter processing realized by digital signal processing is performed by analog processing, the processing speed is significantly increased, the number of wires and components is reduced, power consumption is reduced, filter adjustment is unnecessary, and temperature is reduced. Drift disappears.
【００１２】本発明の実施態様によれば、前記中間周波
数の同相成分、直交成分の各々に対して前記ＦＩＲフィ
ルタを用いる。According to an embodiment of the present invention, the FIR filter is used for each of the in-phase component and the quadrature component of the intermediate frequency.
【００１３】本発明の実施態様によれば、各ＦＩＲフィ
ルタに与えられるクロックを出力する分周器を有する。According to an embodiment of the present invention, there is provided a frequency divider for outputting a clock applied to each FIR filter.
【００１４】本発明の実施態様によれば、デシメーショ
ンフィルタがスペクトラム・アナライザ、ネットワーク
・アナライザ、無線機テスター変調解析装置等の測定装
置である。According to an embodiment of the present invention, the decimation filter is a measuring device such as a spectrum analyzer, a network analyzer, a radio equipment tester modulation analyzer, and the like.
【００１５】[0015]
【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.
【００１６】図１は本発明の第１の実施形態で、スペク
トラムアナライザのブロック図である。FIG. 1 is a block diagram of a spectrum analyzer according to a first embodiment of the present invention.
【００１７】本実施形態のスペクトラムアナライザで
は、従来のスペクトラムアナライザの中間周波数ＩＦ
（例：２１．４ＭＨｚ，必要に応じて変えてもよい）を
ミキサＭｉｘと局部発振器ＬｏｃａｌでＩＦ周波数とミ
キシングし、そのベースバンド信号Ｉを、前述したＡＤ
Ｆである素子ＲＢＷ１，ＲＢＷ２，…，ＲＢＷｎと順
次、狭帯域のフィルタを通過させ、最終段の素子ＲＢＷ
ｎを通過したベースバンド信号Ｉを対数アンプＡＭＰで
増幅し、検波器ＤＴで電力、すなわちスペクトラム成分
を抽出した後、Ａ／Ｄ変換器ＡＤでデジタル化する。こ
こで、各素子ＲＢＷ２，…，ＲＢＷｎに与えるクロック
は各段の、局部発振器Ｌｏｃａｌ０の出力を分周する分
周器ＦＤ１，ＦＤ２，…，で得られる。また、ＡＤＦ素
子の接続段数は必要とする分解能に応じて決められる。In the spectrum analyzer of the present embodiment, the intermediate frequency IF of the conventional spectrum analyzer is used.
(Example: 21.4 MHz, which may be changed as necessary) is mixed with the IF frequency by the mixer Mix and the local oscillator Local, and the baseband signal I is converted to the above-mentioned AD.
RBWn are sequentially passed through a narrow band filter, and the final stage element RBW
The baseband signal I having passed through n is amplified by the logarithmic amplifier AMP, and the power, that is, the spectrum component is extracted by the detector DT, and then digitized by the A / D converter AD. .., RBWn are obtained by frequency dividers FD1, FD2,... At each stage for dividing the output of local oscillator Local0. Further, the number of connection stages of the ADF element is determined according to the required resolution.
【００１８】本実施形態によれば、（１）非常に少ない
配線で多段のフィルタ群を形成でき、（２）部品点数が
大幅に減り、（３）消費電力も大幅に減り、（４）さら
にフィルタ素子の調整が不要で、温度ドリフトも無くな
る。According to the present embodiment, (1) a multi-stage filter group can be formed with very few wirings, (2) the number of parts is significantly reduced, (3) the power consumption is significantly reduced, and (4) further. No adjustment of the filter element is required, and there is no temperature drift.
【００１９】なお、検波器、対数アンプもＡＤＦ素子を
用いて構成することができる。Note that the detector and the logarithmic amplifier can also be configured using ADF elements.
【００２０】図２は本発明の第２の実施形態で、デシメ
ーションフィルタのブロック図である。FIG. 2 is a block diagram of a decimation filter according to a second embodiment of the present invention.
【００２１】本実施形態では、従来のデシメーションフ
ィルタの中間周波ＩＦ（例２１．４ＭＨｚ、必要に応じ
て変えてもよい）を、ミキサＭｉｘ１とＭｉｘ２、局部
発振器Ｌｏｃａｌ１、移相器ＰＳを用いてアナログ信号
のまま同相成分Ｉと直交成分Ｑに直交検波し、同相成分
Ｉを、前述したＡＤＦである素子ＲＢＷ１1，ＲＢＷ
２1，…，ＲＢＷｎ1と順次、狭帯域のフィルタ素子を通
過させ、Ａ／Ｄ変換器ＡＤ１でデジタル信号に変換し、
同様に直交成分Ｑを、前述したＡＤＦである素子ＲＢＷ
１2，ＲＢＷ２2，…，ＲＢＷｎ2と順次、狭帯域のフィ
ルタ素子を通過させ、Ａ／Ｄ変換器ＡＤ２でデジタル信
号に変換し、最後に、ベクトル信号処理回路ＶＣでベク
トル信号処理を行なって変調解析等を行う。なお、ＡＤ
Ｆ素子ＲＢＷ２1と２2，…，ＲＢＷｎ1とＲＢＷｎ2に与
えるクロックはそれぞれ分周器ＦＤ１，ＦＤ２，…で得
られる。また、ＡＤＦ素子の接続段数は必要とする分解
能に応じて決められる。また、ダイナミックレンジが足
らない場合、直交検波の前にステップアンプをおいても
よい。In the present embodiment, the intermediate frequency IF (eg, 21.4 MHz, which may be changed as necessary) of the conventional decimation filter is converted into an analog signal using mixers Mix1 and Mix2, a local oscillator Local1, and a phase shifter PS. The signals are subjected to quadrature detection to the in-phase component I and the quadrature component Q, and the in-phase component I is converted into the ADF elements RBW1 1 and RBW.
2 1, ..., RBWn 1 sequentially passes a narrow band of the filter element, into a digital signal by the A / D converter AD1,
Similarly, the orthogonal component Q is replaced with the element RBW which is the above-described ADF.
1 2, RBW2 2, ..., sequentially and RBWn 2, passed through a narrow band filter element, into a digital signal by the A / D converter AD2, finally, by performing vector signal processing by the vector signal processing circuit VC Perform modulation analysis. Note that AD
The clocks applied to the F elements RBW2 1 and 2 2 ,..., RBWn 1 and RBWn 2 are obtained by frequency dividers FD1, FD2,. Further, the number of connection stages of the ADF element is determined according to the required resolution. If the dynamic range is insufficient, a step amplifier may be provided before quadrature detection.
【００２２】本実施形態によれば、（１）従来、デジタ
ル信号処理で実現していたフィルタ処理をアナログ処理
で行なうため、処理スピードが格段に早くなり、（２）
Ａ／Ｄ変換器は最初からデシメーションした信号を扱え
ばよいので、扱うデータ量の少なく、処理スピードが格
段に早くなり、（３）メモリが最小構成で済み、コス
ト、サイズともに小さくなり、（４）非常に少ない配線
で、多段のフィルタ群を形成でき、（５）部品点数が大
幅に減り、（６）消費電力も大幅に減り、（７）フィル
タ素子の調整が不要で、温度ドリフトもない。According to the present embodiment, (1) the filtering processing which has conventionally been realized by digital signal processing is performed by analog processing, so that the processing speed is significantly increased, and (2)
Since the A / D converter only has to handle the signal decimated from the beginning, the amount of data to be handled is small, the processing speed is much faster, (3) the memory has the minimum configuration, the cost and size are reduced, and (4) ) A multi-stage filter group can be formed with very few wires, (5) the number of components is greatly reduced, (6) the power consumption is significantly reduced, and (7) there is no need to adjust the filter element and there is no temperature drift. .
【００２３】[0023]
【発明の効果】以上説明したように、本発明は下記のよ
うな効果がある。 （１）フィルタ処理の処理スピードが早くなる。 （２）Ａ／Ｄ変換器の扱うデータ量が少なく、処理スピ
ードが早くなる。 （３）メモリが最小構成ですみ、コスト、サイズとも小
さくなる。 （４）非常に少なく配線で多段のフィルタ群を形成でき
る。 （５）フィルタ処理の部品点数が減る。 （６）消費電力が減る。 （７）フィルタの調整が不要で、温度ドリフトもない。As described above, the present invention has the following effects. (1) The processing speed of the filter processing is increased. (2) The amount of data handled by the A / D converter is small, and the processing speed is increased. (3) The memory requires a minimum configuration, and both cost and size are reduced. (4) A multistage filter group can be formed with very few wirings. (5) The number of components for the filtering process is reduced. (6) Power consumption is reduced. (7) No filter adjustment is required and there is no temperature drift.
【図１】本発明の第１の実施形態で、スペクトラムアナ
ライザのブロック図である。FIG. 1 is a block diagram of a spectrum analyzer according to a first embodiment of the present invention.
【図２】本発明の第２の実施形態で、デシメーションフ
ィルタのブロック図である。FIG. 2 is a block diagram of a decimation filter according to a second embodiment of the present invention.
【図３】スペクトラムアナライザの従来例のブロック図
である。FIG. 3 is a block diagram of a conventional example of a spectrum analyzer.
【図４】デシメーションフィルタの従来例のブロック図
である。FIG. 4 is a block diagram of a conventional example of a decimation filter.
Ｍｉｘ，Ｍｉｘ１，Ｍｉｘ２ ミキサ Ｌｏｃａｌ０、Ｌｏｃａｌ１ 局部発振器 ＲＢＷ１，ＲＢＷ２，…ＲＢＷｎ，ＲＢＷ１1，ＲＢＷ
２1，…，ＲＢＷｎ1，ＲＢＷ１2，ＲＢＷ２2，…，ＲＢ
Ｗｎ2 ＡＤＦ素子 ＦＤ１，ＦＤ２ 分周器 ＡＤ，ＡＤ１，ＡＤ２ Ａ／Ｄ変換器 ＤＴ 検波器 ＡＭＰ 対数アンプ ＶＣ ベクトル信号処理回路Mix, Mix1, Mix2 mixer Local0, Local1 local oscillator RBW1, RBW2, ... RBWn, RBW1 1, RBW
2 1, ..., RBWn 1, RBW1 2, RBW2 2, ..., RB
Wn 2 ADF element FD1, FD2 frequency divider AD, AD1, AD2 A / D converter DT detector AMP Logarithmic amplifier VC Vector signal processing circuit
Claims (4)
周波数を帯域制限するフィルタ素子として、１個または
多段に連結された、アナログ処理によるＦＩＲフィルタ
を用いることを特徴とするデシメーションフィルタ。1. A decimation filter in which a single or multi-stage FIR filter by analog processing is used as a filter element for band-limiting an intermediate frequency.
各々に対して前記ＦＩＲフィルタを用いる、請求項１記
載のデシメーションフィルタ。2. The decimation filter according to claim 1, wherein the FIR filter is used for each of an in-phase component and a quadrature component of the intermediate frequency.
を出力する分周器を有する、請求項１または２記載のデ
シメーションフィルタ。3. The decimation filter according to claim 1, further comprising a frequency divider for outputting a clock applied to each FIR filter.
トラム・アナライザ、ネットワーク・アナライザ、無線
機テスター変調解析装置等の測定装置である、請求項１
から３のいずれか１項記載のデシメーションフィルタ。4. The decimation filter according to claim 1, wherein said decimation filter is a measuring device such as a spectrum analyzer, a network analyzer, and a radio equipment tester modulation analyzer.
4. The decimation filter according to any one of claims 1 to 3.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27240996A JPH10126217A (en) | 1996-10-15 | 1996-10-15 | Decimation filter |
| DE1997145391 DE19745391A1 (en) | 1996-10-15 | 1997-10-14 | Decimating filter arrangement with analogue processing FIR filter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27240996A JPH10126217A (en) | 1996-10-15 | 1996-10-15 | Decimation filter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10126217A true JPH10126217A (en) | 1998-05-15 |
Family
ID=17513508
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27240996A Withdrawn JPH10126217A (en) | 1996-10-15 | 1996-10-15 | Decimation filter |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH10126217A (en) |
| DE (1) | DE19745391A1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100606126B1 (en) | 2003-05-12 | 2006-07-28 | 삼성전자주식회사 | Device and Method for canceling narrow-band interference in mobile communication systems |
| JP2008520120A (en) * | 2004-11-10 | 2008-06-12 | 株式会社アドバンテスト | Image cancellation in frequency converters for spectrum analyzers. |
| CN102879644A (en) * | 2012-11-01 | 2013-01-16 | 南京国睿安泰信科技股份有限公司 | System for realizing resolution bandwidth of spectrum analyzer by utilizing pre-switching of analog bandwidth |
| CN102928665A (en) * | 2012-11-01 | 2013-02-13 | 南京国睿安泰信科技股份有限公司 | Intermediate frequency digital spectrum analyzer and method thereof |
| KR101539114B1 (en) * | 2008-06-27 | 2015-07-23 | 삼성전자 주식회사 | No decimation FIR filter |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6844715B2 (en) * | 2002-09-05 | 2005-01-18 | Honeywell International Inc. | Synthetic RF detection system and method |
| DE102004020278A1 (en) * | 2004-04-26 | 2005-11-10 | Rohde & Schwarz Gmbh & Co. Kg | Spectrum analyzer with high speed and high resolution |
-
1996
- 1996-10-15 JP JP27240996A patent/JPH10126217A/en not_active Withdrawn
-
1997
- 1997-10-14 DE DE1997145391 patent/DE19745391A1/en not_active Ceased
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100606126B1 (en) | 2003-05-12 | 2006-07-28 | 삼성전자주식회사 | Device and Method for canceling narrow-band interference in mobile communication systems |
| JP2008520120A (en) * | 2004-11-10 | 2008-06-12 | 株式会社アドバンテスト | Image cancellation in frequency converters for spectrum analyzers. |
| KR101539114B1 (en) * | 2008-06-27 | 2015-07-23 | 삼성전자 주식회사 | No decimation FIR filter |
| CN102879644A (en) * | 2012-11-01 | 2013-01-16 | 南京国睿安泰信科技股份有限公司 | System for realizing resolution bandwidth of spectrum analyzer by utilizing pre-switching of analog bandwidth |
| CN102928665A (en) * | 2012-11-01 | 2013-02-13 | 南京国睿安泰信科技股份有限公司 | Intermediate frequency digital spectrum analyzer and method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| DE19745391A1 (en) | 1998-04-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20040106 |