SU1547075A1

SU1547075A1 - Code converter

Info

Publication number: SU1547075A1
Application number: SU874297691A
Authority: SU
Inventors: Леонид Вольфович Друзь
Original assignee: Предприятие П/Я А-3706
Priority date: 1987-08-18
Filing date: 1987-08-18
Publication date: 1990-02-28

Abstract

Изобретение относитс к вычислительной технике и может быть использовано в устройствах дл передачи данных. Изобретение позвол ет проводить, кроме пр мого преобразовани безрегистровых кодов в многорегистровые, также и обратное преобразование многорегистровых кодов в безрегистровые, чем обеспечиваетс расширение области использовани преобразовател кодов. Преобразователь кодов содержит генератор 1 импульсов, элементы И 2-5, элементы ИЛИ 6,7 и 8, триггеры 9,10 и 11, коммутаторы 12,18 и 19, регистр 13, дешифратор 14, блок 15 сравнени , элемент НЕ 16, распределитель 17 импульсов, блок 20 пам ти и блок 21 регистровых признаков. Дешифратор 14 содержит формирователи сигналов, элемент И, элементы ИЛИ и элемент НЕ. Блок 21 регистровых признаков содержит элементы ИЛИ, триггеры и элементы И. 2 з.п. ф-лы, 3 ил.The invention relates to computing and can be used in devices for data transmission. The invention allows, in addition to direct conversion of non-register codes into multi-register codes, also the reverse conversion of multi-register codes into non-register codes, thus expanding the range of use of the code converter. The code converter contains 1 pulse generator, elements AND 2-5, elements OR 6.7 and 8, triggers 9, 10 and 11, switches 12, 18 and 19, register 13, decoder 14, comparison block 15, HE 16, distributor 17 pulses, a memory block 20 and a register 21 block of signs. The decoder 14 contains the signal conditioners, the AND element, the OR elements and the NOT element. Block 21 of the register features contains OR elements, triggers, and elements I. 2 s.p. f-ly, 3 ill.

Description

элемента И соединен с S-входом перво- 2Q но объединены и вл ютс входом дего триггера, пр мой выход которого соединен с первым входом управлени второго коммутатора, инверсный выход первого триггера соединен с первым входом третьего элемента ИЛИ, выход 25 которого соединен с первым и вторым входами третьего коммутатора и вторым входом третьего элемента И, выход которого соединен с установочным входом регистра и вл етс вторым выходом 30 преобразовател , выход первого элемента ИЛИ соединен с S-входом второго триггера, пр мой выход третьего триггера соединен с вторым входом второгоelement I is connected to the S-input of the first 2Q but combined and is the input of a de trigger, the direct output of which is connected to the first control input of the second switch, the inverse output of the first trigger is connected to the first input of the third OR element, output 25 of which is connected to the first and the second inputs of the third switch and the second input of the third element AND, the output of which is connected to the setup input of the register and is the second output 30 of the converter, the output of the first element OR is connected to the S input of the second trigger, the third direct output about the trigger is connected to the second input of the second

шифратора.the encoder.

3. Преобразователь по п. 1, отличающийс тем, что блок регистровых признаков выполнен на эл ментах ИЛИ, триггерах и элементах И, выход первого элемента И соединен с S-входом первого триггера и первыми входами первого и второго элементов ИЛИ, выходы которых соединены с R-входами соответственно второго и третьего триггеров, выход второго элемента И соединен с S-входом второго триггера, вторым входом второго3. The converter according to claim 1, characterized in that the register feature block is executed on OR elements, triggers and elements AND, the output of the first element AND is connected to the S input of the first trigger and the first inputs of the first and second elements OR, the outputs of which are connected to R-inputs, respectively, of the second and third triggers, the output of the second element And is connected to the S-input of the second trigger, the second input of the second

шифратора.the encoder.

3. Преобразователь по п. 1, отличающийс тем, что блок регистровых признаков выполнен на элментах ИЛИ, триггерах и элементах И, выход первого элемента И соединен с S-входом первого триггера и первыми входами первого и второго элементов ИЛИ, выходы которых соединены с R-входами соответственно второго и третьего триггеров, выход второго элемента И соединен с S-входом второго триггера, вторым входом второго3. The converter according to claim 1, characterized in that the register feature block is made on the OR elements, triggers and elements AND, the output of the first element AND is connected to the S input of the first trigger and the first inputs of the first and second elements OR, the outputs of which are connected to R inputs, respectively, of the second and third triggers, the output of the second element And is connected to the S-input of the second trigger, the second input of the second

элемента ИЛИ и вторым входом управле- ,с элемента ИЛИ и первым входом третьегоthe OR element and the second control input, from the OR element and the first input of the third

ни второго коммутатора, инверсный выход третьего триггера соединен с вторым входом третьего элемента ИЛИ и первым и вторым входами управлени nor the second switch, the inverse output of the third trigger is connected to the second input of the third OR element and the first and second control inputs

элемента ИЛИ, выход которого соединен с R-входом первого триггера, выход третьего элемента И соединен с S-входом третьего триггера и вторымиthe OR element, the output of which is connected to the R input of the first trigger; the output of the third element AND is connected to the S input of the third trigger and the second

первого коммутатора, S и R-входы тре- 0 входами первого и третьего элементовthe first switch, S and R-inputs are three- 0 inputs of the first and third elements

ИЛИ, первые входы первого, второго и третьего элементов И вл ютс соответственно первым, вторым и третьим входами блока, вторые входы первого,OR, the first inputs of the first, second and third elements AND are respectively the first, second and third inputs of the unit, the second inputs of the first,

тьего триггера вл ютс соответственно первым и вторым входами управлени преобразовател .The second trigger are respectively the first and second control inputs of the converter.

2. Преобразователь по п. отличающийс тем, что дешифра-дз второго и третьего элементов И объ- тор выполнен на формировател х сигналов , элементах ИЛИ, элементе И и эле- менте НЕ, первый, второй и третий выходы первого формировател сигналов2. The converter according to claim. 2, in which the decryption-dz of the second and third elements of the AND circuit is made on the signal conditioners, the OR elements, the AND element and the HE element, the first, second and third outputs of the first signal conditioner.

динены и вл ютс четвертым входом блока, выходы первого, второго и тре тьего триггеров вл ютс соответственно первым, вторым и третьим выходthe dinene and are the fourth input of the block, the outputs of the first, second and third flip-flops are respectively the first, second and third outputs

соединены с первыми входами соответст-jQ ми блока.connected to the first inputs of the corresponding-jQ mi block.

второго и третьего элементов И объ- the second and third elements and

динены и вл ютс четвертым входом блока, выходы первого, второго и третьего триггеров вл ютс соответственно первым, вторым и третьим выходаСоставитель Б„Ходов Редактор А.Лежнина ТехредМ.ДидыкThe dinenes are the fourth input of the block, the outputs of the first, second and third flip-flops are the first, second and third outputs, respectively. Compiler B H. Editor A. Lezhnina Tehred.Mididyk

Фив. 2Thebes. 2

фиг.Зfig.Z

Корректор А. ОбручарProofreader A. Obruchar

Claims

Claim

1. A code converter containing 1 pulse generator, AND elements, OR elements, triggers, a first switch, a register, the outputs of which are connected to the corresponding inputs of the decoder, the outputs of which are connected by the inputs of the first OR element, comparison comparison, the output of which is connected by the first input of the first AND element whose output is connected to the R-input of the first trigger, the element is NOT, the output of which is connected to the first input of the second element And, the information inputs of the register are the information input of the converter, characterized in that In order to expand the scope of the converter by providing both direct conversion of non-register codes to multi-register and vice versa, a pulse distributor, second and third switches, a memory block and a block of register signs, the first, second and third outputs of which are connected to the corresponding first inputs of the comparison unit and the information inputs of the first switch, the outputs of which are connected to the first address inputs of the memory unit, the output of which is the first in During the operation of the converter, the first, second and third inputs of the register feature block are combined with the corresponding second inputs of the comparison unit, the information inputs of the second switch and connected to the corresponding outputs of the decoder, the information inputs of the third switch are connected to the corresponding outputs of the register, the outputs of the second and third switches are connected respectively to the second and the third address inputs of the memory block, the output of the pulse generator is connected

1547075 U with an input of a pulse distributor, the first output of which is connected to the first input of the third AND element and the R-input of the second trigger, whose inverse output is connected to the first input of the second OR element, whose output is connected to the first input of the fourth AND element, whose output is connected to the input control unit of the memory, the second output of the pulse distributor is connected to the second inputs of the first and second elements And, the third and fourth outputs of the pulse distributor are connected respectively to the second input of the fourth element And the fourth input of the block of register signs, the input of the element is NOT connected to the output of the comparison unit, the output of the second element And is connected to the S-input of the first 2θ trigger, the direct output of which is connected to the first control input of the second switch, the inverse output of the first trigger is connected to the first input of the third OR element, the output of which 25 is connected to the first and second inputs of the third switch and the second input of the third AND element, the output of which is connected to the installation input of the register and is the second output of the converter q of the first OR element is connected to the S-input of the second trigger, the direct output of the third trigger is connected to the second input of the second OR element and the second control input of the second switch, the inverse output of the third trigger is connected to the second input of the third OR element and the first and second control inputs of the first switch, the S and R inputs of the third trigger are the first and second control inputs of the converter, respectively.

2. The converter according to claim. ^ Characterized in that the decryptor ad 5 tor is made on signal conditioners, OR elements, AND element and NOT element, the first, second and third outputs of the first signal conditioner are connected to the first inputs of the And element respectively , of the first and second OR elements, the outputs of the AND element and the first OR element are connected to the first inputs of the third and fourth OR elements, respectively, the outputs of the second signal conditioner are connected to the inputs of the fifth OR element, the output of which is connected directly to the second the input of the first OR element and through the element NOT with the second input of the AND element, the outputs of the third signal conditioner are connected to the second inputs of the second, third and fourth OR elements, the outputs of which are the first, second and third outputs of the decoder, inputs of the first, second and third signal conditioners respectively combined and are the input of the decoder.

3. The Converter according to claim 1, characterized in that the block of register signs is made on OR elements, triggers and AND elements, the output of the first AND element is connected to the S-input of the first trigger and the first inputs of the first and second OR elements, the outputs of which are connected to R - inputs of the second and third triggers, respectively, the output of the second AND element is connected to the S-input of the second trigger, the second input of the second OR element and the first input of the third OR element, the output of which is connected to the R-input of the first trigger, the output of the third AND element is connected S-input of the third trigger and the second inputs of the first and third elements OR, the first inputs of the first, second and third elements AND are respectively the first, second and third inputs of the block, the second inputs of the first, second and third elements AND are combined and are the fourth input of the block, the outputs the first, second and third triggers are respectively the first, second and third outputs of the block.

·>

>

Fi g. 2