SU1532923A1 - Device for addition and subtraction of numbers by modulo - Google Patents

Abstract

The invention relates to automation and computing and can be used in computers and devices operating in the system of residual classes. The purpose of the invention is to increase speed. The goal is achieved by eliminating the information redundancy of the bits of the ring shift register storing the result of modular addition and subtraction operations by introducing into the device containing the decoders 3 and 11, subtractor 6, blocks 8.9 and 26 elements AND, block 10 elements OR, encoder 12, element OR 13, group of elements OR 14, receiving register 15, elements AND 16 and 18, ring shift register 19, prohibition elements 22 and 23, comparison circuit 24 and counter 25, HE element 17 with corresponding connections. 1 dw., 2 tab.

Description

Sl

WITH

to

with 1C

with

31532923

Comrade YI, block 10 elements OR, typed register 19, elements 22 and 23 rator 12, element OR 13, an ele-ban group, comparison circuit 24 and OR 14, receiving register 15, chick 25, NOT element 17 with the corresponding elements of And 16 and 18, annular shear ties. I or 0, 2 tabl „

I The invention relates to automation and computing and can be used in computers and devices operating in the system of residual classes.

The purpose of the invention is to increase speed.

The drawing shows a diagram of a device for adding and subtracting modulo numbers

The device contains the first information input 1 of the device, the input 2 of the device addition task, the first decoder 3, the second information input 4 of the device, the input 5 of the device subtraction task, the lever 6, the input, 7 tasks of the device module, the first 8 and the second 9 blocks of elements And , block 10 elements OR, second decoder 11, encoder 12, element OR 13, group of elements OR 14, receiving register 15, first element AND 16, element NOT 17, second element AND 18, ring shift register 19, clock input 20 of the device , output 21 of the device, the first 22 and second 23 ale Banners of the prohibition 5 scheme 24 comparison, counter 25 and the third block 26 elements I.

The device works as follows,

In binary code, input 1 receives operand A, input 4 receives operand B, which also arrives at the input of the subtractor 6 modulo t, the output of which receives the value (uv-B). The signal + from input 2 opens the first block of 8 elements AND, through which and through the block of 10 elements OR the operand B enters the input of the second decoder 11. From the output of the second decoder 11, the operand B in the unitary code goes to the first group of inputs of the encoder 12, to the second group of inputs of which is supplied through the first decoder 3 operand A. Depending on the ratio of operands A and B, a binary number is formed at the outputs of the elements OR 14 of the group, corresponding to

five

0

50

5 Q e

five

0

The number of register shifts is 19, and the output of the OR element 13 is a signal if the direction of shift is right. The signal from the output of the element OR 13 goes to the first input of element AND 16, and if there is no signal, then element 18 opens, providing the left direction of shift. From the entrance 20 to the inputs of the open elements 22 and 23 of the ban impulses arrive. When the states of the counter 25 and the receive register 15 match, the comparison circuit 24 outputs a signal that closes the inhibit elements 22 and 23 and opens the AND block 26, through which the value of the bit group of the register 19 (the result of the modular addition operation) enters the output 2J of the device .

Let it be necessary to determine the result (AB) modm. In this case, the signal from input 5 goes to the second block 9 of the elements I. And from the output of the subtractor 6, the value () through the open, second block 9 of the elements I, block 10. elements OR goes to the second decoder 11. Further operation of the device is similar to the definition of the result of the operation of modular addition.

Consider examples of the specific implementation of the modular addition and subtraction operation for.

The initial state of the register is 19: g - 0 -. 1 - 1-0-0-0-1 The first three bits correspond to the number 5W. The number 3 corresponds to the shift of the register to the left by one binary bit q / 2 - to the right by one bit bit, etc. We create a table for the implementation of the modular addition operation. Table 1 shows the results of the modular addition operation.

TabLo2 for building the encoder 12 reflects the required number of shift cycles for each pair of operands A and B and the direction of the shift. The shift to the left corresponds to the positive direction of the shift and is reflected in the table by the sign +

Consequently, the group of elements OR 14 in this case consists of two elements that form four variants of numbers: 00, 01, 10, 11. The element OR 13 combines the outputs of the switch, which are labeled in Table 2 with the - sign.

Example 1.,. It is necessary to define (A + B) modtn. The first operand is fed to the first decoder 3, from the output of which is fed to the first input of the second group of inputs of the encoder 12 “Operand B through the first block of 8 elements AND and the block of 10 elements OR comes to the second decoder. torus 11. From the output of the second decoder 11 enters the third input of the first group of inputs of the encoder 12. Device for adding and subtracting numbers modulo the first and second decoders, subtractor, receiving register, comparison circuit, counter, ring shift register encoder, with first to third blocks of elements AND block of elements OR, first and second elements of prohibition, first 15 and second elements AND, group of elements OR and element OR, the first information input of the device is connected to the input of the first decoder, the second info The device's input input is connected to the first input of the first block of elements And and to the input of the subtracable subtractor, the input is decremented and you output which is connected respectively to the input of the module device assignment 20

thirty

The registered register 15 contains the number 01 according to Table 2. The signal from the output of the element OR 13 is not received, and the element And 12 signal. Imt pulses through open elements 22 and

23 prohibitions are received on the register shift and with the first input of the second block 19 and to the counter 25. At the time of the coincidence of the elements AND, the inputs of the addition and date of the register 15 and the counter

25 (in the counter 25 contains -

/ value 01) comparison circuit 24 generates a signal covering the elements

22 and 23 of the prohibition and the opening block of the 26 elements AND "The state of the register 19 is as follows: y-0 - 0 - 1 - 1 - 0 - Q-J

The contents of the first three bits of register 19 through block 26 elements AND

enters output 21. This is the result of the operation.

Example 2.,. You must define () modm. In this case, the first input of the second group of inputs of the encoder 12 receives a signal. The sixth input of the first group of inputs v of the encoder 12 also receives a signal (7-2 5). In the receiving register 15, the number 00 is recorded. The signal from the output of the element OR 13 does not arrive, and the circuit 45 Pa inputs the right shift offsets

Comparing 24 when the device is turned on, it generates a signal covering the prohibition elements 22 and 23 and the opening element block 26. Shift does not occur. Register state 19

40

and subtracting the device are connected respectively to the second inputs of the first and second blocks of the AND elements, the outputs of which are connected respectively to the first and second inputs of the block of OR elements, the output of which is connected to the input of the second decoder, the outputs of the receiving register and the counter are connected respectively to the first and second the inputs of the comparison circuit, the output of which is connected to the control inputs of the first and second prohibition elements, with the first input of the third block of elements And, the inputs of the bits of the second input of which are connected respectively tween the outputs, where m - the magnitude of modulation, LSBs annular shearing regist50

and to the left of which is connected respectively to the outputs of the first and second elements AND, the output of the OR element is connected to the first input of the first element AND, the clock input of the device is connected to the information inputs of the first and second prohibition elements, the output of the second prohibition element is connected to the counting input of the counter, o t- In order to improve speed, it contains the element NOT, and the output of the element OR through the element is NOT connected to the first input of the second element

the following: j-1 -0- 1 -1 - 0 - 0 - 0 |

The contents of the first three bits of register 19 represent the result of the modular subtraction operation

Thus, in the proposed device, simultaneously with a decrease in the number of binary bits of the register 19, the result is obtained directly in the rows of the register 19.

group of left times

Claims (1)

Invention Formula A device for adding and subtracting modulo numbers, containing the first and second decoders, subtractor, receiving register, comparison circuit, counter, ring shift register, encoder, first to third blocks of elements AND block of elements OR, first and second elements of prohibition, first 5 and the second elements AND, the group of elements OR and the element OR, the first information input of the device is connected to the input of the first decoder, the information input of the device is connected to the first input of the first block of the AND elements and is subtractably with the input a subtractor, and You are a minuend input whose output is connected respectively to the input setting unit ustroy0 and with the first input of the second block of elements And, the inputs of the task of adding and Pa Shift resolution inputs and subtracting the device are connected respectively to the second inputs of the first and second blocks of the AND elements, the outputs of which are connected respectively to the first and second inputs of the block of OR elements, the output of which is connected to the input of the second decoder, the outputs of the receiving register and the counter are connected respectively to the first and second the inputs of the comparison circuit, the output of which is connected to the control inputs of the first and second prohibition elements, with the first input of the third block of elements And, the inputs of the bits of the second input of which are connected respectively tween the outputs, where m - the magnitude of modulation, LSBs annular shearing regist0 five and to the left of which is connected respectively to the outputs of the first and second elements AND, the output of the OR element is connected to the first input of the first element AND, the clock input of the device is connected to the information inputs of the first and second prohibition elements, the output of the second prohibition element is connected to the counting input of the counter, o t- In order to improve speed, it contains the element NOT, and the output of the element OR through the element is NOT connected to the first input of the second element And the second input of which is combined with the BtopbiM input of the first element AND and connected to the output of the first prohibition element, the output of the third block of elements AND is the device output, the outputs of the second and first decoders are connected respectively to the inputs of the first and second encoder groups, the outputs of which are connected with the corresponding inputs of the OR element and the elements of the OR group, the outputs of the OR elements of the group are connected to the inputs of the corresponding receive bits stra0 Table 1 15 Table2