SU1649526A1 - Decimal-to-binary converter - Google Patents

Abstract

The invention relates to digital technology and can be used in automation, telemechanics and computer systems for converting the numbers specified by pressing keys on the remote from a decimal number system to a binary one. The purpose of the invention is to simplify the device and increase its reliability. The device contains a keyboard, five OR elements, a register, a comparison unit, three counters-1 ka, a pulse generator, a prohibition element, element I. The object of the invention is achieved by eliminating permanent memory devices with their control circuits from the composition of the device. 2 ill., 1 tab. S fc

Description

The invention relates to digital technology and can be used in h automation systems, telemechanics and computer technology for converting the numbers specified by pressing keys on the remote from a decimal number system to a digital binary code.

The purpose of the invention is to simplify the device and increase its reliability.

FIG. 1 shows a functional diagram of the device; in fig. 2 - signal plots explaining his work.

The device contains a keyboard 1, register 2, second 3, first 4 and three

5 counters, first 6, second 7, third 8, fourth 9 and fifth 5 OR elements, delay element 11, prohibition element 12, AND element 13, pulse generator 14 and comparison block 15.

Keyboard 1 is designed to set the number in the decimal number system by pressing them sequentially. Its nine outputs from the keys 1.0–1.9, according to the law of one decade, of code 8–4–2–1 are connected to the inputs of the first, second, third, and fourth elements OR.

Counter 5 is designed to form a number in code 8-4-2-1, equivalent to 3

a tape number in the decimal number system specified on keyboards

The device works as follows.

Initially, on the keyboard 1, the R key is pressed, which is achieved

the formation of a pulse UR (Fig 2). This pulse sets the elements of the device to the initial state. Then, the keys are sequentially pressed in accordance with the required number in the decimal numbering system, for example, 9781, i.e. ,

The signals from the information keys arrive at the corresponding inputs of the first 6, second 7, third 8 and fourth 9 elements OR, as shown in the table. The unit in this table means that the corresponding input of the i-th element OR the signal from the j-th key output (the unit is located at the intersection of the 1st element and the j-th key).

When the ninth key is pressed on block 1, a pulse 11- is formed, which is fed to the fifth input of the element OR 6 and to the second input of the element OR 9, passes through these elements and enters the first and fourth information inputs of the register 2, then the record in the first four bits of the register 2 are the numbers 1001,

The pulse U passes through the element OR 10 to the input of the delay element 11 which is delayed by the time the number is written to the register 2. From the output of the delay element 11, the pulse U is removed, which is supplied to the second input of the prohibition element 12 and since the inhibit signal on the second er the input is absent at the moment; it enters the register shift 2, which results in a shift of the contents of register 2 by four bits to the left.

The pulse from the output of the element 12 increases the content of the counter 4 by one.

After pressing the nine key, the seventh key is pressed, then the eighth key, and then the first key and the described process is repeated. Since after pressing the ninth key, the eighth, seventh and first keys are pressed successively, the pulses Ug, U7 and U. are removed from the corresponding keyboard output (Fig. 2). The time interval between adjacent keystrokes is much longer than the device operation time.

Therefore, the time axes on the graphs are broken, as indicated by dots. After pressing the last key (as applied to the considered example - the first), the register 2 contains the number 9781 in the binary-decimal code (UDQ), i.e. the number is 1001 0111 1000 0001, and in the counter 4 - the number of bits of the dialed number in the decimal number system (UCT). The presence in the corresponding register of register 2 and counter 4 units on the graphs is indicated by a vertical segment, and zero - by a point. The symbols shish denotes the number of bits of this register and counter.

0

five

0

five

five

0

five

0

Counter 4, together with element 13, is intended to form a prohibition signal 1 if the number of bits of the dialed number in the decimal number exceeds the allowable one.

After pressing the low-order key of the number in the decimal number system, press the S key. A pulse Uj is taken from the corresponding keyboard output, which is fed to the input of the generator 14 and starts it. Short-time pulses U are taken from the output of generator 14, which arrive at the counting inputs of counter 3 and counter 5. At the time when the contents of counter 5 become equal to the contents of register 2, a pulse U is removed from the output of comparison block 15, which is fed to the generator 14 and stops him. Thus, by the time U is generated, the contents of counter 3 in the digital binary code correspond to the number in the decimal number system, each digit of which is typed on the keyboard by successively pressing keys on it,

If the keyboard mistakenly dials a number in the decimal number system with the number of bits exceeding the maximum possible for which the device is designed (N), then at the moment the NMQli key is pressed; The discharge digit 4 is equal to N.AQ (tc, and the signal from the output of the element 13 is removed, which is fed to the first input of the prohibition element 12, the pulse U from the output of the element 11 does not pass through it.

Claims (1)

Formula of five arr 1649526 A device for converting numbers from decimal1 to binary numbering system, comprising a keyboard, first, second, third and fourth OR elements, a prohibition element and a register, the first information input of which is connected through the first OR element to the first, third, fifth, the seventh and ninth keyboard outputs, the second through the second element OR with the third, fourth, seventh and eighth keyboard outputs, the third through the third element OR with the fifth, sixth, seventh and eighth keyboard outputs, the fourth through the fourth element OR nine The fifth and tenth keyboard outputs, the register reset input is connected to the twelfth keyboard output, characterized in that, in order to simplify the device and increase its reliability, three counters, a comparison unit, the And element, a delay element, a pulse generator are entered into it. the third element OR, whose inputs are connected to the first to ten keyboard outputs, the output of the first OR element, is connected to the second input of the prohibition element, the output of which is connected to the counting input of the first counter and the register shift input. whose outputs are connected Yu with the inputs of the element And whose output is connected to the first input of the prohibition element, the outputs of the register are connected to the inputs of the first group of the comparison unit, the output of which is connected to the first 5 input of the pulse generator, the second input of which is connected to the eleventh keyboard output the second and third counters are connected to the twelfth exit 20 of the keyboard, the output of the pulse generator is connected to the counting inputs of the second and third counters, the outputs of the second counter are information outputs of the device, the outputs of the third 25 of its counter is connected to the inputs of the second group of the comparator unit. 1649526